CN113993281B - PCB differential via hole design method and PCB design method - Google Patents
PCB differential via hole design method and PCB design method Download PDFInfo
- Publication number
- CN113993281B CN113993281B CN202111123554.7A CN202111123554A CN113993281B CN 113993281 B CN113993281 B CN 113993281B CN 202111123554 A CN202111123554 A CN 202111123554A CN 113993281 B CN113993281 B CN 113993281B
- Authority
- CN
- China
- Prior art keywords
- holes
- pair
- differential
- center
- layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 238000013461 design Methods 0.000 title claims abstract description 47
- 238000000034 method Methods 0.000 title claims abstract description 41
- 238000004458 analytical method Methods 0.000 claims description 3
- 238000004088 simulation Methods 0.000 claims description 3
- 208000015181 infectious disease Diseases 0.000 claims description 2
- 230000005540 biological transmission Effects 0.000 abstract description 4
- 238000004080 punching Methods 0.000 abstract description 3
- 238000004519 manufacturing process Methods 0.000 description 9
- 230000000694 effects Effects 0.000 description 3
- 238000004891 communication Methods 0.000 description 2
- 238000011960 computer-aided design Methods 0.000 description 2
- 238000012938 design process Methods 0.000 description 2
- 238000011161 development Methods 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 230000003071 parasitic effect Effects 0.000 description 2
- 238000012827 research and development Methods 0.000 description 2
- 238000006467 substitution reaction Methods 0.000 description 2
- 238000012795 verification Methods 0.000 description 2
- 238000003466 welding Methods 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000008878 coupling Effects 0.000 description 1
- 238000010168 coupling process Methods 0.000 description 1
- 238000005859 coupling reaction Methods 0.000 description 1
- 238000009826 distribution Methods 0.000 description 1
- 230000009977 dual effect Effects 0.000 description 1
- 230000005670 electromagnetic radiation Effects 0.000 description 1
- 230000002349 favourable effect Effects 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000004377 microelectronic Methods 0.000 description 1
- 238000005457 optimization Methods 0.000 description 1
- 150000003071 polychlorinated biphenyls Chemical class 0.000 description 1
- 238000007639 printing Methods 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
- H05K3/4038—Through-connections; Vertical interconnect access [VIA] connections
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/09—Shape and layout
- H05K2201/09209—Shape and layout details of conductors
- H05K2201/095—Conductive through-holes or vias
Landscapes
- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Structure Of Printed Boards (AREA)
- Design And Manufacture Of Integrated Circuits (AREA)
Abstract
The application provides a PCB differential via hole design method and a PCB design method, comprising the following steps: dividing the same-layer differential via hole combination into a first pair of holes and a second pair of holes, wherein the first pair of holes and the second pair of holes comprise two via holes, and setting the inner via hole spacing of the first pair of holes and the second pair of holes; the center connecting line of the first pair of holes forms an included angle of 45 degrees with the axis of the differential signal pin; and positioning a perpendicular bisector of the circle center connecting line of the first pair of holes, and creating a second pair of holes on the perpendicular bisector according to the set distance between the first pair of holes and the second pair of holes so that the circle center connecting line of the second pair of holes coincides with the perpendicular bisector. The application improves the design method of the differential via hole, and changes the punching mode of the differential via hole at the golden finger, thereby optimizing the crosstalk between high-speed signals, improving the signal integrity and improving the transmission quality of the high-speed signals.
Description
Technical Field
The application belongs to the technical field of layout design, and particularly relates to a PCB differential via design method and a PCB design method.
Background
With the development of electronic technology and the increase of signal rate, higher requirements are put on the performance of signals, and in the research and development process, research and development designers are required to more precisely consider and process many problems in the design process of PCBs, so as to achieve the minimization of cost on the basis of the optimization of performance.
In a high speed Printed Circuit Board (PCB), vias have been subject to problems in reducing signal integrity performance. However, the use of vias is unavoidable. On a standard PCB board, the components are placed on top and the traces of the differential pairs are on the inner layer. The electromagnetic radiation of the inner layer and the cross-talk between pairs are low. Vias must be used to connect components on the plane of the PCB to the inner layer. In the existing PCB design process, parallel punching is generally adopted in differential via design of devices such as gold fingers or connectors with high-speed differential lines. The space occupied by the via design is relatively large, signals in the horizontal direction interfere with each other, and when the signal rate becomes high, the transmission quality of high-speed signals is reduced. The vertical arrangement of the differential Kong Hengping in the prior art occupies a relatively large space, and in the horizontal direction, larger crosstalk exists between signals, so that the transmission of high-speed signals is not facilitated. And usually, an anti-pad needs to be dug in an inner layer, and due to space limitation, a 10-degree wiring of a differential signal is very easy to be very close to the edge of the anti-pad, even a complete GND plane cannot be referenced, and a cross-segmentation problem occurs.
Disclosure of Invention
In order to solve the above-mentioned shortcomings of the prior art, the present application provides a method for designing a differential via of a PCB and a method for designing a PCB, so as to solve the above-mentioned technical problems.
The application provides a PCB differential via design method, which comprises the following steps:
dividing the same-layer differential via hole combination into a first pair of holes and a second pair of holes, wherein the first pair of holes and the second pair of holes comprise two via holes, and setting the inner via hole spacing of the first pair of holes and the second pair of holes;
the center connecting line of the first pair of holes forms an included angle of 45 degrees with the axis of the differential signal pin;
and positioning a perpendicular bisector of the circle center connecting line of the first pair of holes, and creating a second pair of holes on the perpendicular bisector according to the set distance between the first pair of holes and the second pair of holes so that the circle center connecting line of the second pair of holes coincides with the perpendicular bisector.
Further, the method further comprises:
and creating a plurality of ground wire through holes according to the set minimum circle center distance between the ground wire through holes and the differential through holes and the principle that two differential through holes share one ground wire through hole preferentially.
Further, the method further comprises:
if two layers of differential via combinations exist, a coordinate system is established by taking the center point of the leftmost pin of one group of differential signal pins as an origin;
creating a first layer of differential signal via combinations on the coordinate system, wherein the via coordinates of the first layer of differential signal via combinations are respectively as follows Wherein a is the distance between the holes in the pair of holes, b is a set constant, c is the minimum distance between the center of the circle of the first pair of hole center connecting lines and the center of the circle of the second pair of holes combined by the same-layer differential holes;
creating a second level difference on the coordinate systemThe via coordinates of the second layer differential signal via combination are respectively as follows Wherein a is the distance between the through holes in the pair of holes, b is a set constant, c is the minimum distance between the center of the circle of the first pair of hole center connecting lines and the center of the circle of the second pair of holes combined by the same-layer differential through holes, and d is the minimum center distance between the ground wire through holes and the differential through holes.
Further, connecting lines of the differential vias and the differential pins are generated according to the set minimum distance between the wirings and the vias and the set minimum distance between the wirings.
Further, the via pitch a in the counter hole was set to 30mils.
Further, setting the minimum distance c between the center of the first pair of hole-center connecting lines and the center of the second pair of holes of the same-layer differential via hole combination as
Further, the first layer of differential signal via combinations are TX signal via combinations, and the second layer of differential signal via combinations are RX signal via combinations.
Further, simulation analysis is carried out on the differential via combination, signal infection is obtained, and verification is carried out on the differential via combination scheme.
The application also provides a PCB design method, which is used for designing the differential via hole of the PCB.
The PCB differential via hole design method and the PCB design method have the beneficial effects that the same-layer differential via hole combination is divided into the first pair of holes and the second pair of holes, the first pair of holes and the second pair of holes comprise two via holes, and the inner via hole spacing of the first pair of holes and the second pair of holes is set; making the center connecting line of the first pair of holes form an included angle of 45 degrees with the axis of the differential signal pin; and positioning a perpendicular bisector of the circle center connecting line of the first pair of holes, and creating a second pair of holes on the perpendicular bisector according to the set distance between the first pair of holes and the second pair of holes so that the circle center connecting line of the second pair of holes coincides with the perpendicular bisector. The application improves the design method of the differential via hole, and changes the punching mode of the differential via hole at the golden finger, thereby optimizing the crosstalk between high-speed signals, improving the signal integrity and improving the transmission quality of the high-speed signals. The design method of the differential via hole for reducing crosstalk saves the space of PCB design. Moreover, due to the short wiring distance, the uncoupling length of DP and DN is short, and the wiring space is sufficient, so that the problem of cross-segmentation is avoided.
In addition, the application has reliable design principle, simple structure and very wide application prospect.
Drawings
In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings that are required to be used in the description of the embodiments or the prior art will be briefly described below, and it will be obvious to those skilled in the art that other drawings can be obtained from these drawings without inventive effort.
Fig. 1 is an exemplary flow chart of a method of PCB differential via design in accordance with one embodiment of the present application.
Fig. 2 is an exemplary schematic diagram of a PCB differential via design method in accordance with one embodiment of the present application.
Fig. 3 is an exemplary effect diagram of a PCB differential via design method according to one embodiment of the present application.
Wherein, 1, a first pair of holes; 2. a second pair of holes; 3. ground wire via holes; 4. differential signal pins; 5. the signal pins are grounded.
Detailed Description
In order to make the technical solution of the present application better understood by those skilled in the art, the technical solution of the present application will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present application, and it is apparent that the described embodiments are only some embodiments of the present application, not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the present application without making any inventive effort, shall fall within the scope of the present application.
It should be noted that, without conflict, the embodiments of the present application and features of the embodiments may be combined with each other.
In the description of the present application, it should be understood that the terms "first," "second," and the like are used for descriptive purposes only and are not to be construed as indicating or implying a relative importance or number of technical features indicated. Thus, a feature defining "a first", "a second", etc. may explicitly or implicitly include one or more such feature. In the description of the present application, unless otherwise indicated, the meaning of "a plurality" is two or more.
In the description of the present application, it should be noted that, unless explicitly specified and limited otherwise, the terms "mounted," "connected," and "connected" are to be construed broadly, and may be either fixedly connected, detachably connected, or integrally connected, for example; can be mechanically or electrically connected; can be directly connected or indirectly connected through an intermediate medium, and can be communication between two elements. The specific meaning of the above terms in the present application can be understood by those of ordinary skill in the art in a specific case.
Layout design is a mask design that is performed according to the requirements of the microelectronic technology circuit and its manufacturing process. Layout designs generally involve two interrelated design steps of layout (placement of circuit elements, devices) and routing (interconnection of circuit elements, devices). The main task of the layout design is to complete the arrangement of circuit elements, devices and the necessary interconnections between the elements according to given manufacturing process conditions, ensuring: the chip has higher layout density; the interconnection meets the electrical performance requirements (such as load capacity and the like) of the elements and the devices; the effect of interconnect-generated parasitics (e.g., interconnect parasitic capacitance, etc.) is within the design requirements and takes into account design manufacturing cycles, design correctness verification, design costs, etc.
PCB (Printed Circuit Board) the Chinese name printed circuit board, also called printed circuit board, is an important electronic component, is a support for electronic components, and is a carrier for electrically interconnecting electronic components. It is called a "printed" circuit board because it is made using electronic printing. PCB (printed circuit board), a printed wiring board, is one of the important components of the electronics industry. Almost every electronic device, as small as an electronic watch, a calculator, as large as a computer, a communication electronic device, a military weapon system, has only electronic components such as an integrated circuit, and a printed board is used for electrically interconnecting the respective components. The printed circuit board consists of an insulating base plate, connecting wires and bonding pads for assembling and welding electronic elements, and has the dual functions of a conductive circuit and the insulating base plate. The wiring device can replace complex wiring, realizes electric connection among elements in a circuit, simplifies assembly and welding work of electronic products, reduces wiring workload in a traditional mode, and greatly lightens labor intensity of workers; and the whole volume is reduced, the product cost is reduced, and the quality and the reliability of the electronic equipment are improved. The printed circuit board has good product consistency, can adopt standardized design, and is favorable for realizing mechanization and automation in the production process. Meanwhile, the whole printed circuit board subjected to assembly and debugging can be used as an independent spare part, so that the whole machine product can be conveniently exchanged and maintained. At present, the printed wiring board has been extremely widely applied to the production and manufacture of electronic products. The earliest printed wiring boards were paper-based copper-clad printed boards. Since the advent of semiconductor transistors in the 50 s of the 20 th century, the demand for printed boards has increased dramatically. Particularly, the rapid development and wide application of integrated circuits make electronic devices smaller and smaller, and circuit wiring density and difficulty are larger and larger, which requires the printed board to be updated continuously. The variety of printed boards has evolved from single-sided boards to double-sided boards, multi-layer boards, and flexible boards; structure and quality have also evolved to ultra high density, miniaturization and high reliability levels; new design methods, design supplies, board manufacturing materials and board manufacturing processes are continuously emerging. In recent years, various Computer Aided Design (CAD) printed wiring board applications have been popular and popularized in the industry, and in specialized printed board manufacturers, mechanical and automated production has completely replaced manual operations.
The application will be described in detail below with reference to the drawings in connection with embodiments.
Example 1
Referring to fig. 1 and 2, the present embodiment provides a method for designing a differential via of a PCB, which includes the following steps:
s1, dividing the same-layer differential via hole combination into a first pair of holes 1 and a second pair of holes 2, wherein the first pair of holes 1 and the second pair of holes 2 comprise two via holes, and the internal via hole spacing of the first pair of holes 1 and the second pair of holes 2 is set;
s2, forming an included angle of 45 degrees between the circle center connecting line of the first pair of holes 1 and the axis of the differential signal pin 4;
s3, positioning a perpendicular bisector of a circle center connecting line of the first pair of holes 1, and creating a second pair of holes 2 on the perpendicular bisector according to the set distance between the first pair of holes 1 and the second pair of holes 2 so that the circle center connecting line of the second pair of holes 2 coincides with the perpendicular bisector.
Example 2
The present embodiment provides a method for designing a differential via of a PCB, please refer to fig. 3, including:
if two layers of differential via combinations exist, taking the differential via of the golden finger as an example, a coordinate system is established by taking the center point of the leftmost pin of the group of differential signal pins 4 as an origin.
Creating a first layer of differential signal via combinations (TX differential vias) on a coordinate system, wherein the via coordinates of the first layer of differential signal via combinations are respectively Wherein a is the distance between the through holes in the pair of holes, b is a set constant, c is the minimum distance between the connecting line of the circle centers of the first pair of holes 1 and the circle centers of the second pair of holes 2 combined by the same-layer differential through holes;
creating a second tier differential signal via on a coordinate systemCombinations (RX differential vias) in which the via coordinates of the second layer differential signal via combinations are respectively Wherein a is the distance between the through holes in the pair of holes, b is a set constant, c is the minimum distance between the connecting line of the circle centers of the first pair of holes 1 and the circle centers of the second pair of holes 2 combined by the same-layer differential through holes, and d is the minimum circle center distance between the ground wire through hole 3 and the differential through hole.
Wherein, the spacing a of the through holes in the opposite holes is set to be 30mils; setting the minimum distance c between the circle center connecting line of the first pair of holes 1 and the circle center of the second pair of holes 2 of the same-layer differential via hole combination asI.e., the minimum distance of the centers of the circles of the first pair of holes 1 from the centers of the circles of the second pair of holes 2 is 40mils.
And generating connecting lines of each differential via hole and the differential pin according to the set minimum distance between the wirings and the via holes and the set minimum distance between the wirings.
After all differential via holes and connecting wires of the differential via holes and the differential pins are generated, a plurality of ground wire via holes 3 are created according to the set minimum circle center distance between the ground wire via holes 3 and the differential via holes and the principle that one ground wire via hole 3 is shared by two differential via holes preferentially. Under the principle, the number of the ground wire through holes 3 can be reduced as much as possible, and the distribution area of the ground wire through holes 3 can be reduced, so that the effect of saving the space of the PCB is realized. Finally, a connecting wire of the ground wire through hole 3 and the grounding signal pin 5 is generated.
As shown in fig. 3, the lower two pairs of differential vias a and B are TX signals, the upper two pairs of differential vias C, D are RX signals, and the remaining vias are GND-accompanying reflow holes. The center-to-center distance between differential vias DP and DN is 30mils, differential pair via B is on the perpendicular bisector of differential pair via a, and the center-to-center distance of differential pair via B to differential pair via a is 40mils. Similarly, the differential pair via D is on the perpendicular bisector of the differential pair via C and the center distance of the differential pair via D to the differential pair via C is 40mils.
Simulation analysis is carried out on a common differential via parallel design mode and a differential via design mode for reducing crosstalk at the golden finger, so that signal crosstalk is checked, the signal crosstalk of the common differential via parallel design mode is about-46 dB@16GHz, and the signal crosstalk of the differential via design mode for reducing crosstalk is about-39 dB@16GHz. The design method of the differential via hole for reducing crosstalk is more optimized in terms of crosstalk.
From the aspect of PCB design space, the space occupied by the common differential via parallel design mode at the golden finger is 5.35mm from Pin of the golden finger to the uppermost via, while the space occupied by the differential via design mode of the embodiment is 4.15mm from Pin of the golden finger to the uppermost via. The space of the PCB layout wiring is saved.
For the common design mode of the differential via holes at the golden finger, the problem of cross-segmentation of the 10-degree reference anti-pad is easy to occur due to insufficient space; for the design method of the embodiment, the wiring distance is short, the coupling length between DP and DN is short, and the wiring space is sufficient, so that the phenomenon of cross-segmentation is avoided.
Although the present application has been described in detail by way of preferred embodiments with reference to the accompanying drawings, the present application is not limited thereto. Various equivalent modifications and substitutions may be made in the embodiments of the present application by those skilled in the art without departing from the spirit and scope of the present application, and it is intended that all such modifications and substitutions be within the scope of the present application/be within the scope of the present application as defined by the appended claims. Therefore, the protection scope of the present application shall be subject to the protection scope of the claims.
Claims (8)
1. The PCB differential via design method is characterized by comprising the following steps:
dividing the same-layer differential via hole combination into a first pair of holes and a second pair of holes, wherein the first pair of holes and the second pair of holes comprise two via holes, and setting the inner via hole spacing of the first pair of holes and the second pair of holes;
the center connecting line of the first pair of holes forms an included angle of 45 degrees with the axis of the differential signal pin;
positioning a perpendicular bisector of a circle center connecting line of the first pair of holes, and creating a second pair of holes on the perpendicular bisector according to the set distance between the first pair of holes and the second pair of holes so that the circle center connecting line of the second pair of holes coincides with the perpendicular bisector;
the method further comprises the steps of:
if two layers of differential via combinations exist, a coordinate system is established by taking the center point of the leftmost pin of one group of differential signal pins as an origin;
creating a first layer of differential signal via combinations on the coordinate system, wherein the via coordinates of the first layer of differential signal via combinations are respectively as follows Wherein a is the distance between the holes in the pair of holes, b is a set constant, c is the minimum distance between the center of the circle of the first pair of hole center connecting lines and the center of the circle of the second pair of holes combined by the same-layer differential holes;
creating a second-layer differential signal via combination on the coordinate system, wherein via coordinates of the second-layer differential signal via combination are respectively as follows Wherein a is the distance between the through holes in the pair of holes, b is a set constant, c is the minimum distance between the center of the circle of the first pair of hole center connecting lines and the center of the circle of the second pair of holes combined by the same-layer differential through holes, and d is the minimum center distance between the ground wire through holes and the differential through holes.
2. The method according to claim 1, wherein the method further comprises:
and creating a plurality of ground wire through holes according to the set minimum circle center distance between the ground wire through holes and the differential through holes and the principle that two differential through holes share one ground wire through hole.
3. The method of claim 1, wherein the connection lines of each differential via and differential pin are generated based on a set minimum distance between the traces and the vias and a set minimum spacing between the traces.
4. The method of claim 1 wherein the via pitch a in the pair of holes is set to 30mils.
5. The method of claim 1, wherein the minimum distance c between the center of the first pair of hole connecting lines and the center of the second pair of holes of the same-layer differential via combination is set as
6. The method of claim 1, wherein the first layer of differential signal via combinations are TX signal via combinations and the second layer of differential signal via combinations are RX signal via combinations.
7. The method of claim 1, wherein the differential via combination is subjected to a simulation analysis to obtain a signal infection, and wherein the differential via combination scheme is verified.
8. A method of designing a PCB, characterized in that the method is used to design a differential via of a PCB using the method of any of claims 1-7.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202111123554.7A CN113993281B (en) | 2021-09-24 | 2021-09-24 | PCB differential via hole design method and PCB design method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202111123554.7A CN113993281B (en) | 2021-09-24 | 2021-09-24 | PCB differential via hole design method and PCB design method |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN113993281A CN113993281A (en) | 2022-01-28 |
| CN113993281B true CN113993281B (en) | 2023-08-22 |
Family
ID=79736541
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202111123554.7A Active CN113993281B (en) | 2021-09-24 | 2021-09-24 | PCB differential via hole design method and PCB design method |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN113993281B (en) |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1870852A (en) * | 2005-05-28 | 2006-11-29 | 鸿富锦精密工业（深圳）有限公司 | Printed circuit board with improved differential via |
| CN107220442A (en) * | 2017-05-31 | 2017-09-29 | 郑州云海信息技术有限公司 | A kind of difference through hole for PCB is to detection instrument |
| CN109815570A (en) * | 2019-01-15 | 2019-05-28 | 郑州云海信息技术有限公司 | A method of it checks and whether there is cabling between differential signal via hole |
| CN111970835A (en) * | 2020-09-17 | 2020-11-20 | 苏州浪潮智能科技有限公司 | Differential via hole and method, system, equipment and medium for manufacturing differential via hole |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US9971864B2 (en) * | 2016-07-22 | 2018-05-15 | Hewlett Packard Enterprise Development Lp | Symmetry verifications for differential signal vias of an electronic circuit design |
-
2021
- 2021-09-24 CN CN202111123554.7A patent/CN113993281B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1870852A (en) * | 2005-05-28 | 2006-11-29 | 鸿富锦精密工业（深圳）有限公司 | Printed circuit board with improved differential via |
| CN107220442A (en) * | 2017-05-31 | 2017-09-29 | 郑州云海信息技术有限公司 | A kind of difference through hole for PCB is to detection instrument |
| CN109815570A (en) * | 2019-01-15 | 2019-05-28 | 郑州云海信息技术有限公司 | A method of it checks and whether there is cabling between differential signal via hole |
| CN111970835A (en) * | 2020-09-17 | 2020-11-20 | 苏州浪潮智能科技有限公司 | Differential via hole and method, system, equipment and medium for manufacturing differential via hole |
Also Published As
| Publication number | Publication date |
|---|---|
| CN113993281A (en) | 2022-01-28 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US11800636B2 (en) | Electronic substrate having differential coaxial vias | |
| US6817870B1 (en) | Technique for interconnecting multilayer circuit boards | |
| US8958214B2 (en) | Motherboard assembly for interconnecting and distributing signals and power | |
| CN113573463B (en) | Circuit board | |
| EP3641510B1 (en) | Systems and methods for providing a high speed interconnect system with reduced crosstalk | |
| US7402757B1 (en) | Method, system, and apparatus for reducing transition capacitance | |
| US20050251777A1 (en) | Method and structure for implementing enhanced electronic packaging and PCB layout with diagonal vias | |
| CN113993281B (en) | PCB differential via hole design method and PCB design method | |
| WO2023019824A1 (en) | Substrate and packaging structure thereof | |
| CN112312644B (en) | Printed circuit board connection of integrated circuits using two wiring layers | |
| CN113678574B (en) | Packaging device for common mode rejection and printed circuit board | |
| CN114189987A (en) | PCB and manufacturing method thereof | |
| US9245828B2 (en) | High speed signal conditioning package | |
| CN213305847U (en) | PCB structure for optimizing via hole crosstalk in BGA | |
| CN219678793U (en) | Printed circuit board and wiring structure thereof | |
| CN214338207U (en) | Improved circuit board structure | |
| CN213847133U (en) | Reduce multilayer circuit board structure of thickness | |
| EP3799537A1 (en) | Reversible electronic card and method of implementation thereof | |
| CN114269063B (en) | PCB interconnection structure and method | |
| KR101886723B1 (en) | Ground routing device and method | |
| CN221058483U (en) | Wiring structure for reducing signal crosstalk in PCB | |
| CN221178002U (en) | Circuit board and electronic device | |
| CN214177635U (en) | Printed circuit board | |
| CN220511308U (en) | Memory chip PCB board, memory chip and processor | |
| TWI727651B (en) | Multilayer circuit board |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |