KR100780093B1 - Manufacturing method for printed circuit board having non-plate pattern - Google Patents

Manufacturing method for printed circuit board having non-plate pattern Download PDF

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Publication number
KR100780093B1
KR100780093B1 KR1020060065066A KR20060065066A KR100780093B1 KR 100780093 B1 KR100780093 B1 KR 100780093B1 KR 1020060065066 A KR1020060065066 A KR 1020060065066A KR 20060065066 A KR20060065066 A KR 20060065066A KR 100780093 B1 KR100780093 B1 KR 100780093B1
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South Korea
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gold
resist
nickel layer
printed circuit
circuit board
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KR1020060065066A
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Korean (ko)
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임철홍
정경상
유영남
김남희
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주식회사 코리아써키트
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    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/10Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern
    • H05K3/12Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern using thick film techniques, e.g. printing techniques to apply the conductive material or similar techniques for applying conductive paste or ink patterns
    • H05K3/1275Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern using thick film techniques, e.g. printing techniques to apply the conductive material or similar techniques for applying conductive paste or ink patterns by other printing techniques, e.g. letterpress printing, intaglio printing, lithographic printing, offset printing
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/02Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding
    • H05K3/06Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding the conductive material being removed chemically or electrolytically, e.g. by photo-etch process
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/10Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern
    • H05K3/20Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern by affixing prefabricated conductor pattern
    • H05K3/205Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern by affixing prefabricated conductor pattern using a pattern electroplated or electroformed on a metallic carrier

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  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing Of Printed Wiring (AREA)

Abstract

A method for manufacturing a printed circuit board without a plating pattern is provided to improve a design flexibility and increase a wiring density by using a nickel layer instead of a chemical copper. A method for manufacturing a printed circuit board without a plating pattern includes the steps of: forming a circuit pattern by compressing a dry film on a board to which a copper plate is attached(S10); forming a nickel layer on the board in which the circuit patter is formed(S20); selectively applying a gold resist on the nickel layer(S30); selectively forming a gold-coated layer on a top surface of the nickel layer to which the gold resist is not applied(S40); stripping the gold resist(S50); and stripping the nickel layer exposed to the outside(S70) after the gold resist stripping step. The method for manufacturing the printed circuit board without a plating pattern further includes the steps of insulating and protecting the circuit pattern from the outside by selectively applying a solder resist(S90) after the nickel layer stripping step.

Description

도금선이 없는 인쇄회로기판의 제조방법{Manufacturing method for printed circuit board having non-plate pattern}Manufacturing method for printed circuit board having non-plate pattern}

도 1은 본 발명의 바람직한 실시예에 따른 도금선이 없는 인쇄회로기판의 제조과정을 나타내는 흐름도,1 is a flow chart showing a manufacturing process of a printed circuit board without a plating line according to a preferred embodiment of the present invention;

도 2a 내지 도 2i는 도 1의 제조방법을 단계적으로 도시한 도면이다.2A to 2I are diagrams illustrating in step the manufacturing method of FIG.

<도면 주요 부분에 대한 부호의 설명><Explanation of symbols for the main parts of the drawings>

110 : 기판 120 : 회로패턴110: substrate 120: circuit pattern

130 : 니켈 층 140 : 금 레지스트130: nickel layer 140: gold resist

150 : 금도금 층 160 : 금도금 보호용 레지스트150: gold plated layer 160: gold plated protective resist

170 : 솔더레지스트170: solder resist

본 발명은 인쇄회로기판의 제조방법에 관한 것으로, 보다 구체적으로는 도금선이 없는 인쇄회로기판의 제조방법에 관한 것이다.The present invention relates to a method for manufacturing a printed circuit board, and more particularly, to a method for manufacturing a printed circuit board without a plating line.

일반적으로 반도체 패키지는 회로패턴이 형성된 인쇄회로기판에 반도체 칩을 부착시키고, 반도체 칩 상의 입출력 패드인 본딩패드와 인쇄회로기판 상에 형성된 본딩핑거를 도전성 와이어로 연결하고, 상기 인쇄회로기판 상의 반도체 칩, 도전성 와이어, 회로패턴 등을 외부의 환경으로부터 보호하기 위해 상부면을 몰딩 수지로 몰딩하여 형성된다. 여기서, 상기 반도체 칩의 본딩패드와 와이어로 연결되는 인쇄회로기판 상의 본딩 핑거는 구리 재질로 이루어져 있다. 그러나, 구리층은 와이어 본딩이 직접 물리적, 화학적으로 결합하기 힘들어 금도금을 해주는데, 이 금도금만으로는 화학적 내식성이나 두께, 가격 측면에서 적절치 않기 때문에 구리층과 금도금 공정 중간에 니켈도금을 하고 있다.In general, a semiconductor package attaches a semiconductor chip to a printed circuit board on which a circuit pattern is formed, connects a bonding pad, which is an input / output pad on the semiconductor chip, and a bonding finger formed on the printed circuit board, with a conductive wire, and the semiconductor chip on the printed circuit board. In order to protect the conductive wire, the circuit pattern, and the like from the external environment, the upper surface is formed by molding the molding resin. Here, the bonding finger on the printed circuit board connected to the bonding pad and the wire of the semiconductor chip is made of a copper material. However, the copper layer is gold plated because wire bonding is difficult to directly bond physically and chemically. Since gold plating alone is not suitable for chemical corrosion resistance, thickness, and price, nickel is plated between the copper layer and the gold plating process.

종래의 니켈/금도금 처리 방법은, 기판에 동을 입힌 후 드라이필름을 이용하여 회로패턴 및 도금용 리드선이 형성될 부분을 제외한 부분의 동을 외부로 노출시킨다. 그 후 외부로 노출된 동을 제거하고, 드라이필름을 스트립하여 원하는 패턴을 얻었다. 또한, 금도금 영역을 제외하고 솔더레지스트를 도포한 후 전기 도금을 수행하여 니켈/금도금 층을 형성시켰다. In the conventional nickel / gold plating treatment method, copper is coated on a substrate and then exposed to the outside of copper except for a portion where a circuit pattern and a plating lead wire are to be formed using a dry film. Thereafter, copper exposed to the outside was removed, and the dry film was stripped to obtain a desired pattern. In addition, after the solder resist was applied except for the gold plating region, electroplating was performed to form a nickel / gold plating layer.

하지만, 상술한 종래 기술은 니켈/금도금을 실시하기 위해 회로패턴과 무관한 도금 인입선이 꼭 필요하고, 이처럼 인쇄회로기판에 잔존하는 도금 인입선은 회로설계시 도금 인입선이 없는 부위에만 회로를 배치할 수 있으므로 회로설계의 자유도를 저하시키므로, 미세회로를 만드는데 한계가 있다. 또한, 이 도금 인입선은 데이터 통신의 고속화에 따른 고주파수 환경에서 일종의 도체 역할을 수행하므로, 안테나와 같은 역할을 하여 기생 인덕턴스를 발생시킨다. 이러한 기생 인덕턴스는 회로 상의 전기 신호와 간섭작용을 일으켜 임피던스 부정합을 우발하므로, 최종 전자 제품의 전기적 성능을 저하시키는 문제점이 있었다. 또한, 기생 인덕턴스로 인 하여 최종 전자 제품의 신호 대 잡음 비율이 악화되고, 갑작스러운 최종 전자 제품의 오작동 등으로 제품의 신뢰도를 저하시키는 문제점이 있다.However, the above-described prior art requires a plating lead wire irrelevant to the circuit pattern to perform nickel / gold plating, and thus, the plating lead wire remaining on the printed circuit board may be disposed only at a portion where there is no plating lead wire in the circuit design. Therefore, since the degree of freedom of circuit design is reduced, there is a limit to making a fine circuit. In addition, the plating lead wire serves as a kind of conductor in a high frequency environment due to the high speed of data communication, and thus acts as an antenna to generate parasitic inductance. Since the parasitic inductance interferes with the electrical signal on the circuit to cause impedance mismatch, there is a problem of lowering the electrical performance of the final electronic product. In addition, due to parasitic inductance, the signal-to-noise ratio of the final electronic product is deteriorated, and the reliability of the product is lowered due to sudden malfunction of the final electronic product.

본 발명은 상술한 문제점을 해결하기 위하여 창출된 것으로, 니켈/금도금을 위한 도금선을 없앰으로써 신뢰도가 향상된 인쇄회로기판의 제조방법을 제공하는데 그 목적이 있다.SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and an object thereof is to provide a method of manufacturing a printed circuit board having improved reliability by eliminating plating lines for nickel / gold plating.

본 발명의 다른 목적 및 장점들은 하기에 설명될 것이며, 본 발명의 실시예에 의해 알게 될 것이다. 또한, 본 발명의 목적 및 장점들은 특허 청구 범위에 나타낸 수단 및 조합에 의해 실현될 수 있다.Other objects and advantages of the invention will be described below and will be appreciated by the embodiments of the invention. In addition, the objects and advantages of the present invention can be realized by means and combinations indicated in the claims.

상기와 같은 목적을 달성하기 위한 본 발명의 도금선이 없는 인쇄회로기판은, 반도체 패키지용 인쇄회로기판의 제조방법에 있어서, 동박이 부착된 기판에 드라이필름을 압착하여 회로패턴을 형성하는 회로패턴 형성 단계와; 상기 회로패턴이 형성된 기판 위에 전면적으로 니켈 층을 형성하는 니켈 층 형성 단계와; 상기 니켈 층 위에 금 레지스트를 선택적으로 도포하는 금 레지스트 도포 단계와; 상기 금 레지스트가 도포되지 않은 니켈 층의 상면에 선택적으로 금도금 층을 형성하는 금도금 단계와; 상기 금 레지스트를 전부 박리하는 금 레지스트 박리 단계; 및 상기 금 레지스트 박리 단계 이후 외부로 노출된 니켈 층을 전부 박리하는 니켈 층 제거 단계를 포함한다.In the printed circuit board without a plating line of the present invention for achieving the above object, a circuit pattern for forming a circuit pattern by pressing a dry film on a substrate with copper foil in the method of manufacturing a printed circuit board for semiconductor packages Forming step; Forming a nickel layer on the substrate on which the circuit pattern is formed; A gold resist coating step of selectively applying a gold resist on the nickel layer; A gold plating step of selectively forming a gold plating layer on an upper surface of the nickel layer to which the gold resist is not applied; A gold resist stripping step of peeling off all of the gold resist; And a nickel layer removing step of peeling off all of the nickel layers exposed to the outside after the gold resist peeling step.

여기서, 상기 니켈 층 제거 단계 이후, 솔더레지스트를 선택적으로 도포하여 회로패턴을 외부로부터 절연시키고 보호하는 솔더레지스트 도포 단계를 더 포함하는 것이 바람직하다.Here, after removing the nickel layer, it is preferable to further include a solder resist coating step of selectively applying a solder resist to insulate and protect the circuit pattern from the outside.

또한, 상기 니켈 층은 스퍼터링 방법으로 도포하는 것이 바람직하다.In addition, the nickel layer is preferably applied by a sputtering method.

더욱이, 상기 금 레지스트는 메쉬를 통한 실크스크린 방법을 통하여 선택적으로 도포하는 것이 바람직하다.Moreover, the gold resist is preferably applied selectively through the silkscreen method through the mesh.

게다가, 상기 선택적으로 도포된 금 레지스트의 가장자리를 레이저를 통하여 다듬을 수 있다.In addition, the edges of the selectively applied gold resist can be trimmed via a laser.

한편, 상기 니켈 층 제거 단계에 앞서 금도금 층을 보호하기 위한 금도금 보호용 레지스트를 상기 선택적으로 분포된 금도금 층의 상부에 형성시키는 금도금 보호용 레지스트 형성 단계; 및 상기 니켈 층 제거 단계 이후 상기 금도금 보호용 레지스트를 전부 박리하는 금도금 레지스트 박리 단계를 더 포함할 수 있다.Meanwhile, a gold plating protection resist forming step of forming a gold plating protection resist for protecting the gold plating layer prior to the nickel layer removing step on top of the selectively distributed gold plating layer; And a gold plating resist stripping step of peeling off the gold plating protective resist after the nickel layer removing step.

나아가 상기 금도금 보호용 레지스트는, 드라이필름을 압착한 후 노광 및 현상하는 방법으로 패턴을 형성하는 것이 바람직하다.Furthermore, it is preferable that the said gold plating protective resist forms a pattern by the method of exposing and developing after crimping a dry film.

또한, 상기 금도금 보호용 레지스트는, 액상의 포토레지스트를 코팅한 후 노광 및 현상하는 방법으로 패턴을 형성할 수도 있다.In addition, the gold-plated protective resist may form a pattern by coating a liquid photoresist, followed by exposure and development.

이하 첨부된 도면을 참조로 본 발명의 바람직한 실시예를 상세히 설명하기로 한다. 이에 앞서, 본 명세서 및 청구 범위에 사용된 용어나 단어는 통상적이거나 사전적인 의미로 한정해서 해석되어서는 아니되며, 발명자는 그 자신의 발명을 가장 최선의 방법으로 설명하기 위해 용어의 개념을 적절하게 정의할 수 있다는 원칙에 입각하여 본 발명의 기술적 사상에 부합하는 의미와 개념으로 해석되어야만 한 다.Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. Prior to this, terms or words used in the present specification and claims should not be construed as being limited to the common or dictionary meanings, and the inventors should properly explain the concept of terms in order to explain their invention in the best way. Based on the principle that can be defined, it should be interpreted as meaning and concept corresponding to the technical idea of the present invention.

따라서, 본 명세서에 기재된 실시예와 도면에 도시된 구성은 본 발명의 가장 바람직한 일 실시예에 불과할 뿐이고 본 발명의 기술적 사상을 모두 대변하는 것은 아니므로, 본 출원시점에 있어서 이들을 대체할 수 있는 다양한 균등물과 변형예들이 있을 수 있음을 이해하여야 한다.Therefore, the embodiments described in the specification and the drawings shown in the drawings are only the most preferred embodiment of the present invention and do not represent all of the technical idea of the present invention, various modifications that can be replaced at the time of the present application It should be understood that there may be equivalents and variations.

이하 도 1 내지 도 2i를 참조하여 본 발명의 바람직한 실시예에 따른 도금선이 없는 인쇄회로기판의 제조방법을 상세히 설명하기로 한다.Hereinafter, a method of manufacturing a printed circuit board without a plating line according to an exemplary embodiment of the present invention will be described in detail with reference to FIGS. 1 to 2I.

도 1은 본 발명의 바람직한 실시예에 따른 도금선이 없는 인쇄회로기판의 제조과정을 나타내는 흐름도이고, 도 2a 내지 도 2i는 도 1의 제조방법을 단계적으로 도시한 도면이다.1 is a flowchart illustrating a manufacturing process of a printed circuit board without a plating line according to a preferred embodiment of the present invention, and FIGS. 2A to 2I are sectional views illustrating the manufacturing method of FIG. 1.

본 발명 도금선이 없는 인쇄회로기판의 제조방법을 단계적으로 설명하면 다음과 같다.Referring to the method of manufacturing a printed circuit board without a plating wire of the present invention step by step.

먼저, 동박이 부착된 기판(110)에 드라이필름을 압착하여 회로패턴(120)을 형성한다(S10).First, the dry film is pressed onto the substrate 110 to which the copper foil is attached to form a circuit pattern 120 (S10).

그리고, 상기 회로패턴(120)이 형성된 기판(110) 위에 전면적으로 니켈 층(130)을 형성한다(S20).The nickel layer 130 is formed on the entire surface of the substrate 110 on which the circuit pattern 120 is formed (S20).

이 니켈 층(130)은 이후 금도금을 위한 전도층의 역할을 하기 위한 것으로, 스퍼터링 방법으로 도포하는 것이 바람직하나 반드시 이에 한정하는 것은 아니다.The nickel layer 130 is intended to serve as a conductive layer for gold plating thereafter, but is preferably applied by a sputtering method, but is not necessarily limited thereto.

그리고나서, 상기 도포된 니켈 층(130) 위에 금 레지스트(140)를 선택적으로 도포한다(S30).Then, the gold resist 140 is selectively applied on the applied nickel layer 130 (S30).

상기 금 레지스트(140)는 메쉬를 통한 실크스크린 방법을 통하여 선택적으로 도포하는 것이 바람직하며, 상기 선택적으로 도포된 금 레지스트(140)의 가장자리를 레이저를 통하여 다듬어 경계를 명확히 할 수 있다.The gold resist 140 may be selectively applied through a silk screen method through a mesh, and the edge of the selectively applied gold resist 140 may be trimmed by a laser to clarify the boundary.

다음, 상기 금 레지스트(140)가 도포되지 않은 니켈 층(130)의 상면에 선택적으로 금도금 층(150)을 형성한다(S40).Next, a gold plating layer 150 is selectively formed on an upper surface of the nickel layer 130 on which the gold resist 140 is not applied (S40).

그런 다음, 상기 금 레지스트(140)를 전부 박리하고(S50), 상기 금도금 층(150)을 보호하기 위한 금도금 보호용 레지스트(160)를 상기 선택적으로 분포된 금도금 층(150)의 상부에 형성시킨다(S60).Then, the gold resist 140 is completely peeled off (S50), and a gold plating protective resist 160 for protecting the gold plating layer 150 is formed on the selectively distributed gold plating layer 150 ( S60).

이 금도금 보호용 레지스트(160)는 드라이필름을 압착한 후 노광 및 현상하는 방법으로 패턴을 형성할 수 있으며, 액상의 포토레지스트를 코팅한 후 노광 및 현상하는 방법으로 패턴을 형성하는 것도 가능하다.The gold-plated protective resist 160 may form a pattern by compressing a dry film, and then exposing and developing the pattern. The pattern may be formed by exposing and developing a liquid photoresist.

다음으로, 외부로 노출된 니켈 층(130)을 전부 박리한(S70) 이후, 상기 금도금 보호용 레지스트(160)를 전부 박리한다(S80).Next, after exfoliating all of the nickel layer 130 exposed to the outside (S70), all of the gold plating protection resist 160 is exfoliated (S80).

마지막으로, 솔더레지스트(170)를 선택적으로 도포하여 회로패턴(120)을 외부로부터 절연시키고 보호한다(S90).Finally, the solder resist 170 is selectively applied to insulate and protect the circuit pattern 120 from the outside (S90).

상기의 단계 중에서 금도금 보호용 레지스트(160)의 도포는 금도금 층(150)의 표면을 보호하기 위한 공정으로 니켈 층(130) 박리 약품에 금도금 층(150)이 손상되지 않는다면, 따로 금도금 보호용 레지스트(160)를 도포하지 않고 금 레지스트(140)만을 사용할 수도 있다.The coating of the gold plating protection resist 160 in the above step is a process for protecting the surface of the gold plating layer 150, and if the gold plating layer 150 is not damaged on the nickel layer 130 peeling chemical, the gold plating protection resist 160 is separately. ), Only the gold resist 140 may be used.

이상과 같이, 본 발명은 비록 한정된 실시예와 도면에 의해 설명되었으나, 본 발명은 이것에 의해 한정되지 않으며 본 발명이 속하는 기술 분야에서 통상의 지식을 가진 자에 의해 본 발명의 기술 사상과 아래에 기재될 특허청구범위의 균등 범위 내에서 다양한 수정 및 변형이 가능함은 물론이다.As mentioned above, although this invention was demonstrated by the limited embodiment and drawing, this invention is not limited by this, The person of ordinary skill in the art to which this invention belongs, Of course, various modifications and variations are possible within the scope of equivalents of the claims to be described.

본 발명의 도금선이 없는 인쇄회로기판의 제조방법에 따르면, 기존에 사용되던 화학동을 대체하여 니켈 층을 사용함으로써 설계의 자유도를 증대시키고, 배선 밀도를 증가시켜 고부가가치의 제품을 만들 수 있으며, 회로간 간섭으로 인한 전기적 노이즈를 최소화하여 품질 향상의 효과가 있다.According to the method of manufacturing a printed circuit board without a plated wire of the present invention, by using a nickel layer in place of the conventional copper, it is possible to increase the degree of freedom of design and increase the wiring density to make a high value-added product. Therefore, there is an effect of improving quality by minimizing electrical noise caused by interference between circuits.

Claims (8)

반도체 패키지용 인쇄회로기판의 제조방법에 있어서,In the method of manufacturing a printed circuit board for a semiconductor package, 동박이 부착된 기판에 드라이필름을 압착하여 회로패턴을 형성하는 회로패턴 형성 단계와;A circuit pattern forming step of forming a circuit pattern by pressing a dry film on a substrate having copper foil; 상기 회로패턴이 형성된 기판 위에 전면적으로 니켈 층을 형성하는 니켈 층 형성 단계와;Forming a nickel layer on the substrate on which the circuit pattern is formed; 상기 니켈 층 위에 금 레지스트를 선택적으로 도포하는 금 레지스트 도포 단계와;A gold resist coating step of selectively applying a gold resist on the nickel layer; 상기 금 레지스트가 도포되지 않은 니켈 층의 상면에 선택적으로 금도금 층을 형성하는 금도금 단계와;A gold plating step of selectively forming a gold plating layer on an upper surface of the nickel layer to which the gold resist is not applied; 상기 금 레지스트를 전부 박리하는 금 레지스트 박리 단계; 및A gold resist stripping step of peeling off all of the gold resist; And 상기 금 레지스트 박리 단계 이후 외부로 노출된 니켈 층을 전부 박리하는 니켈 층 제거 단계를 포함하는 도금선이 없는 인쇄회로기판의 제조방법.And a nickel layer removing step of removing all of the nickel layers exposed to the outside after the gold resist stripping step. 제 1항에 있어서,The method of claim 1, 상기 니켈 층 제거 단계 이후,After the nickel layer removing step, 솔더레지스트를 선택적으로 도포하여 회로패턴을 외부로부터 절연시키고 보호하는 솔더레지스트 도포 단계를 더 포함하는 도금선이 없는 인쇄회로기판의 제조방법.A method for manufacturing a printed circuit board without a plating line, the method comprising: applying a solder resist selectively to insulate and protect the circuit pattern from the outside. 제 1항에 있어서,The method of claim 1, 상기 니켈 층은 스퍼터링 방법으로 도포하는 것을 특징으로 하는 도금선이 없는 인쇄회로기판의 제조방법.And the nickel layer is applied by a sputtering method. 제 1항에 있어서,The method of claim 1, 상기 금 레지스트는 메쉬를 통한 실크스크린 방법을 통하여 선택적으로 도포하는 것을 특징으로 하는 도금선이 없는 인쇄회로기판의 제조방법.The gold resist is a method of manufacturing a printed circuit board without a plating line, characterized in that the coating selectively through the silk screen method through the mesh. 제 4항에 있어서,The method of claim 4, wherein 상기 선택적으로 도포된 금 레지스트의 가장자리를 레이저를 통하여 다듬는 것을 특징으로 하는 도금선이 없는 인쇄회로기판의 제조방법.The method of manufacturing a printed circuit board without a plating line, characterized in that the edge of the selectively applied gold resist is trimmed by a laser. 제 1항에 있어서,The method of claim 1, 상기 니켈 층 제거 단계에 앞서 금도금 층을 보호하기 위한 금도금 보호용 레지스트를 상기 선택적으로 분포된 금도금 층의 상부에 형성시키는 금도금 보호용 레지스트 형성 단계; 및A gold plating protective resist forming step of forming a gold plating protective resist on the selectively distributed gold plating layer to protect the gold plating layer before the nickel layer removing step; And 상기 니켈 층 제거 단계 이후 상기 금도금 보호용 레지스트를 전부 박리하는 금도금 레지스트 박리 단계를 더 포함하는 것을 특징으로 하는 도금선이 없는 인쇄회로기판의 제조방법.And a gold plating resist stripping step of completely peeling off the gold plating protective resist after the nickel layer removing step. 제 6항에 있어서,The method of claim 6, 상기 금도금 보호용 레지스트는,The gold plating protective resist, 드라이필름을 압착한 후 노광 및 현상하는 방법으로 패턴을 형성하는 것을 특징으로 하는 도금선이 없는 인쇄회로기판의 제조방법.A method of manufacturing a printed circuit board without a plating line, comprising: forming a pattern by pressing and drying a dry film and then exposing and developing the dry film. 제 6항에 있어서,The method of claim 6, 상기 금도금 보호용 레지스트는,The gold plating protective resist, 액상의 포토레지스트를 코팅한 후 노광 및 현상하는 방법으로 패턴을 형성하는 것을 특징으로 하는 도금선이 없는 인쇄회로기판의 제조방법.A method of manufacturing a printed circuit board without a plating line, comprising forming a pattern by coating a liquid photoresist and then exposing and developing the liquid.
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Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101158218B1 (en) * 2010-11-02 2012-06-19 삼성전기주식회사 printed circuit board and manufacturing method there of
KR101235386B1 (en) 2011-12-21 2013-02-20 주식회사 심텍 Printed circuit board having fine pitch bump and method of manufacturing the same
KR101341633B1 (en) 2008-11-14 2013-12-16 삼성테크윈 주식회사 Printed circuit board without bus line for electric plating and method thereof
KR101913821B1 (en) 2016-01-08 2018-11-02 주식회사 에이엠에스티 Metal pad structure and fabrication method of the same

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20050050849A (en) * 2003-11-26 2005-06-01 삼성전기주식회사 Fabricating method of printed circuit board without electrolytic plating lead
KR100499003B1 (en) 2002-12-12 2005-07-01 삼성전기주식회사 A package substrate for electrolytic leadless plating, and its manufacturing method
KR20060046805A (en) * 2004-11-10 2006-05-18 삼성전기주식회사 Method for fabricating printed circuit board using liquid-type photoresist

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100499003B1 (en) 2002-12-12 2005-07-01 삼성전기주식회사 A package substrate for electrolytic leadless plating, and its manufacturing method
KR20050050849A (en) * 2003-11-26 2005-06-01 삼성전기주식회사 Fabricating method of printed circuit board without electrolytic plating lead
KR20060046805A (en) * 2004-11-10 2006-05-18 삼성전기주식회사 Method for fabricating printed circuit board using liquid-type photoresist

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101341633B1 (en) 2008-11-14 2013-12-16 삼성테크윈 주식회사 Printed circuit board without bus line for electric plating and method thereof
KR101158218B1 (en) * 2010-11-02 2012-06-19 삼성전기주식회사 printed circuit board and manufacturing method there of
KR101235386B1 (en) 2011-12-21 2013-02-20 주식회사 심텍 Printed circuit board having fine pitch bump and method of manufacturing the same
KR101913821B1 (en) 2016-01-08 2018-11-02 주식회사 에이엠에스티 Metal pad structure and fabrication method of the same

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