JP2013197416A - Manufacturing method of semiconductor package, and semiconductor package - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a manufacturing method, of a semiconductor package having excellent bonding reliability, ensuring excellent manufacturing cost and productivity, and to provide a semiconductor package.SOLUTION: The manufacturing method of a semiconductor package includes a step for forming a resin insulation layer on the surface of a substrate having a first conductor circuit, a step for forming a second conductor circuit penetrating the resin insulation layer and being connected electrically with the first conductor circuit, a step for forming metal columnar connection pads on the second conductor circuit of the uppermost layer after the resin insulation layer and the second conductor circuit are formed layer by layer, or alternately, a step for covering the connection pads by coating the resin insulation layer of the uppermost layer with solder resist, and a step for exposing at least a part of the upper surface of the connection pads by removing the solder resist partially.

Description

  The present invention relates to a method for manufacturing a semiconductor package and a semiconductor package that are excellent in manufacturing cost and productivity and excellent in bonding reliability.

2. Description of the Related Art In recent years, telecommunications equipment typified by mobile phones and communication terminals has been remarkably improved in functionality and performance, and semiconductor packages having an IC chip mounted on a substrate are widely used in these telecommunications equipment. As a form of mounting an IC chip on a substrate, a flip chip method in which an IC chip is directly surface-mounted on a substrate has recently been adopted from a conventional method using lead frames, pins, and wires.
As such a substrate, a substrate provided with a buildup layer formed on a core substrate and a connection pad provided on the upper surface of the buildup layer is known. The IC chip is connected to the connection pad via the solder bump. In order to improve the connectivity between the IC chip and the substrate, an underfill (sealing resin) is filled between the two.

With the increase in functionality and performance of telecommunications equipment, the density and integration of IC chips have progressed, and the diameters of solder bumps and connection pads that serve as connection terminals for IC chips in semiconductor packages Narrow pitch and finer are accelerating.
4A to 4E are cross-sectional views showing a solder bump forming method according to a conventional example in the order of steps.
In FIG. 4A, a conductor circuit 102 serving as a connection terminal is formed on an interlayer insulating resin layer 101 which is the outermost layer (ie, the uppermost layer) of the substrate, and a solder resist (SR) layer 103 is formed so as to cover this. The formed state is shown.

FIG. 4B shows a state in which the opening 104 is provided in the solder resist layer 103 so that the conductor circuit 102 serving as the connection terminal is exposed.
FIG. 4C shows a state in which the metal coating layer 105 is applied to the conductor circuit 102. Here, for example, the metal coating layer 105 is formed in the order of a Ni layer and an Au layer, and is used as a terminal junction. The Ni layer ensures electrical and mechanical reliability of the solder joint, and the Au layer is provided to prevent oxidation of the Ni layer surface until the solder joint is completed. The structure of the terminal joint portion on which such a metal coating layer is formed is not limited to a semiconductor package and is generally used as a terminal portion structure for performing solder joint.

FIG. 4D shows a general solder printing process in which the solder paste 106 is printed through the squeegee 107 and the metal mask 108 to fill the opening 104 with the solder paste 106.
FIG. 4E shows a state where the solder paste is melted in the reflow process, and the Ni bump and the alloy layer are formed to join the conductor circuit 102 and the solder bump 109 is formed. In general, solder bumps 109 used for connection to an IC chip have a diameter of about 50 to 200 μm, and the number thereof is about 50 to 150 per 1 cm ² .

Here, as described above, solder bumps and connection pads are miniaturized, but it is difficult to ensure the height of the solder bumps, and the gap between the IC chip and the substrate after mounting (standoff). Tend to be lower. For this reason, when filling the underfill between the IC chip and the substrate, the fluidity of the resin is deteriorated, and voids are generated when the resin is sealed.
In order to solve the above problems, for example, Patent Document 1 discloses a structure in which the conductor layer on the circuit board side is higher than the surface of the insulating resin layer. In this structure, a preliminary solder layer for mounting an IC chip is formed on the conductor layer.

JP 2000-315706 A

However, in the above structure, when the IC chip is mounted on the substrate, the solder wraps around the side surface of the conductor layer, so that it is necessary to supply a certain amount of solder by electrolytic plating. That is, since it is necessary to form the preliminary solder layer thickly by electrolytic plating, the manufacturing cost may increase and the productivity may decrease.
Therefore, the present invention has been made in view of such circumstances, and an object of the present invention is to provide a semiconductor package manufacturing method and a semiconductor package that are excellent in manufacturing cost and productivity and excellent in bonding reliability.

  In order to solve the above problems, a method for manufacturing a semiconductor package according to one embodiment of the present invention includes a step of forming a resin insulating layer on a surface side of a substrate having a first conductor circuit, A step of forming a second conductor circuit electrically connected to the first conductor circuit, and after the resin insulating layer and the second conductor circuit are formed one by one or alternately, Forming a metal columnar connection pad on the second conductor circuit in the uppermost layer; applying a solder resist on the uppermost resin insulation layer to cover the connection pad; and partially covering the solder resist Removing, leaving the solder resist on at least a part of the side surface of the connection pad, and exposing at least a part of the upper surface of the connection pad from the solder resist.

The semiconductor package manufacturing method may further include a step of forming a bump on the upper surface of the connection pad.
The method for manufacturing a semiconductor package may further include a step of forming a metal coating layer on an upper surface of the connection pad before forming the bump, and in the step of forming the bump, the metal coating layer is formed. The bump is formed on the upper surface of the connection pad.

In the method for manufacturing a semiconductor package, the metal coating layer is formed by plating.
In the method for manufacturing a semiconductor package, in the step of partially removing the solder resist, a portion of the solder resist that covers the upper surface of the connection pad is removed by etching. .

In the semiconductor package manufacturing method, in the step of partially removing the solder resist, a portion of the solder resist covering the upper surface of the connection pad is polished and removed. .
A semiconductor package according to another aspect of the present invention includes a resin insulating layer formed on a surface of a substrate having a first conductor circuit, and electrically connected to the first conductor circuit through the resin insulating layer. The resin insulation layer and the second conductor circuit are formed one layer at a time or alternately, and are formed in the second conductor circuit in the uppermost layer. It further comprises a metal columnar connection pad and a solder resist applied to the uppermost resin insulation layer, and at least a part of the side surface of the connection pad is covered with the solder resist, and the connection pad At least a part of the upper surface of is exposed from the solder resist.

In the above semiconductor package, the entire side surface of the connection pad and the outer peripheral portion of the upper surface of the connection pad are covered with the solder resist, and the central portion of the upper surface of the connection pad is the solder resist. It is exposed from.
In the semiconductor package described above, the diameter of the connection pad is smaller than the diameter of the second conductor circuit in the uppermost layer located immediately below the connection pad.

The semiconductor package may further include a bump formed on the upper surface of the connection pad.
The semiconductor package may further include a metal coating layer formed on an upper surface of the connection pad, and the bump is formed on the upper surface of the connection pad via the metal coating layer. To do.
In the semiconductor package described above, the metal coating layer may be the following material 1, material 2, or material 3.
Material 1: Nickel / Gold Material 2: Nickel / Palladium / Gold Material 3: Tin

  The present invention has the following effects. That is, by providing the metal columnar connection pads on the substrate, it is possible to ensure a sufficient standoff between the IC chip and the substrate. Moreover, the side surface (side wall) of the connection pad is partially or entirely covered with a solder resist. For this reason, when the solder bump is formed on the upper surface of the connection pad, the solder does not spread on the side surface of the connection pad. Thereby, since the supply amount of the solder to the connection pad can be suppressed, it is possible to reduce the manufacturing cost and improve the productivity.

The figure which shows the manufacturing method of the semiconductor package 100 which concerns on embodiment of this invention. The figure which shows the manufacturing method of the semiconductor package 100 which concerns on embodiment of this invention. The figure which expanded a part of manufacturing process concerning an embodiment. The figure which shows the formation method of the solder bump which concerns on a prior art example.

Hereinafter, embodiments according to the present invention will be described with reference to the drawings. Note that, in each drawing described below, parts having the same configuration are denoted by the same reference numerals, and repeated description thereof is omitted.
FIG. 1A to FIG. 2F are cross-sectional views showing a method for manufacturing a semiconductor package 100 according to an embodiment of the present invention in the order of steps. 3A to 3D are partial enlarged views of the semiconductor package 100 (before and after solder formation).

In the embodiment of the present invention, the conductor circuit 11 included in the core substrate 10 includes those formed by a subtractive method using etching treatment and those formed by a semi-additive method using electrolytic plating. You may use what was formed by the construction method.
As a material constituting the core substrate 10 (that is, a core substrate), a copper clad laminate (CCL) is often used as a representative material, and a glass epoxy material, a polyimide film, a polyamide film, a liquid crystal film is used as an insulating layer. An aramid material or the like can be used. Copper-clad laminates are those in which a copper foil is thermocompression bonded to an insulating layer via an adhesive layer, in which the insulating layer itself is thermocompression bonded to copper foil, in which an insulating material is cast on copper foil and heated, insulation Examples thereof include a method in which a surface treatment is performed on a layer, a seed layer such as nichrome is sputtered as a seed layer, and then a copper foil layer is formed by sputtering or plating the conductive layer.

First, the conductor circuit 11 having a desired pattern shape is formed on one side or both sides of the core substrate 10. Then, an insulating resin is applied on the core substrate 10 on which the conductor circuit 11 is formed, vacuum lamination is performed at a temperature of about 120 ° C., and post-baking at a high temperature to form an interlayer insulating resin layer 12 (FIG. 1 (a)). Here, through holes are not shown in the core substrate 10 for convenience, but through hole copper wirings that penetrate the core substrate 10 may be formed as necessary.
Arbitrary organic materials and inorganic materials can be used for the interlayer insulating resin layer 12. Specifically, although it consists of insulating resin, such as an epoxy resin and a polyimide resin, it is not limited to this. The conductor circuit 11 may be made of metal, but copper is generally preferable from the viewpoint of cost and conductivity.

Next, a via hole 13 having a diameter of about 50 μm that reaches the conductor circuit 11 is formed in the interlayer insulating resin layer 12 (FIG. 1B). Thereafter, desmear treatment is performed with a mixed liquid of potassium permanganate and sodium hydroxide or the like in order to remove the residue of the organic insulating material deposited in the lower layer in the via hole 13 that is generated during via processing.
By performing the desmear process as described above, the insulating layer and organic residue at the bottom of the via hole can be removed. Since the desmear process is performed on the entire surface of the substrate, the insulating layer and organic residue at the bottom of the via hole are removed, and the upper part of the insulating layer and the inside of the via hole are roughened.

  As a method for forming the via hole, laser processing is preferable. There are carbon dioxide laser, YAG laser (fundamental wave, 2nd harmonic, 3rd harmonic, or 4th harmonic), or excimer laser, etc., but both the conductive layer and insulating resin layer are processed. A YAG laser (third harmonic or fourth harmonic), or an excimer laser, which is a short wavelength laser of 400 nm or less capable of simultaneously processing the laser beam, is more preferable.

  Thereafter, an electroless copper plating layer 14 without a conductive pattern having a thickness of about 1 μm is formed by electroless copper plating (FIG. 1C). Here, the electroless copper plating layer 14 is formed on the surface of the interlayer insulating resin layer 12 and the surface of the conductor circuit 11 exposed from the interlayer insulating resin layer 12. The electroless copper plating layer 14 is a layer called a seed layer in the conventional semi-additive method. By supplying power to the electroless copper plating layer 14 in a later step, a predetermined layer is formed on the electroless copper plating layer 14. This is for performing electrolytic copper plating of the pattern.

  Next, a dry film resist pattern is formed on the electroless copper plating layer 14. The dry film resist is, for example, a photosensitive resin layer having a thickness of about 25 μm sandwiched between a support film and a protective layer. In the process of forming the dry film resist pattern, the support film is directed to the opposite side of the core substrate 10 while peeling the protective layer of the dry film resist from the electroless copper plating layer 14, and the roll temperature is 120 ° C. with a hot roll laminator. Laminate to the substrate to the extent. Next, a photomask having a desired pattern is placed on the support film side of the dry film resist and exposed from above the photomask to obtain a dry film resist having a cured resist pattern. Thereafter, the support film is peeled off, and the substrate is immersed in an aqueous Na2CO3 solution and developed to obtain a dry film resist pattern 15 having a desired shape (FIG. 1 (d)).

  Next, the electrolytic copper plating layer 16 is formed on the electroless copper plating layer 14 by supplying power to the electroless copper plating layer 14 exposed from the gap between the formed dry film resist patterns 15 (FIG. 1 (e)). )). After the electrolytic copper plating layer 16 is formed, the dry film resist pattern 15 is peeled off. Thereby, the conductor circuit which consists of the electrolytic copper plating layer 16 which has a desired pattern is obtained (FIG.1 (f)).

  In the embodiment of the present invention, a multilayer substrate in which conductor circuits made of the electroless copper plating layer 14 are formed in multiple layers may be manufactured. In that case, the electroless copper plating layer 14 exposed from the gap of the electrolytic copper plating layer 16 (that is, covered with the dry film resist pattern 15) is etched (flash etching). Then, by repeating the same steps from the formation of the interlayer insulating resin layer 12 to the flash etching, it is possible to form a laminated portion of the conductor circuit composed of the electroless copper plating layer 14. That is, a structure in which a plurality of interlayer insulating resin layers 12 and conductor circuits made of electroless copper plating layers 14 are alternately stacked can be formed on the core substrate 10.

Here, as an example of the present invention, a case where the interlayer insulating resin layer 12 and the conductor circuit composed of the electroless copper plating layer 14 are formed one layer at a time on one side of the core substrate (that is, when a single layer substrate is manufactured). ) Is assumed. For this reason, flash etching is not performed and the process proceeds to the next step.
When the metal columnar connection pads 19 are formed only on one surface of the core substrate, it is necessary to protect the opposite surface (here, the motherboard mounting surface). Therefore, the protective film 18 is laminated (FIG. 2A). Since any protective film can be used as long as it has heat resistance and plating resistance, an inexpensive dry film resist or the like is preferable. When the connection pads 19 are formed on both sides, it is not necessary to form the protective film 18. For convenience, FIG. 2A shows a method of forming the connection pads 19 only on one side.

Next, a dry film resist pattern 17 is formed in accordance with a location where the metal columnar connection pad 19 is formed (FIG. 2A). The dry film resist used here can be the same as that used to obtain the dry film resist pattern 15, but it is desirable to select one having a thickness that matches the height of the connection pad 19.
Next, in accordance with the opening shape of the dry film resist pattern 17, a metal columnar connection pad 19 is formed by electrolytic plating, and the electroless copper plating layer 14 is removed by flash etching (FIG. 2B). The connection pad 19 can be manufactured by the same method as a normal semi-additive construction method. It is desirable that the diameter of the connection pad 19 be equal to or smaller than the diameter of the second conductor circuit 14 located immediately below the connection pad 19.

  After the metal columnar connection pads 19 are formed, the dry film resist pattern 17 and the protective film 18 are peeled off (FIG. 2C). For peeling off the dry film resist pattern 17 and the protective film 18, a general alkaline stripping solution or amine stripping solution can be used. Further, when a photosensitive dry film is used as the material of the protective film 18, it is desirable to peel off at the same time as the resist pattern 17 from the viewpoint of cost and production.

  Next, the solder resist layer 20 is applied to both sides of the core substrate (FIG. 2D). The solder resist layer 20 can be formed by applying an uncured resin (resin composition) by a roll coater method or the like, or thermocompression bonding an uncured resin film. As for the thickness of the said soldering resist layer 20, 5-70 micrometers is desirable. When the thickness is less than 5 μm, the solder resist layer is easily peeled off and cracks are easily generated. When the thickness is more than 70 μm, opening is difficult. The solder resist material is not particularly limited as long as it is an electrically insulating resin, and can be selected from general resist materials such as epoxy, phenol resin, xylene, acrylic, and polyimide.

Next, an opening 21 is formed in the solder resist layer 20 (FIG. 2E). The opening 21 is formed so that at least a part of the upper surface (that is, the top of the head) of the connection pad 19 is exposed. An enlarged view of FIG. 2 (e) is FIG. 3 (a) or FIG. 3 (c). In the step of FIG. 2 (e), as shown in FIG. 3 (a) or FIG. 3 (c), the opening 21 is left so as to leave the solder resist layer 20 on part or all of the side surface (side wall) of the connection pad 19. Form. When the opening 21 is formed by pattern exposure and development, any of the methods used at the time of manufacturing the semiconductor package can be used. However, due to the problem of alignment of the exposure machine, the opening 21 is formed on the upper surface of the connection pad 19. It is desirable to form smaller than this diameter (FIG. 3C).
In the embodiment of the present invention, the opening 21 can also be formed by polishing. As a polishing method, physical polishing such as sand blasting or wet blasting is desirable. In any method, the solder resist layer 20 is left on at least a part of the side surface of the connection pad 19.

Next, a metal coating layer 23 is formed on the upper surface of the connection pad 19 and in a region exposed from the solder resist layer 20. Then, solder bumps 24 are formed on the metal coating layer 23 (FIGS. 2 (f), 3 (b), and 3 (d)). Usually, the metal coating layer 23 is desirably a corrosion-resistant metal such as nickel, palladium, gold, silver, platinum, or tin, and specifically, a metal such as nickel-gold, nickel-palladium-gold, or tin. Is desirable.
The metal coating layer 23 can be formed by, for example, plating, vapor deposition, electrodeposition, or the like, and among these, plating is desirable from the viewpoint of excellent uniformity of the coating layer. The solder bumps 24 can be formed not only by a solder paste printing method but also by a solder ball mounting method or the like. After filling the solder paste, the solder bumps 24 are formed by heating reflow and flux cleaning, and the desired semiconductor package 100 is obtained.

First, ABF GX-13 (manufactured by Ajinomoto Fine Techno Co., Ltd.) as an insulating resin is vacuum-laminated on a conductor circuit 11 formed on the core substrate 10 at a laminating temperature of 120 ° C., and then post-baked at 180 ° C. An insulating resin layer 12 was obtained (FIG. 1 (a)).
Next, after forming a via hole 13 having a diameter of 50 μm in the interlayer insulating resin layer 12 with a laser drill (FIG. 1B), desmear treatment was performed to remove smear generated by the laser drill. As the desmear process, a known desmear process can be applied. For example, MLB213A (Rohm and Haas Electronic Materials Co., Ltd.), which is a commercially available product, is immersed in a swelling bath containing 20% by volume and 10% by volume of Qoposit Z for 1 to 15 minutes at 60 to 85 ° C. MLB216-2 was immersed in an etching bath containing 10% by volume of Haas Electronic Materials Co., Ltd.) and 15% by volume of MLB213B (made by Rohm and Haas Electronic Materials Co., Ltd.) at 55 ° C. to 85 ° C. for 2 to 15 minutes. It can be suitably carried out by a known method such as immersing in a neutralization bath containing 20% by volume (made by Rohm and Haas Electronic Materials Co., Ltd.) at 35 ° C. to 55 ° C. for 2 to 10 minutes.

Further, an electroless copper plating layer 14 having a thickness of about 1 μm was formed by electroless copper plating (FIG. 1C).
Furthermore, as a dry film resist, Sunfort AQ-1558 (manufactured by Asahi Kasei Electronics Co., Ltd.) having a thickness of 15 μm was used. This uses a polyethylene terephthalate film as the support film and a polyethylene film as the protective layer, and the photosensitive resin layer thickness is 25 μm. The electroless copper plating layer 14 having a thickness of about 1 μm was laminated on a substrate at a roll temperature of 120 ° C. with a hot roll laminator (Asahi Kasei Co., Ltd., AL-70) while peeling off the protective layer of the dry film resist. The air pressure was 0.3 MPa, and the laminating speed was 1.0 m / min. It was.

A photomask is placed on the support film side of the dry film resist and exposed to an exposure of 120 mJ / cm ² with an ultra-high pressure mercury lamp (OMW Seisakusho, HMW-201KB). A film resist was obtained. Next, the support film was peeled off, and the substrate was immersed in a 1% by mass Na 2 CO 3 aqueous solution at 30 ° C. for 50 seconds and developed to obtain a dry film resist pattern 15 (FIG. 1D). Next, electrolytic copper plating was performed on the first electroless copper plating layer 14 to form an electrolytic copper plating layer 16 having a thickness of 20 μm (FIG. 1 (e)).
Here, a 3% by mass NaOH aqueous solution was prepared as a dry film resist stripping solution, and sprayed at 50 ° C. and a pressure of 0.2 MPa for 60 seconds. Thereafter, it was washed with water and dried to complete the peeling of the dry film resist (FIG. 1 (f)).

  Next, a dry film resist was formed as a protective film 18 on the surface where the metal columnar connection pads 19 were not formed (FIG. 2A). As a material for the protective film 18, Sunfort AQ-1558 (manufactured by Asahi Kasei Electronics Co., Ltd.) was used. Subsequently, dry film resist patterning was performed using Sunfort AQ-4038 (manufactured by Asahi Kasei Electronics Co., Ltd.) having a thickness of 40 μm to obtain a dry film resist pattern 17.

Next, electrolytic copper plating was performed on the dry film resist pattern 17 to form metal columnar connection pads 19 (FIG. 2B). The connection pad 19 had a diameter of 70 μm and a height of 35 μm from the electrolytic copper plating layer 16. The plating conditions are as follows. CuSO ₄ .5H ₂ O 140 g / l, H ₂ SO ₄ 120 g / l, Cl-50 mg / l, additive 300 mg / l, amine sulfonate 100 mg / l, temperature 25 ° C., current density 1.5 A / dm ² , Plating time 60 minutes.

  Next, the dry film resist pattern 17 was peeled and removed, and flash etching was performed to remove the electroless copper plating layer 14 (FIG. 2C). Next, a solder resist layer 20 was formed so that a solder resist (PSR-4000 AUS-703, manufactured by Taiyo Ink Manufacturing Co., Ltd.) had a thickness of about 22 μm (FIG. 2D). Here, from the upper surface of the connection pad 19 The thickness of the upper solder resist layer 20 was 10 μm.

  Next, an opening 21 was formed in the solder resist layer 20 at a predetermined position by photolithography (FIG. 2E). The opening diameter here was 50 μm. An enlarged view of the opening 21 is shown in FIG. 3A or 3C, and the opening 21 has a smaller diameter than the diameter of the upper surface of the connection pad 19. Further, the opening 21 was also performed on the opening by polishing, and an enlarged view thereof was shown in FIG. 3A, and the diameter of the opening 21 was equal to the diameter of the upper surface of the connection pad 19. As the polishing, belt sander polishing using belt polishing paper (manufactured by Sankyori Chemical Co., Ltd.) was performed.

Next, the substrate was immersed in an electroless nickel plating solution having a pH of 5 containing nickel chloride (30 g / l), sodium hypophosphite (10 g / l), and sodium citrate (10 g / l) for 20 minutes. A nickel plating layer having a thickness of 5 μm was formed therein. Further, the substrate was added to an electroless plating solution containing potassium gold cyanide (2 g / l), ammonium chloride (75 g / l), sodium citrate (50 g / l) and sodium hypophosphite (10 g / l). The metal coating layer 23 was obtained by immersing for 23 seconds under the condition of ° C. to form a 0.03 μm thick gold plating layer on the nickel plating layer.
Finally, a metal mask is placed on the solder resist layer 20, and solder paste 24 is filled by filling the openings 21 and 22 in the openings 21 and 22 through the mask using a metal squeegee and then reflowing at 200 ° C. As a result, a desired semiconductor package 100 was obtained (FIG. 2F).

  As described above, according to the embodiment of the present invention, it is possible to ensure a sufficient standoff between the IC chip and the substrate by providing the metal columnar connection pads 19 on the substrate. The side surface (side wall) of the connection pad 19 is partially or entirely covered with the solder resist layer 20. For this reason, when the solder bump 24 is formed on the upper surface of the connection pad 19, the solder does not spread on the side surface of the connection pad 19. Thereby, the supply amount of solder to the connection pad 19 can be suppressed. A structure having both a sufficient solder height and high connection reliability can be realized.

  Further, since it is not necessary to form a noble metal coating layer on the side surface of the connection pad 19, it is more advantageous in terms of cost than the conventional structure. Furthermore, the opening 21 can be formed in the solder resist layer 20 by a polishing process. In this case, an exposure mask for forming the opening 21 is not required. Therefore, the mask cost can be reduced and the process can be simplified, and the productivity is improved. As described above, according to the embodiment of the present invention, it is possible to reduce the manufacturing cost and improve the productivity.

10 Core substrate (substrate)
11 Conductor circuit (first conductor circuit)
12 Interlayer insulation resin layer (resin insulation layer)
13 Via hole 14 Electroless copper plating layer 15, 17 Dry film resist pattern 16 Electrolytic copper plating layer (second conductor circuit)
18 Protective film 19 Metal columnar connection pad 20 Solder resist layer (solder resist)
21 and 22 Opening 23 Metal coating layer 24 Solder bump 100 Semiconductor package

Claims (12)

Forming a resin insulating layer on the side of the substrate having the first conductor circuit;
Forming a second conductor circuit passing through the resin insulation layer and electrically connected to the first conductor circuit;
Forming a metal columnar connection pad on the second conductor circuit of the uppermost layer after the resin insulating layer and the second conductor circuit are formed one layer at a time or alternately in a plurality;
Applying a solder resist to the uppermost resin insulation layer to cover the connection pads;
Removing the solder resist partially, leaving the solder resist on at least part of the side surface of the connection pad, and exposing at least part of the upper surface of the connection pad from the solder resist. A method of manufacturing a semiconductor package.   The method of manufacturing a semiconductor package according to claim 1, further comprising a step of forming a bump on an upper surface of the connection pad. Forming a metal coating layer on the upper surface of the connection pad before forming the bump,
3. The method of manufacturing a semiconductor package according to claim 2, wherein in the step of forming the bump, the bump is formed on an upper surface of the connection pad via the metal coating layer.   4. The method of manufacturing a semiconductor package according to claim 3, wherein the metal coating layer is formed by plating. In the step of partially removing the solder resist,
5. The method of manufacturing a semiconductor package according to claim 1, wherein a portion of the solder resist covering an upper surface of the connection pad is removed by etching. In the step of partially removing the solder resist,
5. The method of manufacturing a semiconductor package according to claim 1, wherein a portion of the solder resist covering an upper surface of the connection pad is polished and removed. A resin insulation layer formed on the surface of the substrate having the first conductor circuit;
A second conductor circuit that penetrates through the resin insulation layer and is electrically connected to the first conductor circuit,
The resin insulation layer and the second conductor circuit are formed one layer at a time or alternately,
Metal columnar connection pads formed on the second conductor circuit in the uppermost layer;
A solder resist applied to the uppermost resin insulation layer; and
At least a part of a side surface of the connection pad is covered with the solder resist, and at least a part of an upper surface of the connection pad is exposed from the solder resist.   All of the side surfaces of the connection pad and the outer peripheral portion of the upper surface of the connection pad are covered with the solder resist, and the central portion of the upper surface of the connection pad is exposed from the solder resist. The semiconductor package according to claim 7.   9. The semiconductor package according to claim 7, wherein a diameter of the connection pad is equal to or smaller than a diameter of the second conductor circuit in the uppermost layer located immediately below the connection pad.   The semiconductor package according to claim 7, further comprising a bump formed on an upper surface of the connection pad. A metal coating layer formed on the upper surface of the connection pad,
The semiconductor package according to claim 10, wherein the bump is formed on an upper surface of the connection pad through the metal coating layer. The semiconductor package according to any one of claims 7 to 11, wherein the metal coating layer is the following material 1, material 2, or material 3.
Material 1: Nickel / Gold Material 2: Nickel / Palladium / Gold Material 3: Tin

Images