JP2016111297A - Wiring board, semiconductor device, and method of manufacturing wiring board - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a wiring board capable of suppressing generation of cracks and the like at an interface between a connection terminal and an insulating layer.SOLUTION: A wiring board 10 has: a wiring layer 52; an insulating layer 53 that is formed of an insulation resin containing a photosensitive resin as a main component, and that covers the wiring layer 52; and a connection terminal P1 that is electrically connected with the wiring layer 52 via a via wiring 55 formed in a through-hole 53X penetrating through the insulating layer 53 in a thickness direction, and that is formed so as to be protruded upward from an upper surface 53A of the insulating layer 53. The wiring board 10 has a protection layer 60 formed of an insulation resin containing a photosensitive resin as a main component, and formed on the upper surface 53A of the insulating layer 53. The protection layer 60 has: a first protection layer 61 formed in a mounting region A1, and formed so as to surround the connection terminal P1 while being contacted with a lateral face of the connection terminal P1; and a second protection layer 62 formed in an outer peripheral region A2 provided outside the mounting region A1 so as to be separated from the first protection layer 61 by an opening 60X, and formed thinner than the first protection layer 61.SELECTED DRAWING: Figure 1

Description

  The present invention relates to a wiring board, a semiconductor device, and a manufacturing method of the wiring board.

  Various shapes and structures of wiring boards for mounting electronic components such as semiconductor chips have been proposed. In recent years, with higher integration and higher functionality of semiconductor chips, there is an increasing demand for wiring miniaturization even in wiring boards on which semiconductor chips are mounted. Therefore, a wiring board is proposed in which a solder resist layer is formed on a base substrate on which a wiring pattern is formed, and columnar connection terminals are formed on the wiring pattern exposed from the solder resist layer (for example, Patent Document 1). reference).

JP 2010-129996 A

  By the way, when a photosensitive resin is used as the material of the solder resist layer, there is a problem that cracks or the like are likely to occur at the interface between the solder resist layer and the connection terminal. More specifically, since the solder resist layer made of a photosensitive resin does not contain a reinforcing material such as glass cloth, the mechanical strength is weak. The solder resist layer and the connection terminal (for example, copper layer) have different thermal expansion coefficients. For this reason, in a region where the connection terminal is formed, thermal stress concentrates on the interface between the connection terminal and the solder resist layer, and cracks or the like are likely to occur at the interface.

  According to one aspect of the present invention, the first wiring layer is made of an insulating resin whose main component is a photosensitive resin, and the first insulating layer covering the first wiring layer and the first insulating layer are thick. A first via wiring formed in a through hole penetrating in a vertical direction to expose the first wiring layer; and electrically connected to the first wiring layer via the first via wiring; The first insulating layer is formed to protrude upward from the upper surface of the insulating layer, and includes a connection terminal connected to the electronic component and an insulating resin mainly composed of a photosensitive resin, and covers the side surface of the connection terminal. A protective layer formed on an upper surface of the layer, wherein the protective layer is formed in a mounting region where the electronic component is mounted, and is formed so as to contact the side surface of the connection terminal and surround the connection terminal. And the first protective layer and the outer peripheral region outside the mounting region. It formed spaced apart from the first protective layer by a first opening exposing the upper surface of the edge layer, and a second protective layer formed thinner than the first protective layer.

  According to one aspect of the present invention, it is possible to suppress the occurrence of cracks and the like at the interface between the connection terminal and the insulating layer.

(A) is schematic sectional drawing (1-1 sectional drawing in FIG. 2) which shows the wiring board of 1st Embodiment, (b) is an expanded sectional view which expanded a part of wiring board shown to (a). . The schematic plan view which shows the wiring board of 1st Embodiment. 1 is a schematic cross-sectional view showing a semiconductor device according to a first embodiment. (A), (b) is a schematic sectional drawing which shows the manufacturing method of the wiring board of 1st Embodiment. (A), (b) is a schematic sectional drawing which shows the manufacturing method of the wiring board of 1st Embodiment. (A), (b) is a schematic sectional drawing which shows the manufacturing method of the wiring board of 1st Embodiment. (A), (b) is a schematic sectional drawing which shows the manufacturing method of the wiring board of 1st Embodiment. (A) is a schematic sectional drawing which shows the manufacturing method of the wiring board of 1st Embodiment, (b) is an expanded sectional view which expanded a part of (a). (A), (b) is a schematic sectional drawing which shows the manufacturing method of the wiring board of 1st Embodiment. FIG. 3 is a schematic cross-sectional view showing the method for manufacturing the wiring board according to the first embodiment. The expanded sectional view which shows the manufacturing method of the wiring board of 1st Embodiment. FIG. 3 is a schematic cross-sectional view showing the method for manufacturing the wiring board according to the first embodiment. (A), (b) is an expanded sectional view which shows the manufacturing method of the wiring board of 1st Embodiment. (A), (b) is an expanded sectional view which shows the manufacturing method of the wiring board of 1st Embodiment. FIG. 3 is a schematic cross-sectional view showing the method for manufacturing the wiring board according to the first embodiment. FIG. 3 is a schematic cross-sectional view showing the method for manufacturing the semiconductor device of the first embodiment. (A) is a schematic sectional drawing which shows the model structure of an Example sample, (b) is a schematic sectional drawing which shows the model structure of a comparative example sample. (A) is explanatory drawing which shows the simulation result of the stress distribution of an Example sample, (b) is explanatory drawing which shows the simulation result of the stress distribution of a comparative example sample. The schematic sectional drawing which shows the protective layer of a comparative example. Explanatory drawing which shows the simulation result of curvature. The schematic sectional drawing which shows the wiring board of 2nd Embodiment. The schematic sectional drawing which shows the wiring board of 3rd Embodiment. The schematic sectional drawing which shows the wiring board of 4th Embodiment. The expanded sectional view which shows a part of wiring board of a modification. The expanded sectional view which shows a part of wiring board of a modification.

Hereinafter, an embodiment will be described with reference to the accompanying drawings.
In the accompanying drawings, for convenience, there is a case where a characteristic part is enlarged to make the characteristic easy to understand, and a dimensional ratio of each component is not always the same as an actual one. In the cross-sectional view, in order to make the cross-sectional structure of each member easy to understand, the hatching of some members is shown in place of a satin pattern, and the hatching of some members is omitted.

  As shown in FIG. 1A, a wiring board 10 includes a wiring structure 11 (first wiring structure) and a wiring structure 12 (second wiring) stacked on one side (here, the upper side) of the wiring structure 11. Structure) and a solder resist layer 13 laminated on the other side (here, the lower side) of the wiring structure 11. The planar shape of the wiring board 10 can be an arbitrary shape and an arbitrary size. For example, the planar shape of the wiring board 10 can be a square shape of about 20 mm × 20 mm to 40 mm × 40 mm.

First, the structure of the wiring structure 11 will be described.
The wiring structure 11 is a low-density wiring layer in which a wiring layer having a wiring density lower than that of the wiring structure 12 is formed. The wiring structure 11 includes a core substrate 20, an insulating layer 31 stacked on the upper surface 20 </ b> A of the core substrate 20, and an insulating layer 41 stacked on the lower surface 20 </ b> B of the core substrate 20.

  Here, as the material of the core substrate 20 and the insulating layers 31 and 41, for example, a non-photosensitive insulating resin mainly composed of a thermosetting resin can be used. For example, as a material of the core substrate 20 and the insulating layers 31 and 41, a so-called glass cloth (glass woven fabric) which is a reinforcing material is impregnated with a thermosetting insulating resin mainly composed of an epoxy resin and cured. Glass epoxy resin can be used. The reinforcing material is not limited to glass cloth, and for example, a glass nonwoven fabric, an aramid woven fabric, an aramid nonwoven fabric, a liquid crystal polymer (LCP) woven fabric or an LCP nonwoven fabric can be used. The thermosetting insulating resin is not limited to an epoxy resin, and for example, an insulating resin such as a polyimide resin or a cyanate resin can be used. The core substrate 20 and the insulating layers 31 and 41 may contain a filler such as silica or alumina, for example. In addition, as the material of the core substrate 20 and the insulating layers 31 and 41, for example, a non-photosensitive insulating resin whose main component is a thermosetting resin not containing a reinforcing material can be used.

  The core substrate 20 is provided near the center of the wiring structure 11 in the thickness direction. The thickness of the core substrate 20 can be about 80 to 800 μm, for example. The core substrate 20 is provided with through holes 20X at required locations (four locations in FIG. 1A). The through hole 20X is formed so as to penetrate from the upper surface 20A to the lower surface 20B of the core substrate 20. A through electrode 21 that penetrates the core substrate 20 in the thickness direction is formed in the through hole 20X. The through electrode 21 is filled in the through hole 20X, for example. The through hole 20X and the through electrode 21 are formed in, for example, a substantially circular shape in plan view, although illustration is omitted. The diameters of the through hole 20X and the through electrode 21 can be set to, for example, about 50 to 100 μm. The pitch of the through holes 20X and the through electrodes 21 can be set to, for example, about 100 to 200 μm. Moreover, as a material of the through electrode 21, for example, copper (Cu) or a copper alloy can be used.

  A wiring layer 22 is formed on the upper surface 20 </ b> A of the core substrate 20, and a wiring layer 23 is formed on the lower surface 20 </ b> B of the core substrate 20. These wiring layers 22 and 23 are electrically connected to each other through the through electrode 21. In addition, as a material of the wiring layers 22 and 23, for example, copper or a copper alloy can be used. The thickness of the wiring layers 22 and 23 can be about 15 to 35 μm, for example. The line and space (L / S) of the wiring layers 22 and 23 can be, for example, about 20 μm / 20 μm. Here, the line and space (L / S) indicates the width of the wiring and the interval between adjacent wirings.

An insulating layer 31 and a via wiring 32 formed in the insulating layer 31 are stacked on the upper surface 20A of the core substrate 20.
The insulating layer 31 is laminated on the upper surface 20 </ b> A of the core substrate 20 so as to cover the wiring layer 22. The thickness of the insulating layer 31 is set to be thinner than the core substrate 20, for example. For example, the thickness of the insulating layer 31 can be about 40 to 75 μm.

  The insulating layer 31 is formed with a through hole 31 </ b> X that opens at a required location on the upper surface 31 </ b> A and penetrates the insulating layer 31 in the thickness direction to expose a part of the upper surface of the wiring layer 22. The through hole 31X is formed in a tapered shape whose diameter increases from the lower side (core substrate 20 side) to the upper side (wiring structure 12 side) in FIG. For example, the through hole 31X is formed in a substantially inverted truncated cone shape in which the opening diameter of the lower opening end is smaller than the opening diameter of the upper opening end. The opening diameter of the upper opening end of the through hole 31X is smaller than the diameter of the through electrode 21, for example. For example, the opening diameter of the upper opening end of the through hole 31X can be about 50 to 70 μm.

  The upper surface 31A of the insulating layer 31 is a smooth surface (low roughness surface) with few irregularities. For example, the upper surface 31A of the insulating layer 31 is a polished surface. For example, the upper surface 31A of the insulating layer 31 has a surface roughness smaller than that of the inner surface of the through-hole 31X and a surface roughness smaller than that of the lower surface of the insulating layer 41. The roughness of the upper surface 31A of the insulating layer 31 is set to be, for example, about 15 to 40 nm in terms of the surface roughness Ra value. Further, the roughness of the inner side surface of the through hole 31X and the roughness of the lower surface of the insulating layer 41 are set to be, for example, about 300 to 400 nm in terms of the surface roughness Ra value. Here, the surface roughness Ra value is a kind of numerical value representing the surface roughness, and is called arithmetic average roughness. Specifically, the absolute value of the height changing in the measurement region is expressed as an average line. Measured from the surface and arithmetically averaged.

  A via wiring 32 electrically connected to the wiring layer 22 is formed in the through hole 31X. The via wiring 32 is formed so as to penetrate the insulating layer 31 in the thickness direction. The via wiring 32 of this example is filled in the through hole 31X. Similar to the through hole 31X, the via wiring 32 of the present example is formed in a substantially inverted truncated cone shape in which the upper end surface 32A is larger than the lower end surface. The diameter of the upper end surface 32A of the via wiring 32 can be, for example, about 50 to 70 μm.

  An upper end surface 32 </ b> A of the via wiring 32 is exposed from the upper surface 31 </ b> A of the insulating layer 31. For example, the upper end surface 32A of the via wiring 32 is formed substantially flush with the upper surface 31A of the insulating layer 31. Similar to the upper surface 31A of the insulating layer 31, the upper end surface 32A of the via wiring 32 is a smooth surface (low roughness surface) with few irregularities. For example, the upper end surface 32A of the via wiring 32 is a polished surface. The roughness of the upper end surface 32A of the via wiring 32 is set to be about 15 to 40 nm, for example, in terms of the surface roughness Ra value. As a material for the via wiring 32, for example, copper or a copper alloy can be used.

  An insulating layer 41 and a wiring layer 42 are sequentially stacked on the lower surface 20B of the core substrate 20. The insulating layer 41 is laminated on the lower surface 20 </ b> B of the core substrate 20 so as to cover the wiring layer 23. The thickness of the insulating layer 41 is set to be thinner than, for example, the core substrate 20. For example, the thickness of the insulating layer 41 can be about 40 to 75 μm.

  The wiring layer 42 is stacked on the lower surface of the insulating layer 41. The wiring layer 42 is electrically connected to the wiring layer 23. The wiring layer 42 has a via wiring filled in the through hole 41X and a wiring pattern formed on the lower surface of the insulating layer 41. The thickness of the wiring layer 42 laminated on the lower surface of the insulating layer 41 can be set to about 15 to 35 μm, for example. The line and space (L / S) of the wiring layer 42 can be, for example, about 20 μm / 20 μm. In addition, as a material of the wiring layer 42, copper and a copper alloy can be used, for example.

Next, the structure of the wiring structure 12 will be described.
The wiring structure 12 is a wiring structure laminated on the upper surface 31 </ b> A of the insulating layer 31 formed in the uppermost layer of the wiring structure 11. The wiring structure 12 is a high-density wiring layer in which a wiring layer having a higher wiring density than the wiring structure 11 is formed.

The wiring structure 12 has a structure in which a wiring layer 50, an insulating layer 51, a wiring layer 52, an insulating layer 53, a wiring layer 54, and a protective layer 60 stacked on the insulating layer 31 are sequentially stacked. doing.
Here, as a material of the insulating layers 51 and 53, for example, an insulating resin whose main component is a photosensitive resin such as a phenol resin or a polyimide resin can be used. These insulating layers 51 and 53 may contain a filler such as silica or alumina.

  Further, the wiring layers 50, 52 and 54 are wiring layers thinner than the wiring layer of the wiring structure 11. The thickness of the wiring layers 50 and 52 formed on the insulating layers 31 and 51 can be, for example, about 1 to 3 μm. The thickness of the wiring layer 54 formed on the insulating layer 53 can be set to about 10 to 15 μm, for example. The wiring widths and wiring intervals of the wiring layers 50, 52 and 54 are smaller than the wiring widths and wiring intervals of the wiring layers 22, 23 and 42 in the wiring structure 11. The line and space (L / S) of the wiring layers 50, 52, and 54 can be set to, for example, about 2 μm / 2 μm. The insulating layers 51 and 53 are thinner than the insulating layers 31 and 41 in the wiring structure 11. The thickness of the insulating layers 51 and 53 can be about 3 to 10 μm, for example.

  The wiring layer 50 is stacked on the upper surface 31A of the insulating layer 31 so as to be connected to the upper end surface 32A of the via wiring 32. That is, a part of the lower surface of the wiring layer 50 is in contact with the upper end surface 32A of the via wiring 32, and the wiring layer 50 and the via wiring 32 are electrically connected. In other words, the wiring layer 50 and the via wiring 32 are electrically connected, but are not integrated. Specifically, the wiring layer 50 is, for example, a stacked body of a seed layer 50A (for example, a titanium (Ti) layer and a Cu layer) formed on the upper end surface 32A of the via wiring 32 (for example, a copper (Cu) layer). And a metal layer 50B (for example, Cu layer) formed on the seed layer 50A. That is, the metal layer 50B is connected to the via wiring 32 via the seed layer 50A.

  The seed layer 50A is formed so as to cover the upper end surface 32A of the via wiring 32 and to cover the upper surface 31A of the insulating layer 31 around the upper end surface 32A. The metal layer 50B is formed so as to cover the entire upper surface of the seed layer 50A.

  The insulating layer 51 is formed on the upper surface 31 </ b> A of the insulating layer 31 so as to cover the wiring layer 50. In the insulating layer 51, through holes 51 </ b> X that penetrate through the insulating layer 51 in the thickness direction and expose a part of the upper surface of the wiring layer 50 are formed at required locations.

  The wiring layer 52 is stacked on the upper surface of the insulating layer 51. The wiring layer 52 is electrically connected to the wiring layer 50. The wiring layer 52 has a via wiring filled in the through hole 51 </ b> X and a wiring pattern formed on the upper surface of the insulating layer 51. As a material of the wiring layer 52, for example, copper or a copper alloy can be used.

  The insulating layer 53 is formed on the upper surface of the insulating layer 51 so as to cover the wiring layer 52. In the insulating layer 53, through holes 53X that penetrate the insulating layer 53 in the thickness direction and expose a part of the upper surface of the wiring layer 52 are formed at required locations.

  Here, the through holes 51X and 53X are formed in a tapered shape whose diameter increases from the lower side (wiring structure 11 side) to the upper side (wiring layer 54 side) in FIG. For example, the through holes 51X and 53X are formed in a substantially inverted truncated cone shape in which the opening diameter of the upper opening end is larger than the opening diameter of the lower opening end. The opening diameter of the upper opening end of the through hole 51X can be set to, for example, about 10 to 20 μm.

  On the upper surface 53A of the insulating layer 53, a wiring layer 54 and a recognition mark 54M are formed. The wiring layer 54 includes a via wiring 55 filled in the through hole 53X and a connection terminal P1 protruding upward from the upper surface 53A of the insulating layer 53. The connection terminal P1 is, for example, a columnar connection terminal (metal post) formed so as to extend upward from the upper surface 53A of the insulating layer 53. The recognition mark 54M is formed in a columnar shape so as to extend upward from the upper surface 53A of the insulating layer 53, for example. In addition, as a material of the via wiring 55 and the connection terminal P1, for example, copper or a copper alloy can be used.

  As shown in FIG. 1B, the connection terminal P1 is formed in a mounting area A1 where an electronic component such as a semiconductor chip is mounted. The connection terminal P1 functions as an electronic component mounting pad for electrical connection with the electronic component. The recognition mark 54M is formed in the outer peripheral area A2 outside the mounting area A1. The recognition mark 54M is used as an alignment mark, for example.

  As shown in FIG. 2, the plurality of connection terminals P1 are formed in a matrix in a plan view on the upper surface 53A of the insulating layer 53 in the mounting region A1. Each connection terminal P1 is formed in a substantially circular shape in plan view, for example. That is, the connection terminal P1 of this example is formed in a substantially cylindrical shape. On the other hand, the planar shape of the recognition mark 54M is formed in a shape different from the connection terminal P1, for example. For example, the recognition mark 54M of this example is formed in a substantially rectangular shape in plan view. That is, the recognition mark 54M of this example is formed in a substantially quadrangular prism shape.

  As shown in FIG. 1B, the height of the connection terminal P1 and the height of the recognition mark 54M are set to substantially the same height. The height of the connection terminal P1 and the recognition mark 54M can be, for example, about 10 to 20 μm. The diameter of the connection terminal P1 can be set to, for example, about 20 to 30 μm. The pitch of the connection terminals P1 can be set to about 40 to 60 μm, for example.

  If necessary, a surface treatment layer may be formed on the surface (upper surface and side surfaces, or only the upper surface) of the connection terminal P1. Examples of the surface treatment layer include a gold (Au) layer, a nickel (Ni) layer / Au layer (a metal layer in which a Ni layer and an Au layer are laminated in this order), a Ni layer / palladium (Pd) layer / Au layer ( And a metal layer in which a Ni layer, a Pd layer, and an Au layer are laminated in this order. As these Ni layer, Au layer, and Pd layer, for example, a metal layer (electroless plating metal layer) formed by an electroless plating method can be used. The Ni layer is a metal layer made of Ni or Ni alloy, the Au layer is a metal layer made of Au or Au alloy, and the Pd layer is a metal layer made of Pd or Pd alloy. Further, the surface treatment layer may be formed by subjecting the surface (upper surface and side surfaces or only the upper surface) of the connection terminal P1 to an oxidation treatment such as an OSP (Organic Solderability Preservative) treatment.

  A protective layer 60 that covers the side surface of the wiring layer 54 is formed on the upper surface 53 </ b> A of the insulating layer 53. The protective layer 60 includes a first protective layer 61 formed in the mounting area A1 and a second protective layer 62 formed in the outer peripheral area A2. In the protective layer 60, a groove-shaped opening 60 </ b> X that exposes the upper surface 53 </ b> A of the lower insulating layer 53 is formed between the first protective layer 61 and the second protective layer 62. The first protective layer 61 and the second protective layer 62 are separated from each other by the opening 60X. The opening 60X is formed in an annular shape so as to surround the mounting area A1, for example.

The first protective layer 61 includes a first protective insulating layer 63 provided corresponding to each of the plurality of connection terminals P1, and a second protective insulating layer 64 formed apart from the first protective insulating layer 63. Have.
Each first protective insulating layer 63 is formed so as to be in contact with a part of the side surface of the connection terminal P1 and to cover the side surface of the connection terminal P1. Each first protective insulating layer 63 is formed so as to surround the connection terminal P <b> 1 formed in a substantially cylindrical shape in a ring shape. That is, the first protective insulating layer 63 of this example is formed in a substantially cylindrical shape. The thickness H2 of each first protective insulating layer 63 is set to a thickness equal to or less than the thickness H1 of the connection terminal P1. The thickness H2 of the first protective insulating layer 63 in this example is set to be thinner than the thickness H1 of the connection terminal P1. For this reason, the upper surface of each connection terminal P1 and the side surface on the upper end side of each connection terminal P1 are exposed from the first protective insulating layer 63.

  The second protective insulating layer 64 is formed in a region where the first protective insulating layer 63 is not formed in the mounting region A1. Specifically, the second protective insulating layer 64 is formed on the upper surface 53A of the insulating layer 53 between the adjacent first protective insulating layers 63. The planar shape of the second protective insulating layer 64 can be any shape and any size. As shown in FIG. 2, the second protective insulating layer 64 may be formed in a substantially rhombus shape in plan view, or the second protective insulating layer 64 may be planar so as to extend in one direction (here, the vertical direction in the figure). It may be formed in a substantially band shape. Further, the second protective insulating layer 64 may be formed in a substantially cross shape in plan view so as to extend in two directions (for example, the vertical direction and the horizontal direction in the figure). Note that the thickness H3 (see FIG. 1B) of the second protective insulating layer 64 is set to be substantially the same as the thickness H2 of the first protective insulating layer 63 (see FIG. 1B), for example. ing.

  The first protective layer 61 has an opening exposing the upper surface 53A of the lower insulating layer 53 between the adjacent first protective insulating layers 63 and between the first protective insulating layer 63 and the second protective insulating layer 64. 61X is formed. The opening 61 </ b> X is formed in an annular shape (here, an approximately annular shape) so as to surround each first protective insulating layer 63. The opening 61X of this example is formed in a shape in which the figure 8 is continuous in plan view. The adjacent first protective insulating layers 63 are separated from each other by the opening 61X, and the first protective insulating layer 63 and the second protective insulating layer 64 are separated from each other. In other words, the first protective insulating layer 63 and the second protective insulating layer 64 are defined by the formation of the opening 61X.

  The second protective layer 62 is formed so as to entirely cover the upper surface 53A of the insulating layer 53 in the outer peripheral region A2. The second protective layer 62 is formed in a solid shape, for example. As shown in FIG. 1B, the second protective layer 62 is formed thinner than the first protective layer 61. That is, the thickness H4 of the second protective layer 62 is set to be thinner than the thickness H2 of the first protective insulating layer 63 and thinner than the thickness H3 of the second protective insulating layer 64.

  In the second protective layer 62, for example, an opening 62X that exposes the recognition mark 54M is formed. The second protective layer 62 is formed away from the recognition mark 54M by the opening 62X. The opening 62X is formed so as to penetrate the second protective layer 62 in the thickness direction, and is formed so as to expose the upper surface 53A of the lower insulating layer 53. As shown in FIG. 2, the planar shape of the opening 62 </ b> X can be an arbitrary shape and an arbitrary size. The opening 62X in this example is formed in a substantially cross shape in plan view. A recognition mark 54 </ b> M having a substantially rectangular shape in plan view is formed at a substantially central portion in plan view of the opening 62 </ b> X.

  As a material of the protective layer 60 described above, that is, the first protective layer 61 (the first protective insulating layer 63 and the second protective insulating layer 64) and the second protective layer 62, for example, insulation mainly composed of a photosensitive resin. Can be used. For example, as the material of the protective layer 60, the same material as the insulating layer 53 or a solder resist can be used.

  As shown in FIG. 1A, the solder resist layer 13 is an outermost insulating layer (here, the lowest layer) formed on the lower surface of the wiring structure 11. The solder resist layer 13 is laminated on the lower surface of the insulating layer 41 formed in the lowermost layer of the wiring structure 11 so as to cover the lowermost wiring layer 42 of the wiring structure 11.

  In the solder resist layer 13, an opening 13X is formed for exposing a part of the lowermost wiring layer 42 as the external connection pad P2. The external connection pads P2 are connected to external connection terminals 86 (see FIG. 3) such as solder balls and lead pins used when the wiring board 10 is mounted on a mounting board such as a mother board. . If necessary, a surface treatment layer may be formed on the wiring layer 42 exposed from the opening 13X. Examples of the surface treatment layer include an Au layer, a Ni / Au layer, a Ni layer / Pd layer / Au layer, and the like. Further, the external connection pad P2 may be subjected to an oxidation prevention process such as an OSP process to form a surface treatment layer. Note that the wiring layer 42 exposed from the opening 13X (or the surface treatment layer when a surface treatment layer is formed on the wiring layer 42) itself may be used as the external connection terminal.

  The planar shape of the opening 13X and the external connection pad P2 can be any shape and any size. For example, the planar shape of the opening 13X and the external connection pad P2 can be a circular shape having a diameter of about 200 to 300 μm. In addition, as a material of the solder resist layer 13, for example, a photosensitive insulating resin whose main component is a phenol resin or a polyimide resin can be used. Solder resist layer 13 may contain fillers, such as silica and alumina, for example.

Next, the structure of the semiconductor device 70 will be described with reference to FIG.
The semiconductor device 70 includes the wiring substrate 10, one or a plurality of (here, two) semiconductor chips 80, an underfill resin 85, and an external connection terminal 86.

  The semiconductor chip 80 is flip-chip mounted on the wiring board 10. That is, by connecting the connection terminal 81 disposed on the circuit formation surface (here, the lower surface) of the semiconductor chip 80 to the connection terminal P1 of the wiring substrate 10 via the bonding member 82, the semiconductor chip 80 is connected. The wiring layer 54 is electrically connected via the terminal 81 and the joining member 82.

  As the semiconductor chip 80, for example, a logic chip such as a CPU (Central Processing Unit) chip or a GPU (Graphics Processing Unit) chip can be used. Further, as the semiconductor chip 80, for example, a memory chip such as a DRAM (Dynamic Random Access Memory) chip, an SRAM (Static Random Access Memory) chip, or a flash memory chip can be used. When mounting a plurality of semiconductor chips 80 on the wiring board 10, a logic chip and a memory chip may be combined and mounted on the wiring board 10. For example, a CPU chip and a DRAM chip may be mounted on the wiring board 10, or a GPU chip and a DRAM chip may be mounted on the wiring board 10.

  The size of the semiconductor chip 80 can be, for example, about 3 mm × 3 mm to 12 mm × 12 mm in plan view. Moreover, the thickness of the semiconductor chip 80 can be set to, for example, about 50 to 100 μm.

  For example, a metal post can be used as the connection terminal 81. The connection terminal 81 is a columnar connection terminal extending downward from the circuit formation surface of the semiconductor chip 80. The connection terminal 81 of this example is formed in a columnar shape, for example. The height of such a connection terminal 81 can be about 10-20 micrometers, for example. The diameter of the connection terminal 81 can be set to, for example, about 20 to 30 μm. Moreover, the pitch of the connection terminal 81 can be about 40-60 micrometers, for example. As a material of the connection terminal 81, for example, copper or copper alloy can be used. For example, a gold bump can be used as the connection terminal 81 in addition to the metal post.

  The joining member 82 is joined to the wiring layer 54 and to the connection terminal 81. As the joining member 82, for example, a tin (Sn) layer or lead (Pb) -free solder plating can be used. As a material for solder plating, for example, Sn-silver (Ag) -based, Sn-Cu-based, or Sn-Ag-Cu-based lead-free solder can be used. In addition, the thickness of the joining member 82 can be about 5-15 micrometers, for example.

  The underfill resin 85 is provided so as to fill a gap between the wiring substrate 10 and the semiconductor chip 80. The underfill resin 85 is formed so as to fill the opening 61 </ b> X of the first protective layer 61. As a material of the underfill resin 85, for example, an insulating resin such as an epoxy resin can be used.

  The external connection terminal 86 is formed on the external connection pad P <b> 2 of the wiring board 10. The external connection terminal 86 is, for example, a connection terminal that is electrically connected to a pad provided on a mounting board such as a mother board (not shown). For example, a solder ball or a lead pin can be used as the external connection terminal 86. In this example, solder balls are used as the external connection terminals 86.

  In this embodiment, the wiring structure 11 is an example of a first wiring structure, the wiring structure 12 is an example of a second wiring structure, the wiring layer 22 is an example of a second wiring layer, the insulating layer 31 is an example of a second insulating layer, and a via The wiring 32 is an example of a second via wiring. The wiring layer 52 is an example of a first wiring layer, the insulating layer 53 is an example of a first insulating layer, the via wiring 55 is an example of a first via wiring, and the semiconductor chip 80 is an example of an electronic component.

Next, the operation of the wiring board 10 and the semiconductor device 70 will be described.
A protective layer 60 (first protective insulating layer 63 of the first protective layer 61) is formed on the upper surface 53A of the uppermost insulating layer 53 of the wiring structure 12 so as to be in contact with the side surface of the columnar connecting terminal P1 and surround the connecting terminal P1. I tried to do it. Accordingly, the lower surface of the connection terminal P1 is in contact with the upper surface 53A of the insulating layer 53, and a part of the side surface of the connection terminal P1 is in contact with the protective layer 60. For this reason, compared with the case where the protective layer 60 is not formed, the interface between the connection terminal P1 and the photosensitive resin layer (the insulating layer 53 and the protective layer 60) can be increased. Thereby, the thermal stress resulting from the difference in thermal expansion coefficient between the connection terminal P1 and the photosensitive resin layer can be dispersed, and the stress concentrated in one place can be reduced. As a result, it is possible to suitably suppress the occurrence of cracks at the interface between the connection terminal P1 and the photosensitive resin layer.

  Next, a method for manufacturing the wiring board 10 will be described. In the following description, one wiring board 10 will be described in an enlarged manner. However, actually, after a member to be a plurality of wiring boards 10 is collectively produced on one board, the individual wiring boards 10 are individually separated. It becomes.

  First, in the process shown in FIG. 4A, for example, a through-hole 20X is formed in a copper clad laminate (CCL) to be the core substrate 20, and the inside of the through-hole 20X is formed by a method such as electrolytic plating or paste filling. A through electrode 21 is formed on the substrate. Thereafter, the wiring layer 22 is formed on the upper surface 20A of the core substrate 20 and the wiring layer 23 is formed on the lower surface 20B of the core substrate 20 by, for example, a subtractive method.

  Next, in the step shown in FIG. 4B, an insulating layer 31 that covers the upper surface 20A of the core substrate 20 and the wiring layer 22 is formed, and an insulating layer 41 that covers the lower surface 20B of the core substrate 20 and the wiring layer 23. Form. When using a resin film as the insulating layers 31 and 41, for example, the resin film is laminated on the upper surface 20A and the lower surface 20B of the core substrate 20. And the insulating layers 31 and 41 can be formed by making it heat-process and harden | cure at the temperature (for example, about 130-200 degreeC) more than hardening temperature, pressing a resin film. At this time, voids can be prevented from being entrained by laminating the resin film in a vacuum atmosphere. In addition, as a resin film, the film of the thermosetting resin which has an epoxy resin as a main component can be used, for example. Further, when a liquid or paste insulating resin is used as the insulating layers 31 and 41, the liquid or paste insulating resin is applied to the upper surface 20A and the lower surface 20B of the core substrate 20 by a spin coating method or the like. The insulating layers 31 and 41 can be formed by heat-treating the applied insulating resin at a temperature equal to or higher than the curing temperature and curing it. As the liquid or paste-like insulating resin, for example, a thermosetting resin mainly composed of an epoxy resin can be used.

Subsequently, in the process illustrated in FIG. 5A, the through hole 31 </ b> X is formed at a predetermined position of the insulating layer 31 so that a part of the upper surface of the wiring layer 22 is exposed, and a part of the lower surface of the wiring layer 23 is formed. A through-hole 41X is formed at a predetermined location of the insulating layer 41 so that is exposed. These through holes 31X and 41X can be formed by, for example, a laser processing method using a CO ₂ laser, a UV-YAG laser, or the like. Next, when the through holes 31X and 41X are formed by a laser processing method, a desmear process is performed to remove the resin smear attached to the exposed surfaces of the wiring layers 22 and 23 exposed at the bottoms of the through holes 31X and 41X. . By this desmear process, the inner surface of the through hole 31X and the upper surface 31A of the insulating layer 31 are roughened, and the inner surface of the through hole 41X and the lower surface of the insulating layer 41 are roughened.

  Next, in the step shown in FIG. 5B, the via wiring filled in the through hole 41 </ b> X of the insulating layer 41 is electrically connected to the wiring layer 23 through the via wiring, and is formed on the lower surface of the insulating layer 41. A wiring layer having a stacked wiring pattern is formed. The wiring layer 42 can be formed by using various wiring forming methods such as a semi-additive method and a subtractive method.

  5B, a seed layer (not shown) that covers the entire surface of the insulating layer 31 including the inner surface of the through hole 31X and the entire upper surface of the wiring layer 22 exposed from the through hole 31X is formed. Then, electrolytic plating using the seed layer as a power feeding layer is performed. For example, a seed layer is formed by an electroless copper plating method, and an electrolytic copper plating method using the seed layer as a power feeding layer is performed. As a result, the conductive layer 100 that fills the through-hole 31X and covers the entire upper surface 31A of the insulating layer 31 is formed.

  Subsequently, the conductive layer 100 protruding from the upper surface 31A of the insulating layer 31 is polished by, for example, CMP (Chemical Mechanical Polishing), and a part of the upper surface 31A of the insulating layer 31 that is a roughened surface is polished. As a result, as shown in FIG. 6A, the via wiring 32 filled in the through hole 31X is formed, and the upper end surface 32A of the via wiring 32 is substantially flush with the upper surface 31A of the insulating layer 31. Formed. Further, by polishing a part of the upper surface 31A of the insulating layer 31, the upper surface 31A of the insulating layer 31 is smoothed. For example, the roughness of the upper surface 31A of the insulating layer 31 before polishing is about 300 to 400 nm in terms of surface roughness Ra, whereas the roughness of the upper surface 31A of the insulating layer 31 is 15 in terms of surface roughness Ra by polishing. It can be set to about ˜40 nm. In other words, in this step, the upper surface 31A of the insulating layer 31 is polished so that the upper surface 31A of the insulating layer 31 is smoothed (for example, the surface roughness Ra value is about 15 to 40 nm). Since the inner side surface of the through hole 31X and the lower surface of the insulating layer 41 remain roughened, the upper surface 31A of the insulating layer 31 is rougher than the inner side surface of the through hole 31X and the lower surface of the insulating layer 41. The degree becomes smaller. By polishing in this step, the upper surface 31A of the insulating layer 31 and the upper end surface 32A of the via wiring 32 become polished surfaces.

The wiring structure 11 can be manufactured by the above manufacturing process.
Next, in the step shown in FIG. 6B, the seed layer 50 </ b> A is formed so as to cover the entire upper surface 31 </ b> A of the insulating layer 31 and the entire upper end surface 32 </ b> A of the via wiring 32. This seed layer 50A can be formed, for example, by sputtering or electroless plating. For example, in this step, since the upper surface 31A of the insulating layer 31 is a smooth surface, the seed layer 50A can be uniformly formed on the upper surface 31A by sputtering, and the upper surface of the seed layer 50A is formed smoothly. be able to. For this reason, the seed layer 50A can be formed thinner than the case where the seed layer 50A is formed on the roughened surface by sputtering. For example, when the seed layer 50A is formed by sputtering, titanium (Ti) is first formed on the upper surface 31A and the upper end surface 32A so as to cover the upper surface 31A of the insulating layer 31 and the upper end surface 32A of the via wiring 32. Is deposited by sputtering to form a Ti layer. Thereafter, copper is deposited on the Ti layer by sputtering to form a Cu layer. Thereby, the seed layer 50A having a two-layer structure (Ti layer / Cu layer) can be formed. Thus, by forming the Ti layer below the seed layer 50A, the adhesion between the insulating layer 31 and the seed layer 50A can be improved. Note that the Ti layer may be changed to a TiN layer made of titanium nitride (TiN), and a seed layer 50A having a two-layer structure made of a TiN layer and a Cu layer may be formed. Here, titanium and titanium nitride are metals having higher corrosion resistance than copper. When the seed layer 50A is formed by an electroless plating method, for example, the seed layer 50A made of a Cu layer (single layer structure) can be formed by an electroless copper plating method.

Note that plasma treatment such as O ₂ plasma ashing may be performed on the upper surface 31A of the insulating layer 31 before the seed layer 50A is formed. By performing the plasma treatment, the upper surface 31A of the insulating layer 31 can be roughened. By roughening the upper surface 31A of the insulating layer 31, the adhesion between the seed layer 50A and the insulating layer 31 can be improved. However, since the fine wiring can be formed on the upper surface 31A by reducing the roughness of the upper surface 31A of the insulating layer 31 and improving the smoothness, when performing the plasma treatment, The upper surface 31A of the insulating layer 31 is roughened to the extent that does not hinder the formation.

  Next, in a step shown in FIG. 7A, a resist layer 101 having an opening pattern 101X at a predetermined location is formed on the seed layer 50A. The opening pattern 101X is formed so as to expose a portion of the seed layer 50A corresponding to the formation region of the wiring layer 50 (see FIG. 1). As a material of the resist layer 101, for example, a material having a plating resistance against the plating process in the next step can be used. For example, as a material of the resist layer 101, a photosensitive dry film resist or a liquid photoresist (for example, a dry film resist or a liquid resist such as a novolac resin or an acrylic resin) can be used. For example, when a photosensitive dry film resist is used, a dry film is laminated on the upper surface of the seed layer 50A by thermocompression bonding, and the dry film is patterned by a photolithography method to form a resist layer 101 having an opening pattern 101X. To do. Note that when a liquid photoresist is used, the resist layer 101 can be formed through a similar process. In this step, since the upper surface of the seed layer 50A is a smooth surface, the occurrence of patterning defects in the resist layer 101 formed on the seed layer 50A can be suppressed. That is, the opening pattern 101X can be formed in the resist layer 101 with high accuracy.

  Next, in the step shown in FIG. 7B, using the resist layer 101 as a plating mask, electrolytic plating using the seed layer 50A as a plating power feeding layer is performed on the upper surface of the seed layer 50A. Specifically, by applying an electrolytic plating method (here, electrolytic copper plating method) to the upper surface of the seed layer 50A exposed from the opening pattern 101X of the resist layer 101, a metal layer 50B ( Electrolytic plating metal layer) is formed.

  Subsequently, the resist layer 101 is removed by, for example, an alkaline stripping solution. Next, the unnecessary seed layer 50A is removed by etching using the metal layer 50B as an etching mask. Thereby, as shown in FIG. 8A, the wiring layer 50 is formed on the upper end surface 32 </ b> A of the via wiring 32 and the upper surface 31 </ b> A of the insulating layer 31. As shown in FIG. 8B, the wiring layer 50 includes a seed layer 50A in contact with the upper end surface 32A of the via wiring 32 and a metal layer 50B formed on the seed layer 50A. Thus, the wiring layer 50 is formed by a semi-additive method. Further, since the wiring layer 50 and the via wiring 32 are formed in separate steps, the wiring layer 50 and the via wiring 32 are not integrally formed.

  Next, in the step shown in FIG. 9A, the insulating layer 51 that covers the entire surface (upper surface and side surfaces) of the wiring layer 50 is formed on the upper surface 31 </ b> A of the insulating layer 31. When a resin film is used as the insulating layer 51, for example, the insulating layer 51 can be formed by laminating a resin film on the upper surface 31A of the insulating layer 31 by thermocompression bonding. At this time, voids can be prevented from being entrained by laminating the resin film in a vacuum atmosphere. In addition, as a resin film, the film of photosensitive resins, such as a phenol-type resin and a polyimide-type resin, can be used, for example. When a liquid or paste insulating resin is used as the insulating layer 51, the insulating layer 51 is formed by applying a liquid or paste insulating resin to the upper surface 31A of the insulating layer 31 by spin coating or the like. can do. In addition, as liquid or paste-like insulating resin, photosensitive resins, such as a phenol-type resin and a polyimide-type resin, can be used, for example.

  Subsequently, in the step shown in FIG. 9B, a through hole 51X that penetrates the insulating layer 51 in a thickness direction and exposes the upper surface of the wiring layer 50 at a required portion of the insulating layer 51 by, for example, photolithography. Form. In addition, the roughness of the upper surface of the insulating layer 51 made of such a photosensitive resin can be, for example, about 2 to 10 nm in terms of the surface roughness Ra value. That is, the upper surface of the insulating layer 51 has a lower surface roughness than the inner surface of the through hole 31X and a lower surface roughness than the upper surface 31A of the insulating layer 31.

  Next, in the process shown in FIG. 10, as in the process shown in FIGS. 6B to 8B, via wiring filled in the through hole 51 </ b> X and the via wiring are performed by, for example, a semi-additive method. Then, a wiring layer 52 that is electrically connected to the wiring layer 50 and has a wiring pattern laminated on the upper surface of the insulating layer 51 is formed. At this time, as shown in FIG. 11, the wiring layer 52 has a seed layer 102 covering the entire inner surface of the through hole 51X and the upper surface of the insulating layer 51 around the through hole 51X, and an electrolytic layer formed on the seed layer 102. The copper plating layer 103 is comprised.

  Next, as in the steps shown in FIGS. 9A and 9B, the insulating layer 53 having the through hole 53X exposing a part of the upper surface of the wiring layer 52 is formed on the insulating layer 51. . Subsequently, similarly to the steps shown in FIGS. 6B to 8B, the via wiring 55 filled in the through-hole 53 </ b> X and the wiring layer 52 through the via wiring 55 are formed by, for example, a semi-additive method. And a wiring layer 54 having a connection terminal P1 stacked on the upper surface 53A of the insulating layer 53 is formed. At this time, the wiring layer 54 includes a seed layer 104 that covers the entire inner surface of the through hole 53X and the upper surface of the insulating layer 53 around the through hole 53X, and an electrolytic copper plating layer 105 formed on the seed layer 104. Has been. Further, the connection terminal P1 is formed in a substantially cylindrical shape. If necessary, a surface treatment layer may be formed on the surface of the connection terminal P1.

  Subsequently, in the step illustrated in FIG. 12, the protective layer 60 including the first protective layer 61 and the second protective layer 62 is formed on the upper surface 53 </ b> A of the insulating layer 53. Below, an example of the formation method of the protective layer 60 is demonstrated.

  In the step shown in FIG. 13A, a photosensitive resin layer that covers the entire surface (side surface and upper surface) of the connection terminal P1 and the entire surface (side surface and upper surface) of the recognition mark 54M on the upper surface 53A of the insulating layer 53. 106 is formed. The photosensitive resin layer 106 can be formed, for example, by applying a varnish-like photosensitive resin by a spin coating method. At this time, the photosensitive resin layer 106 is formed following the step formed by the upper surface 53A of the insulating layer 53 and the connection terminal P1. For this reason, the photosensitive resin layer 106 is formed so as to rise at the level difference caused by the connection terminal P1. In the present embodiment, a positive photosensitive resin is used as the material of the photosensitive resin layer 106. However, as the material of the photosensitive resin layer 106, a negative photosensitive resin can also be used.

  Next, in the step shown in FIG. 13B, a photomask 107 for forming the protective layer 60 by patterning the photosensitive resin layer 106 is prepared. The photomask 107 includes a light transmitting portion 107A and a light shielding portion 107B. Then, the photomask 107 is disposed above the photosensitive resin layer 106 and aligned. At the time of this alignment, the recognition mark 54M can be used as an alignment mark.

Subsequently, the photosensitive resin layer 106 disposed at positions corresponding to the openings 60X, 61X, and 62X of the protective layer 60 is exposed through the light transmitting portion 107A of the photomask 107.
Next, in the step shown in FIG. 14A, the photosensitive resin layer 106 is developed. As a result of this development, the photosensitive resin layer 106 irradiated (exposed) with light of a predetermined wavelength is completely removed, and openings 60X, 61X, and 62X that expose the upper surface 53A of the lower insulating layer 53 are formed. Is done. Further, in this step, the development is performed excessively to reduce the thickness of the photosensitive resin layer 106 in the unexposed portion, and thin the photosensitive resin layer 106 in the unexposed portion. Thereby, a part of the upper end side of the connection terminal P <b> 1 is exposed from the photosensitive resin layer 106. At this time, due to the difference in film thickness when the photosensitive resin layer 106 is formed (see the broken line), a difference also occurs in the film thickness of the photosensitive resin layer 106 after excessive development. Specifically, after development, the photosensitive resin layer 106 (that is, the first protective layer 61) disposed in the mounting area A1 is replaced with the photosensitive resin layer 106 (that is, the second protective layer) disposed in the outer peripheral area A2. It is formed thicker than layer 62). Excess development can be realized by setting the development time longer than the general development time, for example.

  By forming the opening 60X by the exposure / development process described above, the first protective layer 61 and the second protective layer 62 are patterned. By forming the opening 61 </ b> X, the first protective insulating layer 63 and the second protective insulating layer 64 are patterned in the first protective layer 61. The recognition mark 54M is exposed from the protective layer 60 by forming the opening 62X.

  Thereafter, the photosensitive resin layer 106 is cured by heat treatment. As a result, as shown in FIG. 14B, the protective layer 60 having the first protective layer 61 and the second protective layer 62 is formed on the upper surface 53 </ b> A of the insulating layer 53.

Through the above manufacturing process, as shown in FIG. 15, the wiring structure 12 can be laminated on the upper surface 31 </ b> A of the insulating layer 31 formed in the uppermost layer of the wiring structure 11.
Next, in the step shown in FIG. 15, the solder resist layer 13 having the opening 13X for exposing the external connection pad P2 defined at a required portion of the lowermost wiring layer 42 of the wiring structure 11 is changed to an insulating layer. Laminate on the lower surface of 41. The solder resist layer 13 can be formed, for example, by laminating a photosensitive solder resist film or applying a liquid solder resist and patterning the resist into a required shape.

If necessary, a surface treatment layer may be formed on the wiring layer 42 exposed from the opening 13X of the solder resist layer 13 (that is, the external connection pad P2).
The wiring board 10 of this embodiment can be manufactured by the above manufacturing process.

Next, a method for manufacturing the semiconductor device 70 will be described.
In the process shown in FIG. 16, the external connection terminal 86 is formed on the external connection pad P2. For example, after appropriately applying a flux on the external connection pad P2, an external connection terminal 86 (here, a solder ball) is mounted and reflowed and fixed at a temperature of about 240 to 260 ° C. Thereafter, the surface is washed to remove the flux.

  In the step shown in FIG. 16, a semiconductor chip 80 having columnar connection terminals 81 is prepared. Since the connection terminal 81 can be manufactured by a known manufacturing method, the illustration is omitted and detailed description is omitted. For example, the connection terminal 81 is manufactured by the following method.

  First, for example, a protective film having an opening for exposing the electrode pad is formed on the circuit formation surface (here, the lower surface) of the semiconductor chip 80, and the seed layer is coated so as to cover the lower surface of the protective film and the lower surface of the electrode pad. Form. Next, a resist layer is formed by exposing a portion of the seed layer corresponding to the formation region of the connection terminal 81 (seed layer covering the lower surface of the electrode pad). Subsequently, columnar connection terminals 81 are formed on the electrode pads by performing electrolytic plating (for example, electrolytic copper plating) using the seed layer as a power feeding layer on the seed layer exposed from the resist layer. To do.

  Subsequently, the bonding member 82 is formed on the lower surface of the connection terminal 81. For example, the bonding member 82 applies solder to the lower surface of the connection terminal 81 by an electrolytic solder plating method using a resist layer formed on the seed layer as a plating mask and using the seed layer as a plating power feeding layer. Can be formed. Thereafter, unnecessary seed layer and resist layer are removed.

  Next, the connection terminal 81 of the semiconductor chip 80 is flip-chip bonded onto the connection terminal P1 (wiring layer 54) of the wiring board 10. For example, after the wiring substrate 10 and the semiconductor chip 80 are aligned, a reflow process is performed to melt the bonding member 82 (solder plating layer), and the connection terminal 81 is electrically connected to the connection terminal P1.

  Thereafter, an underfill resin 85 (see FIG. 3) is filled between the semiconductor chip 80 and the wiring substrate 10 which are flip-chip bonded, and the underfill resin 85 is cured. At this time, since the opening 61 </ b> X is formed in the first protective layer 61, the capillary phenomenon becomes remarkable, so that the filling property of the underfill resin 85 can be improved.

The semiconductor device 70 shown in FIG. 3 can be manufactured by the above manufacturing process.
(simulation result)
Next, simulation results obtained by analyzing the stress distribution in the semiconductor device 70 described above will be described.

First, a sample for evaluation, that is, the model structure (example sample) shown in FIG. 17A and the model structure (comparative example sample) shown in FIG. 17B will be described.
As shown in FIG. 17A, the example sample has a structure substantially similar to the semiconductor device 70 having the structure shown in FIG. As simulation conditions, the planar shape of the semiconductor chip 80 is 150 μm × 150 μm, the diameter of the lower end surface of the via wiring 55 is 10 μm, the diameter of the connection terminal P1 is 25 μm, the thickness of the connection terminal P1 is 10 μm, and the diameter of the connection terminal 81 is The thickness of 22 μm and the connection terminal 81 was 25 μm. In the example sample, the protective layer 60 (first protective layer 61) is formed so as to cover the entire side surface of the connection terminal P1.

  On the other hand, as shown in FIG. 17B, in the comparative sample, the connection terminal P1 is formed so as to protrude upward from the upper surface 53A of the insulating layer 53, and the protective layer 60 is formed on the upper surface 53A of the insulating layer 53. Is not formed. For this reason, in the comparative example sample, the side surface of the connection terminal P1 is covered with the joining member 82A. The simulation conditions are the same as the simulation conditions in the example sample except that the protective layer 60 is not formed.

  FIG. 18A shows a simulation result obtained by analyzing the distribution of stress generated at the interface between the connection terminal P1 and the photosensitive resin layer (the insulating layer 53 and the protective layer 60) in the example sample. FIG. 18B shows a simulation result obtained by analyzing the distribution of stress generated at the interface between the connection terminal P1 and the photosensitive resin layer (insulating layer 53) in the comparative sample.

  As shown in FIG. 18B, in the comparative sample, stress is concentrated immediately below the corner of the connection terminal P1, that is, at the interface between the lower surface of the connection terminal P1 and the upper surface of the insulating layer 53. And the stress which arises in the interface of the connection terminal P1 and the insulating layer 53 in a comparative example sample was about 146.0 MPa. On the other hand, as shown in FIG. 18A, in the example sample, the stress generated at the interface between the connection terminal P1 and the photosensitive resin layer is dispersed. Thereby, in the example sample, the stress concentrated on the interface between the lower surface of the connection terminal P1 and the upper surface of the insulating layer 53 is reduced. Specifically, the stress generated at the interface between the connection terminal P1 and the insulating layer 53 in the example sample is about 100.2 MPa, which is significantly smaller than that of the comparative example sample.

  As described above, by forming the protective layer 60 (photosensitive resin layer) so as to surround the connection terminal P1, the stress concentrated in one place at the interface between the connection terminal P1 and the photosensitive resin layer is reduced. It was confirmed. Thereby, it can suppress suitably that a crack generate | occur | produces in the interface of the connecting terminal P1 and the photosensitive resin layer.

According to this embodiment described above, the following effects can be obtained.
(1) The protective layer 60 (the first protective insulating layer 63 of the first protective layer 61) surrounding the connection terminal P1 in contact with the side surface of the columnar connection terminal P1 is formed. Thereby, since the interface between the connection terminal P1 and the photosensitive resin layer (the protective layer 60 and the insulating layer 53) can be increased, the stress generated at the interface between the connection terminal P1 and the photosensitive resin layer can be dispersed. it can. For this reason, the stress concentrated on one place at the interface between the connection terminal P1 and the photosensitive resin layer can be reduced. As a result, it is possible to suitably suppress the occurrence of cracks at the interface between the connection terminal P1 and the photosensitive resin layer.

  (2) The first protective layer 61 and the second protective layer 62 were formed apart from each other by the opening 60X. For this reason, it can suppress suitably that underfill resin 85 spreads outside the mounting field A1. That is, the second protective layer 62 formed outside the opening 60X can function as a dam that stops the underfill resin 85. Moreover, since the 1st protective layer 61 and the 2nd protective layer 62 can be isolate | separated by the opening part 60X, the curvature by the thermal contraction of resin can be reduced.

  (3) The first protective layer 61 is formed thicker than the second protective layer 62. Thereby, the curvature of the wiring board 10 can be suppressed compared with the case where the 1st protective layer 61 and the 2nd protective layer 62 are formed in substantially the same thickness.

  More specifically, as shown in FIG. 19, in the case of the comparative example in which the first protective layer 61 and the second protective layer 62 are formed to have substantially the same thickness, the wiring structure 12 side tends to warp in a concave shape. This is because the outer peripheral area A2 has a lower wiring density than the mounting area A1, and the thermal expansion coefficient (for example, about 50 to 70 ppm / ° C.) of the protective layer 60 (photosensitive resin layer) is the connection terminal P1 (copper layer). This is due to the fact that the coefficient of thermal expansion is higher (for example, about 17 ppm / ° C.). Specifically, when the first protective layer 61 and the second protective layer 62 are formed to have substantially the same thickness, the content of the photosensitive resin in the outer peripheral region A2 is larger than the content of the photosensitive resin in the mounting region A1. Become more. Then, since heat shrinkage is larger in the outer peripheral area A2 than in the mounting area A1, the outer peripheral area A2 warps toward the mounting area A1, and the wiring structure 12 side warps in a concave shape. On the other hand, in the present embodiment, the first protective layer 61 in the mounting region A1 is formed thicker than the second protective layer 62 in the outer peripheral region A2. Thereby, the difference of content of the photosensitive resin in mounting area | region A1 and content of the photosensitive resin in outer peripheral area | region A2 can be made small. As a result, the warpage of the wiring substrate 10 can be suppressed as compared with the case where the first protective layer 61 and the second protective layer 62 are formed to have substantially the same thickness. An example of an evaluation result indicating this is shown in FIG.

  FIG. 20 shows a result of a warping simulation performed on the wiring board 10 (Example) shown in FIG. Specifically, the planar shape of the wiring substrate 10 was a square shape of 40 mm × 40 mm, and the planar shape of the mounting region A1 was a rectangular shape of 20 mm × 10 mm. The core substrate 20 has a thickness of 800 μm, the wiring layers 22 and 23 in the wiring structure 11 have a thickness of 25 μm, the wiring layer 42 has a thickness of 15 μm, and the insulating layers 31 and 41 in the wiring structure 11 have a thickness of The thickness of 40 μm and the solder resist layer 13 was 20 μm. Furthermore, the thickness of the wiring layers 50 and 52 in the wiring structure 12 is 2.5 μm, the thickness of the connection terminal P1 is 10 μm, and the thickness of the insulating layers 51 and 53 in the wiring structure 12 is 5 μm. In such a wiring substrate 10, a warping simulation was performed when the thickness of the first protective layer 61 was 5 μm and the thickness of the second protective layer 62 was 3 μm. As a comparative example, when the first protective layer 61 and the second protective layer 62 are set to the same thickness as in the wiring substrate shown in FIG. A simulation of warping was also performed when the thickness was 3 μm and the thickness of the second protective layer 62 was 3 μm.

  As is apparent from the simulation results shown in FIG. 20, the first protective layer 61 and the second protective layer 62 have the same thickness by forming the first protective layer 61 thicker than the second protective layer 62. It was confirmed that the amount of warping of the wiring board 10 can be reduced as compared with the example.

  (4) The second protective insulating layer 64 is patterned between the adjacent first protective insulating layers 63. In other words, the opening 61 </ b> X is formed between the first protective insulating layer 63 and the second protective insulating layer 64 so as to surround the first protective insulating layer 63. By forming the opening 61X, when the underfill resin 85 is filled between the wiring substrate 10 and the semiconductor chip 80, the capillary phenomenon becomes remarkable, so that the filling property of the underfill resin 85 is improved. Can do.

  (5) Further, since the second protective insulating layer 64 is left between the adjacent first protective insulating layers 63, it is necessary to fill the space between the adjacent connection terminals with the underfill resin 85 as in the prior art. Disappear. That is, the area filled with the underfill resin 85 can be reduced as compared with the prior art. Thereby, generation | occurrence | production of a void etc. in the underfill resin 85 can be suppressed suitably. In addition, since the capillary phenomenon becomes more noticeable by forming the second protective insulating layer 64, the filling property of the underfill resin 85 can be improved.

  (6) Furthermore, since the second protective insulating layer 64 is formed, the contact area between the first protective layer 61 and the underfill resin 85 can be increased. Further, the second protective insulating layer 64 is formed so as to bite into the underfill resin 85. Thereby, a big anchor effect comes to be acquired and the adhesiveness of the 1st protective layer 61 and the underfill resin 85 can be improved.

(Second Embodiment)
Hereinafter, a second embodiment will be described with reference to FIG. The wiring board 10A of this embodiment is different from the first embodiment in that the wiring structure 11 is replaced with the wiring structure 11A. Hereinafter, the difference from the first embodiment will be mainly described. The same members as those shown in FIGS. 1 to 20 are denoted by the same reference numerals, and detailed description of these elements is omitted.

  As shown in FIG. 21, the wiring substrate 10A includes a wiring structure 11A, a wiring structure 12 stacked on the upper side of the wiring structure 11A, and a solder resist layer 13 stacked on the lower side of the wiring structure 11A. Yes.

  The wiring structure 11A is a low-density wiring layer in which a wiring layer having a wiring density lower than that of the wiring structure 12 is formed. On the upper surface 20 </ b> A of the core substrate 20, an insulating layer 33 that covers the wiring layer 22, a wiring layer 34, an insulating layer 31, and a via wiring 32 are sequentially stacked. On the lower surface 20 </ b> B of the core substrate 20, an insulating layer 43 that covers the wiring layer 23, a wiring layer 44, an insulating layer 41, and a wiring layer 42 are sequentially stacked.

  As a material of the insulating layers 33, 31, 43, 41, for example, a non-photosensitive insulating resin whose main component is a thermosetting resin such as an epoxy resin or a polyimide resin can be used. These insulating layers 33, 31, 43, and 41 may contain a filler such as silica or alumina, for example. As a material of the wiring layers 34, 44, 42 and the via wiring 32, for example, copper or a copper alloy can be used. Moreover, the thickness of the insulating layers 33, 31, 43, and 41 can be set to about 20 to 45 μm, for example. The thickness of the wiring layers 34, 44, 42 can be set to about 15 to 35 μm, for example. The line and space (L / S) of the wiring layers 34, 44, 42 can be set to about 20 μm / 20 μm, for example.

  In the insulating layer 33, a through hole 33 </ b> X that penetrates the insulating layer 33 in the thickness direction and exposes a part of the upper surface of the wiring layer 22 is formed at a required location. In the insulating layer 31, a through hole 31 </ b> X that penetrates the insulating layer 31 in the thickness direction and exposes a part of the upper surface of the wiring layer 34 is formed at a required location. These through holes 33X and 31X are formed in a tapered shape whose diameter increases from the lower side (core substrate 20 side) to the upper side (wiring structure 12 side) in FIG. The wiring layer 34 has via wiring filled in the through hole 33 </ b> X and electrically connected to the wiring layer 22. The via wiring 32 is filled in the through hole 31 </ b> X and is electrically connected to the wiring layer 34. The wiring structure 12 is laminated on the upper surface 31A of the insulating layer 31 and the upper end surface 32A of the via wiring 32.

  On the other hand, the insulating layer 43 is formed with through holes 43X that penetrate the insulating layer 43 in the thickness direction and expose a part of the lower surface of the wiring layer 23 at a required location. In the insulating layer 41, through holes 41 </ b> X that penetrate the insulating layer 41 in the thickness direction and expose a part of the lower surface of the wiring layer 44 are formed at required locations. These through holes 43X and 41X are formed in a tapered shape whose diameter increases from the upper side (core substrate 20 side) to the lower side (solder resist layer 13 side) in FIG. The wiring layer 44 has via wiring filled in the through hole 43 </ b> X and electrically connected to the wiring layer 23. The wiring layer 42 has via wiring filled in the through hole 41 </ b> X and electrically connected to the wiring layer 44.

Thus, even when the insulating layer and the wiring layer are laminated on the upper and lower surfaces of the core substrate 20, the same effects as the effects (1) to (6) of the first embodiment can be obtained. Can do.
In this embodiment, the wiring structure 11A is an example of the first wiring structure, the wiring layer 34 is an example of the second wiring layer, the insulating layer 31 is an example of the second insulating layer, and the via wiring 32 is an example of the second via wiring. It is.

(Third embodiment)
The third embodiment will be described below with reference to FIG. The wiring board 10B of this embodiment is different from the first embodiment in that the wiring structure 11 is replaced with the wiring structure 11B and the wiring structure 12 is replaced with the wiring structure 12B. Hereinafter, the difference from the first embodiment will be mainly described. The same members as those shown in FIGS. 1 to 21 are denoted by the same reference numerals, and detailed description of these elements is omitted.

  As shown in FIG. 22, the wiring board 10B includes a wiring structure 11B, a wiring structure 12B stacked on the upper side of the wiring structure 11B, and a solder resist layer 13 stacked on the lower side of the wiring structure 11B. Yes.

  The wiring structure 11B is a wiring structure that does not have a stacked structure in which insulating layers and wiring layers are stacked in multiple layers, and is a low-density wiring layer in which a wiring layer having a lower wiring density than the wiring structure 12B is formed. In the wiring structure 11B, only the insulating layer 37 is stacked on the upper surface 20A of the core substrate 20, and the insulating layer 47 and the wiring layer 48 are stacked on the lower surface 20B of the core substrate 20. As a material of the insulating layers 37 and 47, for example, a non-photosensitive insulating resin whose main component is a thermosetting resin such as an epoxy resin or a polyimide resin can be used. These insulating layers 37 and 47 may contain a filler such as silica or alumina. As a material of the wiring layer 48, for example, copper or a copper alloy can be used. The thickness of the insulating layers 37 and 47 can be about 20 to 45 μm, for example. The thickness of the wiring layer 48 can be about 15 to 35 μm, for example.

  The core substrate 20, the insulating layer 37, and the insulating layer 47 are formed with through holes 20Y that penetrate the core substrate 20 and the insulating layers 37, 47 in the thickness direction. A through electrode 21 is formed in the through hole 20Y. The through electrode 21 is formed, for example, so as to fill the through hole 20Y. The upper end surface of the through electrode 21 is exposed from the upper surface of the insulating layer 37, and the lower end surface of the through electrode 21 is exposed from the lower surface of the insulating layer 47. For example, the upper end surface of the through electrode 21 is formed to be substantially flush with the upper surface of the insulating layer 37, and the lower end surface of the through electrode 21 is formed to be substantially flush with the lower surface of the insulating layer 47. The upper end surface of the through electrode 21 is directly joined to the via wiring V1 included in the wiring layer 52 in the wiring structure 12B. The lower end surface of the through electrode 21 is directly bonded to the wiring layer 48.

  The wiring structure 12B does not have the wiring layer 50, and the lower end surface of the via wiring V1 is directly joined to the upper end surface of the through electrode 21. The insulating layer 51 is formed so as to cover the entire upper surface of the insulating layer 37 exposed from the via wiring V1.

  The solder resist layer 13 is formed on the lower surface of the insulating layer 47 so as to cover the lowermost wiring layer 48. The solder resist layer 13 is formed with an opening 13X for exposing a part of the lowermost wiring layer 48 as the external connection pad P2.

  Thus, even when the wiring structure 11B does not have a laminated structure in which the insulating layer and the wiring layer are laminated in multiple layers, the same effects as the effects (1) to (6) of the first embodiment are obtained. Can play.

(Fourth embodiment)
Hereinafter, a fourth embodiment will be described with reference to FIG. The wiring board 10C of this embodiment is different from the first embodiment in that the wiring structure 11 is replaced with the wiring structure 11C. Hereinafter, the difference from the first embodiment will be mainly described. The same members as those shown in FIGS. 1 to 22 are denoted by the same reference numerals, and detailed description of these elements is omitted.

  As shown in FIG. 23, the wiring structure 11C is a wiring structure that does not have the core substrate 20, and is a low-density wiring layer in which a wiring layer having a lower wiring density than the wiring structure 12 is formed. The wiring structure 11C has a structure in which a wiring layer 110, an insulating layer 111, a wiring layer 112, an insulating layer 113, a wiring layer 114, an insulating layer 115, and a via wiring 116 are sequentially stacked. . As a material of the insulating layers 111, 113, and 115, for example, a non-photosensitive insulating resin whose main component is a thermosetting resin such as an epoxy resin or a polyimide resin can be used. These insulating layers 111, 113, and 115 may contain, for example, a filler such as silica or alumina, or may contain a reinforcing material. As a material of the wiring layers 112 and 114 and the via wiring 116, for example, copper or a copper alloy can be used. Moreover, the thickness of the insulating layers 111, 113, and 115 can be set to about 20 to 45 μm, for example. The thickness of the wiring layers 110, 112, and 114 can be set to about 15 to 35 μm, for example. The line and space (L / S) of the wiring layers 110, 112, and 114 can be set to about 20 μm / 20 μm, for example.

  The wiring layer 110 is the lowermost wiring layer of the wiring structure 11C. For example, the lower surface of the wiring layer 110 is exposed from the insulating layer 111. For example, the lower surface of the wiring layer 110 is formed to be substantially flush with the lower surface of the insulating layer 111. For example, as the wiring layer 110, a structure in which a first conductive layer (for example, Cu layer) and a second conductive layer (for example, Ni layer / Au layer) are stacked can be employed. In this case, the wiring layer 110 is formed so that the Au layer is exposed from the insulating layer 111.

  The insulating layer 111 is formed so as to cover the upper surface and side surfaces of the wiring layer 110 and to expose the lower surface of the wiring layer 110. In the insulating layer 111, through holes 111X that penetrate the insulating layer 111 in the thickness direction and expose a part of the upper surface of the wiring layer 110 are formed at required locations.

  The wiring layer 112 is stacked on the upper surface of the insulating layer 111. The wiring layer 112 includes a via wiring filled in the through hole 111 </ b> X, and a wiring pattern that is electrically connected to the wiring layer 110 through the via wiring and is stacked on the upper surface of the insulating layer 111. .

  The insulating layer 113 is formed on the upper surface of the insulating layer 111 so as to cover the wiring layer 112. In the insulating layer 113, a through hole 113 </ b> X that penetrates the insulating layer 113 in the thickness direction and exposes a part of the upper surface of the wiring layer 112 is formed at a required location.

  The wiring layer 114 is stacked on the upper surface of the insulating layer 113. The wiring layer 114 has a via wiring filled in the through hole 113X, and a wiring pattern electrically connected to the wiring layer 112 through the via wiring and stacked on the upper surface of the insulating layer 113. .

  The insulating layer 115 is formed on the upper surface of the insulating layer 113 so as to cover the wiring layer 114. The insulating layer 115 is formed with a through hole 115 </ b> X that opens at a required position on the upper surface of the insulating layer 115 and penetrates the insulating layer 115 in the thickness direction to expose a part of the upper surface of the wiring layer 114. Yes.

  Here, the through holes 111X, 113X, and 115X are formed in a tapered shape whose diameter increases from the lower side (solder resist layer 13 side) to the upper side (wiring structure 12 side) in FIG. That is, all of the through holes 111X, 113X, and 115X formed in the wiring structure 11C are formed in a tapered shape in which the opening on the wiring structure 12 side is expanded with respect to the opening on the solder resist layer 13 side. . In addition, the opening diameter of the upper opening end of the through holes 111X, 113X, and 115X can be set to, for example, about 60 to 70 μm.

  In the through-hole 115X, a via wiring 116 that electrically connects the wiring layer 114 and the wiring layer 50 formed on the upper surface 115A of the insulating layer 115 is formed. For example, the via wiring 116 is filled in the through hole 115X. For this reason, the via wiring 116 is formed in the same shape as the through hole 115X. For example, the upper end surface 116A of the via wiring 116 is formed to be substantially flush with the upper surface 115A of the insulating layer 115.

  On the upper surface 115A of the insulating layer 115 and the upper end surface 116A of the via wiring 116, the wiring structure 12 is laminated. For example, the wiring layer 50 of the wiring structure 12 is stacked on the upper surface 115A of the insulating layer 115 so as to be connected to the upper end surface 116A of the via wiring 116. Here, the upper surface 115A of the insulating layer 115 and the upper end surface 116A of the via wiring 116 are, for example, similar to the upper surface 31A of the insulating layer 31 and the upper end surface 32A of the via wiring 32 of the first embodiment (see FIG. 1). It may be a polished surface.

  On the other hand, the solder resist layer 13 is formed on the lower surface of the insulating layer 111 so as to cover the lowermost wiring layer 110. In the solder resist layer 13, an opening 13X is formed for exposing a part of the lowermost wiring layer 110 as the external connection pad P2.

Thus, even when the wiring structure 11C does not have the core substrate 20, the same effects as the effects (1) to (6) of the first embodiment can be obtained.
In the present embodiment, the wiring structure 11C is an example of a first wiring structure, the wiring layer 114 is an example of a second wiring layer, the insulating layer 115 is an example of a second insulating layer, and the via wiring 116 is an example of a second via wiring. .

(Other embodiments)
In addition, the said embodiment can also be implemented in the following aspects which changed this suitably.
24, as shown in FIG. 24, on the upper surface of the first protective insulating layer 63, from the side surface side of the connection terminal P1, a curved portion 63A that is curved in a direction away from the connection terminal P1 is formed. Also good. With such a curved portion 63A, the fluidity of the underfill resin 85 (see FIG. 3) can be improved, and as a result, the filling property of the underfill resin 85 can be improved. In this case, the thickness H12 of the second protective insulating layer 64 is thinner than the thickness H11 of the first protective insulating layer 63 that is in most contact with the side surface of the connection terminal P1. Further, the thickness H13 of the second protective layer 62 is thinner than the thickness H12 of the second protective insulating layer 64. In other words, the upper surface of the second protective insulating layer 64 is lower than the top (upper end) of the first protective insulating layer 63 that is in most contact with the side surface of the connection terminal P1. Further, the upper surface of the second protective layer 62 is lower than the upper surface of the second protective insulating layer 64. In the illustrated example, the curved portion 63A is formed on the entire upper surface of the first protective insulating layer 63, but the curved portion 63A is formed only on a part of the upper surface of the first protective insulating layer 63. Also good. Further, a curved portion that is recessed in a curved shape may be formed on the upper surface of the second protective insulating layer 64 in the same manner as the curved portion 63A.

  -As shown in FIG. 25, it is good also considering the upper surface and side surface of the connecting terminal P1 as a roughening surface. For example, the surface roughness of the upper surface and the side surface of the connection terminal P <b> 1 may be larger than the surface roughness of the wiring layer 52. Thereby, the adhesiveness of the connection terminal P1 and the protective layer 60 can be improved.

  As shown in FIG. 25, a raised portion 63 </ b> B that rises upward may be formed on the upper surface of the first protective insulating layer 63. The raised portion 63B is formed, for example, in such a shape that the top portion T1 (upper end portion) is pointed like a needle in a sectional view. Specifically, the raised portion 63B includes an inclined portion B1 inclined downward from the top portion T1 toward the connection terminal P1, and an inclined portion B2 inclined downward from the top portion T1 toward the direction away from the connection terminal P1. It is composed of In the illustrated example, the inclined portion B1 is formed so as to be curved in a curved shape from the top T1 toward the connection terminal P1, and the inclined portion B2 is curved in a direction away from the connection terminal P1 from the top T1. It is formed to be recessed. Such a raised portion 63B (particularly, the inclined portion B1) can suitably suppress the bonding member 82 (see FIG. 3) such as solder plating from spreading outside the connection terminal P1. Moreover, the fluidity | liquidity of the underfill resin 85 (refer FIG. 3) can be improved by inclination part B2 dented in curved shape.

Note that the top T1 does not necessarily have a sharp shape like a needle. For example, the top portion T1 may be formed in a shape having a flat surface.
-You may abbreviate | omit formation of the opening part 61X in each said embodiment and said each modification. In this case, for example, the first protective insulating layer 63 and the second protective insulating layer 64 are continuously formed integrally.

-You may abbreviate | omit the 2nd protective insulating layer 64 in said each embodiment and each said modification.
-You may make it plasma-process on the surface (an upper surface and a side surface, or only an upper surface) of the protective layer 60 in each said embodiment and said each modification. Thereby, the wettability in the protective layer 60 can be improved.

  In each of the above embodiments, the upper end surface 32A of the via wiring 32 is formed to be flush with the upper surface 31A of the insulating layer 31. For example, the upper end surface 32A of the via wiring 32 may be formed so as to be recessed below the upper surface 31A of the insulating layer 31. Further, the upper end surface 32A of the via wiring 32 may be formed so as to protrude above the upper surface 31A of the insulating layer 31.

  -The cross-sectional shape of the through-hole formed in the wiring board 10, 10A-10C of each said embodiment and said each modification is not specifically limited. For example, the through holes formed in the wiring boards 10, 10A to 10C may be formed in a straight shape (substantially rectangular shape in cross section).

The number of wiring layers and insulating layers in the wiring structures 11 and 11A to 11C in each of the embodiments and the modifications described above, and the routing of the wiring can be variously modified and changed.
-The number of wiring layers and insulating layers in the wiring structures 12 and 12B in each of the above-described embodiments and the above-described modified examples, the wiring arrangement, and the like can be variously modified and changed.

  In place of the semiconductor chip 80, the wiring boards 10 and 10A to 10C according to the above embodiments and the above modifications are replaced with semiconductor components such as chip capacitors, chip resistors and chip inductors, and electronic devices other than semiconductor chips such as crystal resonators. You may make it mount components.

  In addition, the mounting form (for example, flip chip mounting, wire bonding mounting, solder mounting, or a combination thereof) of electronic components such as the semiconductor chip 80, chip components, and crystal units can be variously modified and changed. It is.

  In each of the above embodiments, the upper and lower wiring layers of the core substrate 20 are electrically connected to each other through the through electrodes 21 filling the through holes 20X and 20Y of the core substrate 20. For example, the upper and lower wiring layers of the core substrate 20 may be electrically connected to each other via through hole plating layers (through electrodes) provided on the inner walls of the through holes 20X and 20Y. . In this case, the holes of the through holes 20X and 20Y formed inside the through hole plating layer may be filled with resin.

10, 10A to 10C wiring board 11, 11A to 11C wiring structure (first wiring structure)
12, 12B Wiring structure (second wiring structure)
22, 34, 114 Wiring layer (second wiring layer)
31, 115 Insulating layer (second insulating layer)
32 Via wiring (second via wiring)
52 Wiring layer (first wiring layer)
53 Insulating layer (first insulating layer)
53X Through hole 55 Via wiring (first via wiring)
60 protective layer 60X opening (first opening)
61 1st protective layer 61X Opening part (2nd opening part)
62 second protective layer 63 first protective insulating layer 63A curved portion 63B raised portion 64 second protective insulating layer 70 semiconductor device 80 semiconductor chip (electronic component)
106 Photosensitive resin layer A1 Mounting area A2 Outer peripheral area B1, B2 Inclined part P1 Connection terminal T1 Top part

Claims (10)

A first wiring layer;
A first insulating layer made of an insulating resin containing a photosensitive resin as a main component and covering the first wiring layer;
A first via wiring formed in a through hole that penetrates the first insulating layer in a thickness direction and exposes the first wiring layer;
A connection terminal electrically connected to the first wiring layer via the first via wiring, protruding upward from the upper surface of the first insulating layer, and connected to an electronic component;
A protective layer formed on an upper surface of the first insulating layer so as to cover a side surface of the connection terminal, comprising an insulating resin having a photosensitive resin as a main component;
The protective layer is
A first protective layer that is formed in a mounting region where the electronic component is mounted, and is formed so as to surround the connection terminal in contact with a side surface of the connection terminal;
In the outer peripheral region outside the mounting region, a first opening exposing the upper surface of the first insulating layer is formed apart from the first protective layer, and is formed thinner than the first protective layer. A wiring board comprising two protective layers.   The wiring board according to claim 1, wherein a thickness of the first protective layer is thinner than the connection terminal. The first protective layer is formed between a first protective insulating layer formed so as to surround each of the plurality of connection terminals and the adjacent first protective insulating layer, and is separated from the first protective insulating layer. A second protective insulating layer formed as described above,
Between the first protective insulating layer and the second protective insulating layer, and between the adjacent first protective insulating layers, a second opening that exposes an upper surface of the first insulating layer is the first protective layer. The wiring board according to claim 1, wherein the wiring board is formed so as to surround the insulating layer.   4. The curved portion that is recessed in a curved shape from the side surface side of the connection terminal toward the direction away from the connection terminal is formed on the upper surface of the first protective insulating layer. Wiring board. On the upper surface of the first protective insulating layer, a raised portion that rises upward is formed,
The raised portion is formed so as to be recessed in a curved shape from the top portion of the raised portion toward the connection terminal, and is formed so as to be recessed in a curved shape from the top portion in a direction away from the connection terminal. The wiring board according to claim 3, wherein the wiring board is provided.   The wiring board according to claim 1, wherein an upper surface and a side surface of the first wiring layer are roughened surfaces. A second wiring layer; a second insulating layer covering the second wiring layer; and the second insulating layer passing through the second insulating layer in a thickness direction and electrically connected to the second wiring layer; A first wiring structure including a second via wiring having an upper end surface exposed from the first wiring structure;
A second wiring structure laminated on the upper surface of the second insulating layer and the upper end surface of the second via wiring;
The second wiring structure includes the first wiring layer electrically connected to the second via wiring, the first insulating layer, the first via wiring, the connection terminal, and the protective layer. Including
The wiring board according to any one of claims 1 to 6, wherein a wiring width and a wiring interval of the first wiring layer are smaller than a wiring width and a wiring interval of the second wiring layer. The wiring board according to any one of claims 1 to 7,
A semiconductor chip flip-chip mounted on the connection terminal;
A semiconductor device comprising: Forming a first wiring layer;
A step of forming a first insulating layer made of an insulating resin having a photosensitive resin as a main component and covering the first wiring layer;
Forming a first via wiring penetrating through the first insulating layer in a thickness direction, electrically connected to the first wiring layer via the first via wiring, and extending upward from an upper surface of the first insulating layer; Forming a column-shaped connection terminal protruding into
A step of forming a protective layer covering the side surface of the connection terminal on the upper surface of the first insulating layer, comprising an insulating resin containing a photosensitive resin as a main component;
In the step of forming the protective layer,
A first protective layer formed in a mounting region where an electronic component connected to the connection terminal is mounted, and in contact with a side surface of the connection terminal so as to surround the connection terminal; and an outer side of the mounting region In the outer peripheral region, the second protective layer is formed so as to be separated from the first protective layer by a first opening that exposes the upper surface of the first insulating layer, and is formed thinner than the first protective layer. A method of manufacturing a wiring board, wherein a protective layer is formed. The step of forming the protective layer includes:
Applying a varnish-like photosensitive resin to the upper surface of the first insulating layer, and forming a photosensitive resin layer covering the entire surface of the connection terminal;
The method of manufacturing a wiring board according to claim 9, further comprising: patterning the photosensitive resin layer by exposure and development, and forming the protective layer by thinning the photosensitive resin layer. Method.