JP2012074449A - Mounting substrate - Google Patents
Mounting substrate Download PDFInfo
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- JP2012074449A JP2012074449A JP2010216734A JP2010216734A JP2012074449A JP 2012074449 A JP2012074449 A JP 2012074449A JP 2010216734 A JP2010216734 A JP 2010216734A JP 2010216734 A JP2010216734 A JP 2010216734A JP 2012074449 A JP2012074449 A JP 2012074449A
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- solder resist
- mounting substrate
- groove
- shape
- chip
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- Electric Connection Of Electric Components To Printed Circuits (AREA)
- Wire Bonding (AREA)
Abstract
Description
本発明は、ＩＣチップ等を実装する実装基板に係り、特には、アンダーフィルをＩＣチップと実装基板とがなす隙間に短時間でボイドを発生させずに導入するために、実装基板の表面を被覆しているソルダーレジストが備えるべきソルダーレジストの表面構造に関する。 The present invention relates to a mounting substrate on which an IC chip or the like is mounted. In particular, in order to introduce an underfill into a gap formed between an IC chip and a mounting substrate in a short time without generating a void, the surface of the mounting substrate is The present invention relates to a surface structure of a solder resist to be provided with the solder resist to be coated.
図１はＩＣチップ１aを実装した実装基板５aの断面視の図であるが、該実装基板においては、半田バンプ２同士が融着しないようにソルダーレジスト層６aが設けられる。このソルダーレジスト層６aに開口部を設け、この開口部直下に露出した配線部をＦＣパッド４として、該パッド上に半田バンプ２を敷設しＩＣチップ１aとの半田溶融接続を行う。そして、実装基板側とＩＣチップとの接続信頼性の向上のために実装基板５aとＩＣチップ１aの間にアンダーフィル７を注入している。 FIG. 1 is a sectional view of the mounting substrate 5a on which the IC chip 1a is mounted. On the mounting substrate, a solder resist layer 6a is provided so that the solder bumps 2 are not fused to each other. An opening is provided in the solder resist layer 6a, and the wiring portion exposed immediately below the opening is used as the FC pad 4, and solder bumps 2 are laid on the pad to perform solder melting connection with the IC chip 1a. Then, in order to improve the connection reliability between the mounting substrate side and the IC chip, an underfill 7 is injected between the mounting substrate 5a and the IC chip 1a.
上記実装基板のソルダーレジスト６aは導体パターン上に印刷または塗布されているため、ソルダーレジスト層表面は導体パターンの有無や導体パターン厚さの影響を受けて凹凸面となっており、実装基板５aとＩＣチップ１aとの隙間は一定にならない。このため、アンダーフィル７の流れ込み速度に不均一が生じアンダーフィル７中にボイドが発生する原因となることがあり、当該ボイドがハンダバンプ部の接続信頼性や絶縁性の低下を招くという問題がある。 Since the solder resist 6a of the mounting substrate is printed or coated on the conductor pattern, the surface of the solder resist layer is uneven due to the presence or absence of the conductor pattern and the thickness of the conductor pattern. The gap with the IC chip 1a is not constant. For this reason, the flow rate of the underfill 7 becomes uneven, which may cause voids in the underfill 7, and there is a problem that the voids cause deterioration in the connection reliability and insulation of the solder bump portion. .
下記の特許文献１では、チップ実装部の開口部以外を被覆するソルダーレジストを厚くして平坦にすることで、実装基板とＩＣチップとの隙間を一定にし、アンダーフィル内にボイドが残存しないような実装基板の表面構造を開示している。 In Patent Document 1 below, the solder resist that covers other than the opening of the chip mounting portion is thickened and flattened, so that the gap between the mounting substrate and the IC chip is constant, and no voids remain in the underfill. A surface structure of a simple mounting board is disclosed.
特許文献２では、ソルダーレジストを塗布した後、それを硬化させる前に平坦化を行うことで実装基板とＩＣチップとの隙間を一定にするとともに、表面を粗化することで、アンダーフィル内にボイドが残存しないような実装基板の表面構造を開示している。 In Patent Document 2, after applying a solder resist, it is flattened before it is cured, so that the gap between the mounting substrate and the IC chip is made constant, and the surface is roughened, so that the underfill is formed. A surface structure of a mounting substrate in which no voids remain is disclosed.
このアンダーフィル７の隙間への注入は毛細管現象を利用しているが、接続バンプ２の狭ピッチ化により実装基板６aとＩＣチップ１ａとの隙間が狭くなってきていることや、バンプ配列の複雑化により、単にソルダーレジスト層６a表面を平坦にして実装基板５aとＩＣチップ１aとの隙間を一定にするだけの従来の注入方法では、ボイドの発生が完全に抑止できず信頼性の確保に限界があり、注入時間も長いといった問題がある。
そこで本発明は、実装基板とＩＣチップとの隙間に毛細管現象を利用してアンダーフィルを満遍なく確実に且つ短時間で導入するために、ソルダーレジストの表面が備えるべき構造を提供することを目的とした。
The injection of the underfill 7 into the gap uses a capillary phenomenon, but the gap between the mounting substrate 6a and the IC chip 1a is narrowed due to the narrow pitch of the connection bumps 2, and the bump arrangement is complicated. With the conventional injection method that simply flattens the surface of the solder resist layer 6a and keeps the gap between the mounting substrate 5a and the IC chip 1a constant, the generation of voids cannot be completely suppressed, and there is a limit to ensuring reliability. There is a problem that the injection time is long.
Accordingly, the present invention has an object to provide a structure that should be provided on the surface of the solder resist in order to introduce the underfill uniformly and in a short time in the gap between the mounting substrate and the IC chip by utilizing capillary action. did.
上記課題を達成するための、請求項1に記載の発明は、導体パターンと導体パターンを
被覆するソルダーレジストを備え、且つＩＣチップの接続用端子と導体パターンとがソルダーレジストに形成された開口部に敷設される半田を介して電気接続され、ソルダーレジストとＩＣチップ間の隙間で電気接続部以外がアンダーフィルによって充填される実装基板において、アンダーフィルによって被覆されるソルダーレジスト部分が接続用開口部の設置ピッチよりも狭い幅の溝を備えていることを特徴とする実装基板としたものである。
In order to achieve the above object, the invention according to claim 1 is provided with a conductor pattern and a solder resist that covers the conductor pattern, and an opening in which the IC chip connection terminal and the conductor pattern are formed in the solder resist. In the mounting substrate that is electrically connected through the solder laid on and filled with underfill in the gap between the solder resist and the IC chip except for the electrical connection portion, the solder resist portion covered with the underfill is the connection opening. The mounting board is characterized by having a groove having a narrower width than the installation pitch of the mounting board.
また、請求項２に記載の発明は、前記ソルダーレジストが備える溝が、各接続用開口部間にストライプ状に縫うように形成されていることを特徴とする請求項１に記載の実装基板としたものである。 The invention according to claim 2 is characterized in that the groove provided in the solder resist is formed so as to be sewn in a stripe shape between the connection openings. It is a thing.
また、請求項３に記載の発明は、前記ソルダーレジストが備える溝が、各接続用開口部を格子状に囲うように形成されていることを特徴とする請求項１に記載の実装基板としたものである。 According to a third aspect of the present invention, in the mounting substrate according to the first aspect, the groove provided in the solder resist is formed so as to surround each connection opening in a lattice shape. Is.
また、請求項４に記載の発明は、前記ソルダーレジストが備える溝が、各接続用開口部を多角形形状で囲うように形成されていることを特徴とする請求項１に記載の実装基板としたものである。 According to a fourth aspect of the present invention, in the mounting substrate according to the first aspect, the groove provided in the solder resist is formed so as to surround each connection opening with a polygonal shape. It is a thing.
また、請求項５に記載の発明は、前記ソルダーレジストが備える溝が、各接続用開口部を円形状または楕円形状で囲うように形成されていることを特徴とする請求項１に記載の実装基板としたものである。 According to a fifth aspect of the present invention, in the mounting according to the first aspect, the groove provided in the solder resist is formed so as to surround each connection opening with a circular shape or an elliptical shape. It is a substrate.
また、請求項６に記載の発明は、前記ソルダーレジストが備える溝が、各接続用開口部間を波状に縫うように形成されていることを特徴とする請求項１に記載の実装基板としたものである。 According to a sixth aspect of the present invention, there is provided the mounting substrate according to the first aspect, wherein the groove provided in the solder resist is formed so as to sew between the connection openings. Is.
また、請求項７に記載の発明は、前記ソルダーレジストが備える溝が、より幅の狭い複数の溝から構成されていることを特徴とする請求項２から請求項６のいずれか１項に記載の実装基板としたものである。 Further, in the invention according to claim 7, the groove provided in the solder resist is constituted by a plurality of grooves having a narrower width, according to any one of claims 2 to 6. This is a mounting board.
また、請求項８に記載の発明は、前記ソルダーレジストが備える溝が、Ｖ字型の断面形状を有することを特徴とする請求項２から請求項７のいずれか１項に記載の実装基板としたものである。 The invention according to claim 8 is characterized in that the groove provided in the solder resist has a V-shaped cross-sectional shape, and the mounting substrate according to any one of claims 2 to 7 It is a thing.
また、請求項９に記載の発明は、前記ソルダーレジストが備える溝が、Ｕ字型の断面形状を有することを特徴とする請求項２から請求項７のいずれか１項に記載の実装基板としたものである。 The invention according to claim 9 is characterized in that the groove provided in the solder resist has a U-shaped cross-sectional shape, and the mounting substrate according to any one of claims 2 to 7 It is a thing.
また、請求項１０に記載の発明は、前記ソルダーレジストが備える溝が、矩型型の断面形状を有することを特徴とする請求項２から請求項７のいずれか１項に記載の実装基板としたものである。 The invention according to claim 10 is characterized in that the groove provided in the solder resist has a rectangular cross-sectional shape, and the mounting substrate according to any one of claims 2 to 7 It is a thing.
また、請求項１１に記載の発明は、前記ソルダーレジストが備える溝が、請求項２から請求項１０のいずれか１項に記載の溝を組み合わせた形状で形成されていることを特徴とする請求項１に記載の実装基板としたものである。 The invention described in claim 11 is characterized in that the grooves provided in the solder resist are formed in a shape combining the grooves described in any one of claims 2 to 10. The mounting board according to Item 1 is obtained.
また、請求項１２に記載の発明は、前記ソルダーレジストが備える溝の深さは、ソルダーレジストの厚みより薄く導体パターン露出しない深さであることを特徴とする請求項８から請求項１１のいずれか１項に記載の実装基板としたものである。 The invention described in claim 12 is characterized in that the depth of the groove provided in the solder resist is smaller than the thickness of the solder resist and is a depth at which the conductor pattern is not exposed. Or a mounting substrate according to item 1.
本発明は、実装基板表面のソルダーレジスト層に溝を設けることにより、アンダーフィルが溝に沿って効率的に流れることにより、ＩＣチップと実装基板が狭い間隔を有していてもボイド残りが発生しにくく、実装信頼性を向上させることができる。また、短時間で効率的にアンダーフィルを充填できるため、生産性向上に資する。 In the present invention, by providing a groove in the solder resist layer on the surface of the mounting substrate, the underfill flows efficiently along the groove, so that a void residue is generated even if the IC chip and the mounting substrate have a narrow interval. Mounting reliability can be improved. In addition, the underfill can be efficiently filled in a short time, which contributes to an improvement in productivity.
また、本発明は、平坦化プレス工程にて平坦化と同時に溝を形成するため、工程数を増やすことなく実装基板を作製することができる。 Further, according to the present invention, since the groove is formed simultaneously with the flattening in the flattening press step, the mounting substrate can be manufactured without increasing the number of steps.
または、バンプ用開口部を形成するための露光現像工程にて同時に溝を形成するため、工程数を増やすことなく実装基板を作製することができる。 Alternatively, since the groove is formed at the same time in the exposure and development process for forming the bump opening, the mounting substrate can be manufactured without increasing the number of processes.
本発明になる実装基板は、該実装基板の表面を被覆しているソルダーレジスト層の開口部周辺にアンダーフィルの流動性を向上させるための溝を設けた実装基板である。
本発明の実装基板とその製造工程の一例を、図を参照して説明する。
The mounting substrate according to the present invention is a mounting substrate in which a groove for improving the fluidity of the underfill is provided around the opening of the solder resist layer covering the surface of the mounting substrate.
An example of the mounting substrate of the present invention and its manufacturing process will be described with reference to the drawings.
図１２に本発明が適用されるＩＣチップを搭載した実装基板の詳細な断面視の図を示したが、コアとなる基板１６には貫通孔１７が設けられ、該貫通孔１７の側壁面が銅めっき１８されることによりコア基板表裏の配線導体１８との導通がとられており、貫通孔自体は絶縁樹脂により埋設されている。コア基板の表裏両面に形成された導体層の上にレジストを塗布するなど定法のフォトリソ工法（現像・エッチング・レジスト剥離）を適用して銅層をエッチングして導体パターン１８（配線、導体層とも記す）を形成する。 FIG. 12 shows a detailed sectional view of a mounting substrate on which an IC chip to which the present invention is applied is mounted. A through-hole 17 is provided in the substrate 16 serving as a core, and the side wall surface of the through-hole 17 is The copper plating 18 provides electrical continuity with the wiring conductors 18 on the front and back of the core substrate, and the through holes themselves are embedded with insulating resin. Conductive pattern 18 (both wiring and conductor layers) is etched by applying a standard photolithographic method (development, etching, resist stripping) such as applying a resist on the conductor layers formed on both sides of the core substrate. Form).
次に、導体パターン１８が形成されたコア基板１６の両面にフィルム状絶縁樹脂２０をラミネートし、レーザー加工にて下層と導通させるためのビア孔１９と呼ばれる開口を設ける。フィルム状絶縁樹脂２０上に無電界銅めっきを施し、その後再びレジストを塗布し露光現像することでレジストに導体パターンに対応する開口部を形成する。次いで、電界銅めっきを行い開口部をめっき銅で埋設し、その後レジストを剥離してから無電界銅めっきをフラッシュエッチングにより除去して導体パターン２１を形成する。フィルム状絶縁樹脂ラミネートからフラッシュエッチまでの上記の工程を繰り返して多層構造の実装基板とする。 Next, a film-like insulating resin 20 is laminated on both surfaces of the core substrate 16 on which the conductor pattern 18 is formed, and openings called via holes 19 are provided for electrical connection with the lower layer by laser processing. Electroless copper plating is performed on the film-like insulating resin 20, and then a resist is applied again and exposed and developed to form an opening corresponding to the conductor pattern in the resist. Next, electrolytic copper plating is performed, the opening is filled with plated copper, the resist is then peeled off, and then the electroless copper plating is removed by flash etching to form a conductor pattern 21. The above steps from film-like insulating resin lamination to flash etching are repeated to obtain a multi-layer mounting board.
実装基板表面にソルダーレジスト６を塗布し、露光現像を行うことでソルダーレジストの所定の位置に開口部を形成して開口底部の導体を露出させ、FCパッド４を形成する。このFCパッド４に、ＩＣチップ１と接続するための半田バンプ２を形成する。 The solder resist 6 is applied to the surface of the mounting substrate, and exposure development is performed to form an opening at a predetermined position of the solder resist to expose the conductor at the bottom of the opening, thereby forming the FC pad 4. Solder bumps 2 for connection to the IC chip 1 are formed on the FC pads 4.
最後に、実装基板に、ＩＣチップ側の金属端子と実装基板の半田バンプとを位置合わせしてＩＣチップ１を搭載し、その後半田バンプを溶融してＩＣチップ１を実装基板にしっかりと実装する。その後、ＩＣチップ１ｃと実装基板１６のなす隙間で溶融半田以外の隙間にアンダーフィル７を注入し、アンダーフィル７を硬化させる。 Finally, the IC chip 1 is mounted on the mounting board by aligning the metal terminals on the IC chip side with the solder bumps of the mounting board, and then the solder bumps are melted to securely mount the IC chip 1 on the mounting board. . Thereafter, the underfill 7 is injected into a gap other than the molten solder through the gap formed by the IC chip 1c and the mounting substrate 16, and the underfill 7 is cured.
実装基板の最表面に形成されている導体パターン上にソルダーレジスト（ネガレジスト）を塗布する。塗布後、ベークにてソルダーレジストを半硬化させ、次いでソルダーレジスト表面をＰＥＴフィルムで被覆した。 A solder resist (negative resist) is applied on the conductor pattern formed on the outermost surface of the mounting substrate. After coating, the solder resist was semi-cured by baking, and then the surface of the solder resist was coated with a PET film.
ＰＥＴフィルムで被覆した基板を、図８に示すように、溝パターン１１を有するSUS板等の金型１０にて、ホットプレスを行うことで、ソルダーレジスト６oの表面を平坦化するとともに、アンダーフィル流動性を向上させるための溝を一括して形成する。このとき、上記の溝形状は金型の形状を変更することで所望の形状に形成することが可能である。 As shown in FIG. 8, the surface of the solder resist 6 o is flattened by performing hot pressing on the substrate coated with the PET film with a mold 10 such as a SUS plate having a groove pattern 11 as shown in FIG. Grooves for improving fluidity are collectively formed. At this time, the groove shape can be formed into a desired shape by changing the shape of the mold.
溝パターン形成後、図９に示すように、半田バンプを敷設するための開口部となる箇所以外のソルダーレジスト６pをフォトマスク１２を介して露光し、その後ＰＥＴフィルムを剥離する。ＰＥＴフィルム剥離後、現像するとソルダーレジスト６pが除去されてFCパッド開口部４が露出・形成され、図２から図７に示すような溝を開口部周辺のソルダーレジスト上に備える実装基板となる。 After the groove pattern is formed, as shown in FIG. 9, the solder resist 6p other than the portion that becomes the opening for laying the solder bump is exposed through the photomask 12, and then the PET film is peeled off. When the PET film is peeled and developed, the solder resist 6p is removed and the FC pad opening 4 is exposed and formed, and a mounting substrate having grooves as shown in FIGS. 2 to 7 on the solder resist around the opening is obtained.
そして、図１１に示すように、FCパッド４上に半田バンプ２を形成して、ＩＣチップ１bを実装した後、アンダーフィル７を注入すると、この溝８がアンダーフィル７をＩＣチップ１bとソルダーレジストとの隙間全体に効果的に誘導し、ボイドの発生率が抑えられ、且つ短時間で注入可能となった。アンダーフィル７はソルダーレジスト６rに形成された溝が延びる方向に進行するようにＩＣチップ近傍にセットしておくのが好ましい。
また、アンダーフィルはＩＣチップ底面と実装基板（ソルダーレジスト）とがなす隙間で接続用バンプを除いた部分を占めるが、ソルダーレジスト上に１ｍｍ程度裾を引くように滲み出る。したがって、図２から図７に示した種々の形状の溝も、この範囲内に形成するのが好ましい。
Then, as shown in FIG. 11, after forming the solder bump 2 on the FC pad 4 and mounting the IC chip 1b, when the underfill 7 is injected, the groove 8 forms the underfill 7 with the IC chip 1b and the solder. It was effectively guided to the entire gap with the resist, the generation rate of voids was suppressed, and injection was possible in a short time. The underfill 7 is preferably set in the vicinity of the IC chip so that the groove formed in the solder resist 6r proceeds in the extending direction.
The underfill occupies the portion excluding the connection bumps in the gap formed by the bottom surface of the IC chip and the mounting substrate (solder resist), but oozes out so as to have a hem of about 1 mm on the solder resist. Therefore, it is preferable to form grooves having various shapes shown in FIGS. 2 to 7 within this range.
実装基板の最表面に形成されている導体パターン上にソルダーレジスト（ポジレジスト）を塗布する。塗布後、ベークにてソルダーレジストを半硬化させ、次いでソルダーレジスト表面をＰＥＴフィルム（図示せず）で被覆した。ソルダーレジスト表面のホットプレスによる平坦化を行った後、図１０に示すように、溝形成用グレートーンパターンまたはハーフトーンパターン１４とＦＣパッド開口用透過パターン１２を有するフォトマスク１３を用いてソルダーレジスト６qを露光した。ＰＥＴフィルムを剥離した後、ソルダーレジスト６qの現像を行った。 A solder resist (positive resist) is applied on the conductor pattern formed on the outermost surface of the mounting substrate. After coating, the solder resist was semi-cured by baking, and then the surface of the solder resist was coated with a PET film (not shown). After the surface of the solder resist is flattened by hot pressing, as shown in FIG. 10, a solder resist is used using a photomask 13 having a groove-forming gray-tone pattern or half-tone pattern 14 and an FC pad opening transmission pattern 12. 6q was exposed. After peeling off the PET film, the solder resist 6q was developed.
透過した光で完全露光された部分は現像にてレジストが除去されて開口となりFCパッド開口部となる。同時に、グレートーンまたはハーフトーン部を半透過した光で露光された部分は、現像にて表面がハーフエッチングされ、溝が形成された。
このとき、上記の溝形状はグレートーンまたはハーフトーンの形状を変更することで所望の形状で所望の位置に形成することが可能である。これにより図２から図７に示すようなソルダーレジストに溝を備えた実装基板となる。
そして、図１１に示すように、FCパッド４上に半田バンプ２を形成して、ＩＣチップ１を実装した後、アンダーフィル７を溝のなす方向に注入すると、この溝９aがアンダーフィルをＩＣチップとソルダーレジストとの隙間全体に効果的に誘導し、ボイドの発生率が抑えられ、且つ短時間で注入可能となった。
In the part completely exposed to the transmitted light, the resist is removed by development to become an opening and an FC pad opening. At the same time, the surface of the portion exposed by the light that partially transmitted through the gray tone or half tone portion was half-etched by development to form a groove.
At this time, the groove shape can be formed at a desired position in a desired shape by changing the shape of gray tone or half tone. As a result, a mounting substrate having grooves in the solder resist as shown in FIGS.
Then, as shown in FIG. 11, after forming the solder bump 2 on the FC pad 4 and mounting the IC chip 1, when the underfill 7 is injected in the direction of the groove, the groove 9a Effectively guiding the entire gap between the chip and the solder resist, the void generation rate is suppressed, and the injection can be performed in a short time.
本発明は、実装基板表面のソルダーレジスト層に溝を設けることにより、アンダーフィルが短時間で充填でき、ボイド残りが発生しにくく接続信頼性の高い実装基板を提供できる。 According to the present invention, by providing a groove in the solder resist layer on the surface of the mounting substrate, it is possible to fill the underfill in a short time, and it is possible to provide a mounting substrate that is less likely to generate voids and has high connection reliability.
１a〜c、ＩＣチップ
２、半田バンプ
３、FCパッド（ＩＣチップ）
４、FCパッド（実装基板）
５a〜j、 実装基板
６a〜s、ソルダーレジスト層
７、アンダーフィル
８a〜g、溝
９a〜e、溝（断面形状）
１０、プレス金型
１１、金型に形成された溝形状
１２、１３、フォトマスク
１４、フォトマスク半透過部（グレートーンまたはハーフトーン部）
１５、導体パターン（導体）
１６、コア基板
１７、貫通孔（スルーホール）
１８、２１、導体パターン（銅めっき）
１９、ビア孔（開口）
２０、絶縁層（絶縁樹脂）
２２a〜e、ＩＣチップ実装エリア
X、アンダーフィル流動方向
1a to c, IC chip 2, solder bump 3, FC pad (IC chip)
4. FC pad (mounting board)
5a to j, mounting substrate 6a to s, solder resist layer 7, underfill 8a to g, groove 9a to e, groove (cross-sectional shape)
10. Press mold 11, groove shape 12, 13 formed in the mold, photomask 14, photomask semi-transmission part (gray tone or halftone part)
15. Conductor pattern (conductor)
16, core substrate 17, through hole (through hole)
18, 21, conductor pattern (copper plating)
19, via hole (opening)
20, Insulating layer (insulating resin)
22a-e, IC chip mounting area
X, direction of underfill flow
Claims (12)
ＩＣチップの接続用端子と導体パターンとがソルダーレジストに形成された開口部に敷設される半田を介して電気接続され、
ソルダーレジストとＩＣチップ間の隙間で電気接続部以外がアンダーフィルによって充填される実装基板において、
アンダーフィルによって被覆されるソルダーレジスト部分が接続用開口部の設置ピッチよりも狭い幅の溝を備えていることを特徴とする実装基板。 A solder resist covering the conductor pattern and the conductor pattern is provided, and the connection terminal of the IC chip and the conductor pattern are electrically connected via solder laid in the opening formed in the solder resist,
In the mounting board where the parts other than the electrical connection part are filled with underfill in the gap between the solder resist and the IC chip,
A mounting substrate, wherein a solder resist portion covered with an underfill is provided with a groove having a width narrower than an installation pitch of connection openings.
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| JP2010216734A JP2012074449A (en) | 2010-09-28 | 2010-09-28 | Mounting substrate |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2010216734A JP2012074449A (en) | 2010-09-28 | 2010-09-28 | Mounting substrate |
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| JP2010216734A Pending JP2012074449A (en) | 2010-09-28 | 2010-09-28 | Mounting substrate |
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