TWI566648B - Wiring board - Google Patents

Wiring board Download PDF

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Publication number
TWI566648B
TWI566648B TW102129226A TW102129226A TWI566648B TW I566648 B TWI566648 B TW I566648B TW 102129226 A TW102129226 A TW 102129226A TW 102129226 A TW102129226 A TW 102129226A TW I566648 B TWI566648 B TW I566648B
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Taiwan
Prior art keywords
wiring
connection terminal
width
wiring board
layer
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TW102129226A
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Chinese (zh)
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TW201419956A (en
Inventor
Tatsuya Ito
Makoto Nagai
Seiji Mori
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Ngk Spark Plug Co
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Publication of TWI566648B publication Critical patent/TWI566648B/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49822—Multilayer substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49838—Geometry or layout
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49866—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers characterised by the materials
    • H01L23/49894—Materials of the insulating layers or coatings
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/11—Printed elements for providing electric connections to or between printed circuits
    • H05K1/111—Pads for surface mounting, e.g. lay-out
    • H05K1/112—Pads for surface mounting, e.g. lay-out directly combined with via connections
    • H05K1/113—Via provided in pad; Pad over filled via
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
    • H05K3/4007—Surface contacts, e.g. bumps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16238—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bonding area protruding from the surface of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8112—Aligning
    • H01L2224/81121—Active alignment, i.e. by apparatus steering, e.g. optical alignment using marks or sensors
    • H01L2224/81132—Active alignment, i.e. by apparatus steering, e.g. optical alignment using marks or sensors using marks formed outside the semiconductor or solid-state body, i.e. "off-chip"
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8119—Arrangement of the bump connectors prior to mounting
    • H01L2224/81191—Arrangement of the bump connectors prior to mounting wherein the bump connectors are disposed only on the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8138—Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/81385—Shape, e.g. interlocking features
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/544—Marks applied to semiconductor devices or parts, e.g. registration marks, alignment structures, wafer maps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09209—Shape and layout details of conductors
    • H05K2201/095—Conductive through-holes or vias
    • H05K2201/096—Vertically aligned vias, holes or stacked vias
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09209—Shape and layout details of conductors
    • H05K2201/09654—Shape and layout details of conductors covering at least two types of conductors provided for in H05K2201/09218 - H05K2201/095
    • H05K2201/09727—Varying width along a single conductor; Conductors or pads having different widths
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/341—Surface mounted components
    • H05K3/3431—Leadless components
    • H05K3/3436—Leadless components having an array of bottom contacts, e.g. pad grid array or ball grid array components
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H05K3/4644—Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Geometry (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)

Description

配線基板 Wiring substrate

本發明係有關在主面形成有用以連接半導體晶片的連接端子之配線基板。 The present invention relates to a wiring substrate on which a connection terminal for connecting a semiconductor wafer is formed on a main surface.

一般係在配線基板的主面(表面)，形成用來與半導體晶片連接的連接端子(以下，稱為凸塊)。此凸塊係以被形成於尺寸(面積)比阻焊劑的開口面積還大且被稱為連接盤(land)的圓形或四角形銅箔上，且其上端位於比阻焊劑還高的位置的方式以焊料形成。 Generally, a connection terminal (hereinafter referred to as a bump) for connection to a semiconductor wafer is formed on a main surface (surface) of a wiring board. The bump is formed on a circular or quadrangular copper foil which is formed in a size (area) larger than the opening area of the solder resist and is called a land, and whose upper end is located higher than the solder resist. The way is formed by solder.

而近年來，隨著此凸塊的高密度化持續進展中，要求將所配置之凸塊的間隔(晶片)窄化。然而，為了如上所述般形成凸塊，必須將尺寸比凸塊還大一圈的連接盤設置於基底配線。因此，凸塊難以高密度化。 In recent years, as the density of the bumps continues to progress, it is required to narrow the interval (wafer) of the arranged bumps. However, in order to form the bump as described above, it is necessary to provide a land having a size larger than that of the bump to the substrate wiring. Therefore, it is difficult to increase the density of the bumps.

又，因必須避開連接盤來拉引配線，所以配線的布局(layout)會受到限制。因此，為了形成引繞不盡的配線，必須設置多餘的配線層。於是，提出在基底配線上直接形成凸塊而不設置連接盤，藉此獲得高密度配線之方法(參照專利文獻1)。 Moreover, since the wiring must be pulled away from the lands, the layout of the wiring is limited. Therefore, in order to form an inexhaustible wiring, an unnecessary wiring layer must be provided. Then, a method of forming a bump directly on the substrate wiring without providing a land to obtain a high-density wiring has been proposed (see Patent Document 1).

先前技術文獻 Prior technical literature 專利文獻 Patent literature

專利文獻1 日本特開2003-347334號公報 Patent Document 1 Japanese Patent Laid-Open Publication No. 2003-347334

然而，專利文獻1所提出的方法中，由於凸塊的直徑比配線寬度還小，所以會有凸塊與半導體晶片的連接可靠性降低之問題。又，當增大凸塊的直徑時，配線寬度會變粗，故會有配線布局的自由度受到限制之問題。 However, in the method proposed in Patent Document 1, since the diameter of the bump is smaller than the wiring width, there is a problem that the connection reliability between the bump and the semiconductor wafer is lowered. Further, when the diameter of the bump is increased, the wiring width becomes thick, and there is a problem that the degree of freedom in wiring layout is limited.

本發明係為因應上述情事而開發者，目的在於提供一種可提升配線布局的自由度之配線基板。 The present invention has been made in response to the above circumstances, and an object thereof is to provide a wiring board capable of improving the degree of freedom in wiring layout.

為了達成上述目的，本發明的配線基板，係具有分別積層有一層以上的絕緣層及導體層之積層體，該配線基板的特徵為，具備：形成於前述積層體上的複數個配線；及直接形成於前述複數個配線的至少一部分的配線上之柱狀連接端子；形成前述至少一部分的配線的前述連接端子之位置處的寬度，小於前述連接端子之前述寬度方向上的長度。 In order to achieve the above object, the wiring board of the present invention has a laminated body in which one or more insulating layers and a conductor layer are laminated, and the wiring board is characterized by comprising: a plurality of wirings formed on the laminated body; a columnar connection terminal formed on the wiring of at least a part of the plurality of wires; a width at a position of the connection terminal forming the at least one of the wires is smaller than a length in the width direction of the connection terminal.

根據本發明，由於係在配線上直接形成連接端子，故不需設置連接端子用的連接盤，配線布局的自由度得以提升。又，將供形成連接端子之位置處的配線的寬度，設成小於與配線的寬度方向一致的方向上之連接端子的長度，可抑制連接端子變小且連接可靠性降低。 According to the present invention, since the connection terminal is directly formed on the wiring, it is not necessary to provide the connection pad for the connection terminal, and the degree of freedom in wiring layout is improved. Moreover, the width of the wiring at the position where the connection terminal is formed is set to be smaller than the length of the connection terminal in the direction in which the width direction of the wiring is aligned, and it is possible to suppress the connection terminal from being small and the connection reliability from being lowered.

此外，本發明的一態樣中，其特徵為：形成連接端子之位置處的配線的寬度，為與配線的寬度方 向一致之方向上的連接端子的長度的0.5倍以上且小於1.0倍。藉由將供形成連接端子之位置處的配線的寬度，設成小於連接端子之在配線的寬度方向上的長度的0.5倍以上且小於1.0倍，可抑制連接端子變小且連接可靠性降低，且可抑制連接端子過大於配線寬度，致使連接端子傾斜或倒塌。 Further, in an aspect of the invention, the width of the wiring at the position where the connection terminal is formed is the width of the wiring. The length of the connection terminal in the direction of the coincidence is 0.5 times or more and less than 1.0 times. By setting the width of the wiring at the position where the connection terminal is formed to be less than 0.5 times and less than 1.0 times the length of the connection terminal in the width direction of the wiring, it is possible to suppress the connection terminal from being small and the connection reliability from being lowered. Moreover, it is possible to suppress the connection terminal from being excessively larger than the wiring width, causing the connection terminal to tilt or collapse.

又，本發明的其他態樣中，其特徵為：在供形成連接端子的位置，具有配線寬度變粗的第1粗寬度部。藉由在供形成連接端子的位置具有配線寬度變粗的第1粗寬度部，可將直徑大的連接端子直接形成於配線上。又，可提升連接端子與形成導體層的配線之連接可靠性。 Further, in another aspect of the invention, the first thick portion having a thick wiring width is provided at a position at which the connection terminal is formed. By having the first thick width portion in which the wiring width is thick at the position where the connection terminal is formed, the connection terminal having a large diameter can be directly formed on the wiring. Moreover, the connection reliability of the connection terminal and the wiring forming the conductor layer can be improved.

又，本發明的其他態樣中，其特徵為：在配線的延伸方向上之第1粗寬度部的長度，為連接端子在前述延伸方向上的長度的0.5倍以上且2.0倍以下。藉由將配線在延伸方向上之第1粗寬度部的長度，設成連接端子之與配線的延伸方向一致的方向上的長度的0.5倍以上且2.0倍以下，第1粗寬度部在延伸方向上的長度不會過長，可抑制配線布局的自由度降低。 Further, in another aspect of the invention, the length of the first thick portion in the extending direction of the wiring is 0.5 times or more and 2.0 times or less the length of the connection terminal in the extending direction. The length of the first thick portion in the extending direction of the wiring is set to be 0.5 times or more and 2.0 times or less the length of the connection terminal in the direction in which the wiring extends. The first thick width portion is in the extending direction. The length on the upper side is not too long, and the degree of freedom in wiring layout can be suppressed from being lowered.

又，本發明的其他態樣中，其特徵為：又具備覆蓋複數個配線，以使連接端子的至少一部分露出的阻焊劑層。藉由具備使連接端子的至少一部分露出的阻焊劑層，讓連接端子不易剝離。 Further, another aspect of the present invention is characterized in that it further includes a solder resist layer covering a plurality of wirings to expose at least a part of the connection terminals. The connection terminal is less likely to be peeled off by providing a solder resist layer that exposes at least a part of the connection terminal.

又，本發明的其他態樣中，其特徵為：連接端子的至少一部分係從阻焊劑層的表面突出。藉由使 連接端子從阻焊劑層的表面突出，可容易與相對側端子連接。 Further, in another aspect of the invention, at least a part of the connection terminal protrudes from a surface of the solder resist layer. By making The connection terminal protrudes from the surface of the solder resist layer and can be easily connected to the opposite side terminal.

又，本發明的其他態樣中，其特徵為：僅在設定於積層體上的矩形零件搭載區域的外周部配置複數個連接端子作為信號用連接端子，且在零件搭載區域的中央部，配列複數個電源及接地連接盤用連接墊。 Further, in another aspect of the present invention, a plurality of connection terminals are disposed as signal connection terminals only in the outer peripheral portion of the rectangular component mounting region set on the laminated body, and are arranged in the central portion of the component mounting region. A plurality of connection pads for power and ground connection pads.

由於僅在零件搭載區域的外周部配列複數個連接端子，故藉由作為配線長度變長且配線的引繞難以進行的信號用連接端子使用，配線的引繞可容易進行，可提升配線布局的自由度。又，藉由在零件搭載區域的中央部，配列複數個電源及接地連接盤用連接墊，可縮短電源及接地連接盤用的配線長度。 Since a plurality of connection terminals are arranged only in the outer peripheral portion of the component mounting region, the wiring can be easily used as a signal connection terminal in which the wiring length is long and wiring is difficult to be performed, and the wiring layout can be improved. Degree of freedom. Further, by arranging a plurality of connection pads for the power supply and the ground connection pad in the center portion of the component mounting region, the wiring length for the power supply and the ground connection pad can be shortened.

又，本發明的其他態樣中，其特徵為：前述積層體係交替積層複數個前述導體層與複數個前述絕緣層而成，並且具備通路導體，該通路導體係直接形成於形成前述導體層的複數個配線上且貫通前述絕緣層而將前述導體層間連接；形成前述導體層的配線之供形成前述通路導體的位置處的寬度，為前述通路導體之前述寬度方向上的長度的0.5倍以上且小於1.0倍。 Further, in another aspect of the invention, the laminated system is formed by alternately stacking a plurality of the plurality of conductor layers and a plurality of the insulating layers, and further comprising a via conductor formed directly on the conductor layer. The conductor layers are connected to each other through a plurality of wires, and the width of the wiring forming the conductor layer at a position where the via conductor is formed is 0.5 times or more the length of the via conductor in the width direction. Less than 1.0 times.

藉由將形成導體層的配線之供形成通路導體的位置處的寬度，設成通路導體之寬度方向上的長度的0.5倍以上且小於1.0倍，可將通路導體間窄晶片化，可提升配線布局的自由度。又，可抑制通路導體與形成導體層的配線之連接可靠性降低。 By making the width of the wiring forming the conductor layer at the position where the via conductor is formed to be 0.5 times or more and less than 1.0 times the length in the width direction of the via conductor, the via conductor can be narrowly padded, and the wiring can be improved. The freedom of layout. Further, it is possible to suppress a decrease in connection reliability between the via conductor and the wiring forming the conductor layer.

又，本發明的其他態樣中，其特徵為：形成前述導體層的配線，係在供形成前述通路導體的位置處，具有配線寬度較粗的第2粗寬度部。藉由在供形成通路導體的位置處具有配線寬度變粗的第2粗寬度部，可將直徑較大的通路導體直接形成於配線上。又，通路導體與形成導體層的配線之連接可靠性得以提升。 Further, in another aspect of the invention, the wiring for forming the conductor layer has a second thick width portion having a thick wiring width at a position where the via conductor is formed. By having the second thick portion having a thick wiring width at a position where the via conductor is formed, a via conductor having a large diameter can be directly formed on the wiring. Moreover, the connection reliability of the via conductor and the wiring forming the conductor layer is improved.

再者，本發明的其他態樣中，其特徵為：形成前述導體層之前述配線的第2粗寬度部在延伸方向上的長度，為前述通路導體在前述延伸方向上的長度的0.5倍以上且2.0倍以下。藉由將形成導體層之配線的第2粗寬度部在延伸方向上的長度，設成通路導體在延伸方向上的長度的0.5倍以上且2.0倍以下，而使第2粗寬度部在延伸方向的長度不會過長，可抑制配線布局的自由度降低。 Furthermore, in another aspect of the invention, the length of the second thick portion of the wiring forming the conductor layer in the extending direction is 0.5 times or more the length of the via conductor in the extending direction. And 2.0 times or less. The length of the second thick portion of the wiring forming the conductor layer in the extending direction is set to be 0.5 times or more and 2.0 times or less the length of the via conductor in the extending direction, and the second thick width portion is extended. The length is not too long, and the degree of freedom in wiring layout can be suppressed from being lowered.

如以上說明，根據本發明，可提供一種能提升配線布局的自由度之配線基板。 As described above, according to the present invention, it is possible to provide a wiring board capable of improving the degree of freedom in wiring layout.

AM‧‧‧對準遮罩 AM‧‧ Alignment mask

B‧‧‧焊料球 B‧‧‧ solder ball

F‧‧‧主面 F‧‧‧Main face

L‧‧‧階差 L‧‧‧ step

L1、L2、L3‧‧‧金屬配線 L1, L2, L3‧‧‧ metal wiring

L11、L12、L13‧‧‧金屬配線 L11, L12, L13‧‧‧ metal wiring

L2a、L3a、L13a‧‧‧粗寬度部 L2a, L3a, L13a‧‧‧ thick width

M‧‧‧金屬鍍敷層 M‧‧‧metal plating

MR1~MR5、MR11~MR15‧‧‧樹脂遮罩 MR1~MR5, MR11~MR15‧‧‧ resin mask

P1、P2‧‧‧墊 P1, P2‧‧‧ pads

T1、T11‧‧‧連接端子 T1, T11‧‧‧ connection terminal

100、100A、200~400‧‧‧配線基板 100, 100A, 200~400‧‧‧ wiring board

2‧‧‧芯基板 2‧‧‧ core substrate

3‧‧‧增層 3‧‧‧Additional

4‧‧‧充填構件 4‧‧‧Filling components

5‧‧‧阻焊劑層 5‧‧‧Solder layer

5a、5b‧‧‧開口 5a, 5b‧‧‧ openings

13‧‧‧增層 13‧‧‧Additional

14‧‧‧阻焊劑層 14‧‧‧Solder layer

14a‧‧‧開口 14a‧‧‧ Opening

21、22‧‧‧芯導體層 21, 22‧‧‧ core conductor layer

23‧‧‧貫穿孔 23‧‧‧through holes

24‧‧‧貫穿孔導體 24‧‧‧through hole conductor

25‧‧‧樹脂製埋孔材 25‧‧‧Resin buried hole

31‧‧‧樹脂絕緣層 31‧‧‧Resin insulation

31、131‧‧‧樹脂絕緣層 31, 131‧‧‧ resin insulation

32、132‧‧‧導體層 32, 132‧‧‧ conductor layer

34、134‧‧‧導體層 34, 134‧‧‧ conductor layer

36、136‧‧‧導體層 36, 136‧‧‧ conductor layer

37、137‧‧‧樹脂絕緣層 37, 137‧‧‧ resin insulation

41‧‧‧蓋鍍敷層 41‧‧‧ cover plating

42、43、142、143‧‧‧充填通路 42, 43, 142, 143‧‧ fill channels

圖1為第1實施形態之配線基板的俯視圖(表面側)。 Fig. 1 is a plan view (surface side) of a wiring board of the first embodiment.

圖2為第1實施形態之配線基板的部分剖面圖。 Fig. 2 is a partial cross-sectional view showing the wiring board of the first embodiment.

圖3為第1實施形態之配線基板的表面側的連接端子之構成圖。 3 is a configuration diagram of a connection terminal on the front surface side of the wiring board of the first embodiment.

圖4為第1實施形態之配線基板的表面側之連接端子與配線的俯視圖。 4 is a plan view showing a connection terminal and a wiring on the front surface side of the wiring board of the first embodiment.

圖5為第1實施形態之配線基板的製造步驟圖(芯基板步驟)。 Fig. 5 is a view showing a manufacturing step of the wiring board of the first embodiment (core substrate step).

圖6為第1實施形態之配線基板的製造步驟圖(增設步驟)。 Fig. 6 is a manufacturing step diagram (additional step) of the wiring board of the first embodiment.

圖7為第1實施形態之配線基板的製造步驟圖(凸鍍敷層形成步驟)。 Fig. 7 is a view showing a manufacturing step of the wiring board of the first embodiment (protrusion plating layer forming step).

圖8為第1實施形態之配線基板的製造步驟圖(充填步驟)。 Fig. 8 is a manufacturing step diagram (filling step) of the wiring board of the first embodiment.

圖9為第4充填方法的說明圖。 Fig. 9 is an explanatory diagram of a fourth filling method.

圖10為第1實施形態之配線基板的製造步驟圖(阻焊劑層步驟)。 Fig. 10 is a manufacturing step diagram (step of a solder resist layer) of the wiring board of the first embodiment.

圖11為第1實施形態之配線基板的製造步驟圖(鍍敷步驟)。 Fig. 11 is a manufacturing step diagram (plating step) of the wiring board of the first embodiment.

圖12為第1實施形態的變形例之配線基板的部分剖面圖。 Fig. 12 is a partial cross-sectional view showing a wiring board according to a modification of the first embodiment.

圖13為第1實施形態的變形例之配線基板的配線與通路導體的俯視圖。 Fig. 13 is a plan view showing a wiring and a via conductor of a wiring board according to a modification of the first embodiment.

圖14為第1實施形態的變形例之配線基板的配線與通路導體的放大俯視圖。 FIG. 14 is an enlarged plan view showing a wiring and a via conductor of a wiring board according to a modification of the first embodiment.

圖15為第1實施形態的變形例之配線基板的製造步驟圖(增設步驟)。 Fig. 15 is a manufacturing step diagram (additional step) of the wiring board according to a modification of the first embodiment.

圖16為第1實施形態的變形例之配線基板的製造步驟圖(增設步驟)。 Fig. 16 is a manufacturing step diagram (additional step) of the wiring board according to a modification of the first embodiment.

圖17為第2實施形態之配線基板的俯視圖(表面側)。 Fig. 17 is a plan view (surface side) of the wiring board of the second embodiment.

圖18為第3實施形態之配線基板的俯視圖(表面側)。 Fig. 18 is a plan view (surface side) of the wiring board of the third embodiment.

圖19為第3實施形態之配線基板的部分剖面圖。 Fig. 19 is a partial cross-sectional view showing a wiring board of a third embodiment.

圖20為第4實施形態之配線基板的俯視圖(表面側)。 Fig. 20 is a plan view (surface side) of the wiring board of the fourth embodiment.

圖21為第5實施形態之配線基板的部分放大圖。 Fig. 21 is a partially enlarged view of the wiring board of the fifth embodiment.

圖22為顯示其他實施形態之配線基板的充填構件的上面形狀之圖。 Fig. 22 is a view showing the shape of the upper surface of the filling member of the wiring board of the other embodiment.

[用以實施發明的形態] [Formation for carrying out the invention]

以下，一面參照圖式，一面說明詳細本發明的實施形態。此外，以下的說明中，雖以芯基板上形成有增層的配線基板為例來說明本發明的實施形態，惟只要是形成有複數個連接端子的配線基板即可，例如，亦可為不具有芯基板的配線基板。 Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. In the following description, an embodiment of the present invention will be described by taking a wiring board having a build-up layer formed on a core substrate as an example. However, the wiring board may have a plurality of connection terminals. For example, A wiring substrate having a core substrate.

(第1實施形態) (First embodiment)

圖1為第1實施形態之配線基板100的俯視圖(表面側)。圖2為圖1的線段I-I之配線基板100的部分剖面圖。圖3為形成於配線基板100的表面側之連接端子T1的構成圖。圖3(a)為連接端子T1的俯視圖。圖3(b)為圖3(a)之線段II-II的剖面圖。此外，以下的說明中，將供連接半導體晶片(零件)的那側設為表面側，將供連接母板、插座(socket)等(以下，稱為母板等)的那側設為背面側。 FIG. 1 is a plan view (surface side) of the wiring board 100 of the first embodiment. FIG. 2 is a partial cross-sectional view of the wiring substrate 100 of the line segment I-I of FIG. 1. FIG. 3 is a configuration diagram of the connection terminal T1 formed on the front surface side of the wiring substrate 100. Fig. 3(a) is a plan view of the connection terminal T1. Fig. 3(b) is a cross-sectional view taken along line II-II of Fig. 3(a). In the following description, the side to which the semiconductor wafer (component) is to be connected is referred to as the front side, and the side to which the mother board, the socket or the like (hereinafter referred to as a mother board or the like) is to be connected is referred to as the back side. .

(配線基板100的構成) (Configuration of Wiring Substrate 100)

圖1~3所示的配線基板100具備：芯基板2；增層3(表面側)，係形成有複數個與半導體晶片(未圖示) 連接的連接端子T1，且積層於芯基板2的表面側；充填構件4，係積層於增層3，且充填於複數個連接端子T1間；阻焊劑層5，係積層於充填構件4，且形成有使連接端子T1露出的開口5a；增層13(背面側)，係形成有複數個與母板等(未圖示)連接的連接端子T11，且積層於芯基板2的背面側；及阻焊劑層14，係積層於增層13，且形成有使連接端子T11的至少一部分露出的開口14a。 The wiring board 100 shown in FIGS. 1 to 3 includes a core substrate 2 and a build-up layer 3 (surface side) in which a plurality of semiconductor wafers (not shown) are formed. The connection terminal T1 is connected to the surface side of the core substrate 2; the filling member 4 is laminated on the build-up layer 3 and filled between the plurality of connection terminals T1; the solder resist layer 5 is laminated on the filling member 4, and An opening 5a for exposing the connection terminal T1 is formed; and the build-up layer 13 (back side) is formed with a plurality of connection terminals T11 connected to a mother board or the like (not shown), and laminated on the back side of the core substrate 2; The solder resist layer 14 is laminated on the buildup layer 13 and has an opening 14a through which at least a part of the connection terminal T11 is exposed.

芯基板2係由耐熱性樹脂板(例如雙馬來醯亞胺基-三(triazine)樹脂板)、或纖維強化樹脂板(例如玻璃纖維強化環氧樹脂)等所構成的板狀樹脂製基板。在芯基板2的表面及背面，分別形成有構成金屬配線L1、L11的芯導體層21、22。又，在芯基板2形成有藉由鑽孔機等所穿設的貫穿孔23，且在該貫穿孔23的內壁面形成有使芯導體層21、22相互導通的貫穿孔導體24。再者，貫穿孔23係由環氧樹脂等的樹脂製埋孔材25所充填。 The core substrate 2 is made of a heat resistant resin sheet (for example, bismaleimide-three A plate-shaped resin substrate made of a (triazine) resin sheet or a fiber-reinforced resin sheet (for example, a glass fiber reinforced epoxy resin). Core conductor layers 21 and 22 constituting the metal wirings L1 and L11 are formed on the front surface and the back surface of the core substrate 2, respectively. Further, the core substrate 2 is formed with a through hole 23 that is bored by a drill or the like, and a through hole conductor 24 that electrically connects the core conductor layers 21 and 22 to each other is formed on the inner wall surface of the through hole 23. Further, the through hole 23 is filled with a resin-made buried hole material 25 such as an epoxy resin.

(表面側的構成) (Structure on the surface side)

配線基板100的表面側形成有與芯導體層21電性連接的蓋鍍敷層41，此蓋鍍敷層41與構成金屬配線L2的導體層32，係藉由充填通路42電性連接。充填通路42具有：通路孔42a；和藉由鍍敷充填於充填通路孔42a內側的通路導體42b。 A cap plating layer 41 electrically connected to the core conductor layer 21 is formed on the surface side of the wiring substrate 100. The cap plating layer 41 and the conductor layer 32 constituting the metal wiring L2 are electrically connected by a filling via 42. The filling passage 42 has a via hole 42a and a via conductor 42b which is filled and filled inside the filling via hole 42a by plating.

形成於配線基板100之導體層32上的連接端子T1，係與半導體晶片連接的連接端子。半導體晶片係藉由與此連接端子T1電性連接而被安裝於配線基板100。此實施形態中，連接端子T1係沿著半導體晶片的安 裝區域(零件搭載區域)的整體配置成大致等間隔。連接端子T1由俯視觀之，係形成圓形的柱狀形狀，其係以上部從充填構件4的表面突出的狀態直接形成於導體層32上。因為是將連接端子T1直接形成於導體層32上，所以無需設置供連接端子T1用的連接盤，配線布局的自由度得以提升。 The connection terminal T1 formed on the conductor layer 32 of the wiring substrate 100 is a connection terminal to which a semiconductor wafer is connected. The semiconductor wafer is mounted on the wiring substrate 100 by being electrically connected to the connection terminal T1. In this embodiment, the connection terminal T1 is along the semiconductor wafer. The entire mounting area (part mounting area) is arranged at substantially equal intervals. The connection terminal T1 is formed in a plan view and has a circular columnar shape, and is formed directly on the conductor layer 32 in a state where the upper portion protrudes from the surface of the filling member 4. Since the connection terminal T1 is directly formed on the conductor layer 32, it is not necessary to provide a land for the connection terminal T1, and the degree of freedom in wiring layout is improved.

圖4係連接端子T1與金屬配線L2的俯視圖。圖4(a)係在供形成連接端子T1的位置處不具有配線寬度較粗的粗寬度部L2a之金屬配線L2的俯視圖。圖4(b)係在供形成連接端子T1的位置處具有配線寬度較粗的粗寬度部(第1粗寬度部)L2a之金屬配線L2的俯視圖。 4 is a plan view of the connection terminal T1 and the metal wiring L2. 4(a) is a plan view of the metal wiring L2 having no thick width portion L2a having a thick wiring width at a position where the connection terminal T1 is formed. 4(b) is a plan view of the metal wiring L2 having a thick width portion (first thick width portion) L2a having a thick wiring width at a position where the connection terminal T1 is formed.

如圖4(a)所示，金屬配線L2上之供形成連接端子T1之位置處的寬度W，宜小於連接端子T1之與金屬配線L2的寬度方向一致之方向上的長度(直徑)W1。藉由將金屬配線L2之供形成連接端子T1之位置處的寬度W，設成小於連接端子T1之與金屬配線L2的寬度方向一致之方向的長度(直徑)W1，連接端子T1的寬度不會過細，可抑制連接端子T1與半導體晶片的連接可靠性降低之情形。 As shown in FIG. 4(a), the width W at the position where the connection terminal T1 is formed on the metal wiring L2 is preferably smaller than the length (diameter) W1 of the connection terminal T1 in the direction in which the width direction of the metal wiring L2 coincides. The width W of the metal wiring L2 at the position where the connection terminal T1 is formed is set to be smaller than the length (diameter) W1 of the connection terminal T1 in the direction in which the width direction of the metal wiring L2 coincides, and the width of the connection terminal T1 is not If it is too fine, the connection reliability of the connection terminal T1 and the semiconductor wafer can be suppressed from being lowered.

又，金屬配線L2上之供形成連接端子T1之位置處的寬度W，宜為連接端子T1之與金屬配線L2的寬度方向一致之方向上的長度W1的0.5倍以上且小於1.0倍。藉由將金屬配線L2上之供形成連接端子T1之位置處的寬度W，設成連接端子T1之在配線的寬度方向上的長度W1的0.5倍以上且小於1.0倍，可抑制連接端子T1變細 且與半導體晶片的連接可靠性降低，且可抑制連接端子T1之寬度方向上的長度W1太過長於配線寬度W，致使形成於金屬配線L2上的連接端子T1傾斜或倒塌。 Further, the width W at the position where the connection terminal T1 is formed on the metal wiring L2 is preferably 0.5 times or more and less than 1.0 times the length W1 of the connection terminal T1 in the direction in which the width direction of the metal wiring L2 coincides. By setting the width W at the position where the connection terminal T1 is formed on the metal wiring L2 to be 0.5 times or more and less than 1.0 times the length W1 of the connection terminal T1 in the width direction of the wiring, the connection terminal T1 can be suppressed from being changed. fine Further, the connection reliability with the semiconductor wafer is lowered, and the length W1 in the width direction of the connection terminal T1 can be suppressed from being too long longer than the wiring width W, so that the connection terminal T1 formed on the metal wiring L2 is inclined or collapsed.

又，當在金屬配線L2較細，且在金屬配線L2上直接形成連接端子T1的情況，有致使連接端子T1發生傾斜、倒塌之虞時，如圖4(b)所示，可在供形成連接端子T1的位置，設置配線寬度W變粗的粗寬度部L2a。藉由在供形成連接端子T1的位置，具有配線寬度較粗的粗寬度部L2a，即便是金屬配線L2的線寬較窄的情況，或連接端子T1在寬度方向上的長度W1較長的情況、即連接端子T1的直徑較大的情況，也可在金屬配線L2上直接形成連接端子T1。 Further, when the metal wiring L2 is thin and the connection terminal T1 is directly formed on the metal wiring L2, when the connection terminal T1 is tilted or collapsed, as shown in FIG. 4(b), it can be formed. The position of the connection terminal T1 is set to the thick width portion L2a in which the wiring width W is thick. When the thick width portion L2a having a thick wiring width is provided at a position where the connection terminal T1 is formed, even when the line width of the metal wiring L2 is narrow, or the length W1 of the connection terminal T1 in the width direction is long In other words, when the diameter of the connection terminal T1 is large, the connection terminal T1 may be directly formed on the metal wiring L2.

又，金屬配線L2的粗寬度部L2a在延伸方向上的長度W2，宜為連接端子T1之與金屬配線L2的延伸方向一致的方向上的長度W1的0.5倍以上且2.0倍以下。藉由將金屬配線L2在延伸方向上之粗寬度部L2a的長度W2，設成金屬配線L2之延伸方向的連接端子T1的長度W1的0.5倍以上且2.0倍以下，可抑制粗寬度部L2a在延伸方向上變長、配線布局的自由度降低的情況。 Moreover, the length W2 of the thick portion L2a of the metal wiring L2 in the extending direction is preferably 0.5 times or more and 2.0 times or less the length W1 of the connecting terminal T1 in the direction in which the metal wiring L2 extends. By setting the length W2 of the thick portion L2a of the metal wiring L2 in the extending direction to 0.5 times or more and 2.0 times or less the length W1 of the connection terminal T1 in the extending direction of the metal wiring L2, it is possible to suppress the thick portion L2a from being The length in the extension direction is increased, and the degree of freedom in wiring layout is lowered.

又，關於設有粗寬度部L2a的金屬配線L2，金屬配線L2之供形成連接端子T1的位置處的寬度W，較佳為小於連接端子T1之與金屬配線L2的寬度方向一致之方向上的長度(徑)L1，更佳為連接端子T1之與金屬配線L2的寬度方向一致之方向上的長度的0.5倍以上且小於1.0倍。 Further, regarding the metal wiring L2 having the thick width portion L2a, the width W at the position where the metal wiring L2 is formed to form the connection terminal T1 is preferably smaller than the direction in which the connection terminal T1 coincides with the width direction of the metal wiring L2. The length (diameter) L1 is more preferably 0.5 times or more and less than 1.0 times the length of the connection terminal T1 in the direction in which the width direction of the metal wiring L2 coincides.

各連接端子T1係於表面施以粗化，以提升與充填構件4的黏著性。連接端子T1的表面，可藉由例如用MEC Etch Bond(日本MEC股份有限公司)等的蝕刻液進行處理來進行粗化。 Each of the connection terminals T1 is roughened on the surface to improve the adhesion to the filling member 4. The surface of the connection terminal T1 can be roughened by, for example, treatment with an etching solution such as MEC Etch Bond (Japan MEC Co., Ltd.).

此外，於沒有將各連接端子T1的表面施以粗化的情況下，亦可藉由將Sn(錫)、Ti(鈦)、Cr(鉻)、Ni(鎳)的任一金屬元素塗佈於各連接端子T1的表面以形成金屬層後，在該金屬層上實施耦合劑處理，而使其與充填構件4的黏著性提升。 Further, in the case where the surface of each connection terminal T1 is not roughened, any metal element of Sn (tin), Ti (titanium), Cr (chromium), or Ni (nickel) may be coated. After forming a metal layer on the surface of each connection terminal T1, a couplant treatment is performed on the metal layer to improve the adhesion to the filling member 4.

再者，如圖3(b)所示，各連接端子T1係在第1主面F的外周形成階差L，含此階差L的連接端子T1的露出面係被金屬鍍敷層M所覆蓋。將半導體晶片安裝於配線基板100之際，係藉由將塗佈於半導體晶片之連接端子的焊料進行迴焊(reflow)，而使半導體晶片的連接端子和連接端子T1電性連接。此外，金屬鍍敷層M係由從例如Ni層、Sn層、Ag層、Pd層、Au層等的金屬層選擇的單一層或複數個層(例如Ni層/Au層、Ni層/Pd層/Au層)所構成。 Further, as shown in FIG. 3(b), each of the connection terminals T1 forms a step L on the outer circumference of the first main surface F, and the exposed surface of the connection terminal T1 including the step L is formed by the metal plating layer M. cover. When the semiconductor wafer is mounted on the wiring substrate 100, the connection between the connection terminal of the semiconductor wafer and the connection terminal T1 is electrically connected by reflowing the solder applied to the connection terminal of the semiconductor wafer. Further, the metal plating layer M is a single layer or a plurality of layers selected from a metal layer such as a Ni layer, a Sn layer, an Ag layer, a Pd layer, an Au layer, or the like (for example, a Ni layer/Au layer, a Ni layer/Pd layer). /Au layer).

又，作為取代金屬鍍敷層M，亦可施加防鏽用OSP(Organic Solder ability Preservative：有機可焊性保護劑)處理。又，亦可在含階差L之連接端子T1的露出面塗佈焊料，再者，亦可在以金屬鍍敷層M覆蓋含階差L之連接端子T1的露出面之後，於該金屬鍍敷層M塗佈焊料。此外，關於在連接端子T1的露出面塗佈焊料的方法將於後敘述。 Further, as the substitute metal plating layer M, an OSP (Organic Solder Ability Preservative) treatment for rust prevention may be applied. Further, the solder may be applied to the exposed surface of the connection terminal T1 including the step difference L, or the metal plating may be applied after the exposed surface of the connection terminal T1 including the step L is covered with the metal plating layer M. The coating M is coated with solder. Further, a method of applying solder to the exposed surface of the connection terminal T1 will be described later.

充填構件4係在與增層3的表層所形成之各連接端子T1的側面密接的狀態下，充填於連接端子T1間。又，充填構件4的厚度D2係薄於連接端子T1的厚度(高度)D1。此外，關於充填構件4的充填方法，將於後敘述。 The filling member 4 is filled between the connection terminals T1 in a state in which it is in close contact with the side surface of each of the connection terminals T1 formed on the surface layer of the buildup layer 3. Moreover, the thickness D2 of the filling member 4 is thinner than the thickness (height) D1 of the connection terminal T1. In addition, the filling method of the filling member 4 will be described later.

阻焊劑層5係覆蓋與連接端子T1連接之配線圖案的表面側，並具有：開口5a，使以大致等間隔配置於半導體晶片的安裝區域之連接端子T1露出；及開口5b，使薄片電容器(chip capacitor)安裝用墊P1露出。阻焊劑層5的開口5a係成為在同一開口內配置複數個連接端子T1之NSMD(non solder mask defined：非焊罩定義)形狀。又，阻焊劑層5上形成有對準遮罩AM。此外，對準遮罩AM非為必要者。 The solder resist layer 5 covers the surface side of the wiring pattern connected to the connection terminal T1, and has an opening 5a for exposing the connection terminals T1 disposed at substantially equal intervals in the mounting region of the semiconductor wafer, and an opening 5b for the sheet capacitor ( The chip capacitor mounting pad P1 is exposed. The opening 5a of the solder resist layer 5 is an NSMD (non solder mask defined) shape in which a plurality of connection terminals T1 are disposed in the same opening. Further, an alignment mask AM is formed on the solder resist layer 5. In addition, alignment of the mask AM is not necessary.

(背面側的構成) (constitution on the back side)

配線基板100的背面側形成有與芯導體層22電性連接的蓋鍍敷層141，此蓋鍍敷層141和導體層132係藉由充填通路142電性連接。充填通路142具有：通路孔142a；和藉鍍敷充填於通路孔142a內側的通路導體142b。又，導體層132具有未隔著通路而與母板等(未圖示)連接的連接端子T11。 A cap plating layer 141 electrically connected to the core conductor layer 22 is formed on the back surface side of the wiring substrate 100, and the cap plating layer 141 and the conductor layer 132 are electrically connected by a filling via 142. The filling passage 142 has a via hole 142a and a via conductor 142b which is plated and filled inside the via hole 142a. Further, the conductor layer 132 has a connection terminal T11 that is connected to a mother board or the like (not shown) without a via.

連接端子T11被利用作為用於將配線基板100連接於母板等的背面連接盤(PGA墊、BGA墊)，形成於除了配線基板100的大致中心部以外的外周區域，且以圍繞前述大致中央部的方式配列成矩形狀。又，連接端子T11的表面的至少一部分係由金屬鍍敷層M所覆蓋。 The connection terminal T11 is used as a back surface connection pad (PGA pad, BGA pad) for connecting the wiring board 100 to a mother board or the like, and is formed in an outer peripheral area other than the substantially central portion of the wiring board 100, and surrounds the substantially central portion. The way of the parts is arranged in a rectangular shape. Further, at least a part of the surface of the connection terminal T11 is covered by the metal plating layer M.

阻焊劑層14係以薄膜狀阻焊劑積層於增層13的表面上的方式形成。在阻焊劑層14，形成有使各連接端子T11表面的一部分露出之開口14a。因此，各連接端子T11係成為其表面的一部分透過開口14a而從阻焊劑層14露出的狀態。亦即，阻焊劑層14的開口14a係成為露出有各連接端子T11表面的一部分之SMD(solder mask defined：焊罩定義)形狀。此外，與阻焊劑層5的開口Sa不同之處在於，阻焊劑層14的開口14a係依每個連接端子T11形成。 The solder resist layer 14 is formed in such a manner that a film-like solder resist is laminated on the surface of the buildup layer 13. In the solder resist layer 14, an opening 14a for exposing a part of the surface of each connection terminal T11 is formed. Therefore, each of the connection terminals T11 is in a state in which a part of the surface thereof is exposed from the solder resist layer 14 through the opening 14a. That is, the opening 14a of the solder resist layer 14 is in the shape of an SMD (solder mask definition) in which a part of the surface of each of the connection terminals T11 is exposed. Further, it is different from the opening Sa of the solder resist layer 5 in that the opening 14a of the solder resist layer 14 is formed by each connection terminal T11.

由例如Sn-Ag、Sn-Cu、Sn-Ag-Cu、Sn-Sb等實質上不含Pb的焊料所構成焊料球B，是以隔著金屬鍍敷層M與連接端子T11電性連接的方式形成於開口14a內。此外，將配線基板100安裝於母板等之際，是藉由對配線基板100的焊料球B施以迴焊，而將連接端子T11電性連接至母板等的連接端子。 The solder ball B composed of a solder containing substantially no Pb such as Sn—Ag, Sn—Cu, Sn—Ag—Cu, and Sn—Sb is electrically connected to the connection terminal T11 via the metal plating layer M. The manner is formed in the opening 14a. In addition, when the wiring board 100 is mounted on a mother board or the like, the solder ball B of the wiring board 100 is reflowed, and the connection terminal T11 is electrically connected to a connection terminal such as a mother board.

(配線基板的製造方法) (Method of Manufacturing Wiring Substrate)

圖2、圖5~圖11為顯示第1實施形態之配線基板100的製造步驟之圖。以下，參照圖2、圖5~圖11，就配線基板100的製造方法加以說明。 2 and 5 to 11 are views showing a manufacturing procedure of the wiring board 100 of the first embodiment. Hereinafter, a method of manufacturing the wiring board 100 will be described with reference to FIGS. 2 and 5 to 11.

(芯基板步驟：圖5) (core substrate step: Figure 5)

準備在板狀樹脂製基板的表面及背面貼附有銅箔而成的敷銅層板。又，使用鑽孔機對敷銅層板進行穿孔加工，將作為貫穿孔23的貫通孔事先形成於既定位置。然後，利用以往周知的方法進行無電解鍍銅及電解鍍銅，藉此於貫穿孔23內壁形成貫穿孔導體24，且於敷銅層板的兩面形成鍍銅層(參照圖5(a))。 A copper-clad laminate in which a copper foil is attached to the front and back surfaces of a plate-shaped resin substrate is prepared. Further, the copper-clad laminate is perforated using a drill, and the through-hole as the through-hole 23 is formed in advance at a predetermined position. Then, electroless copper plating and electrolytic copper plating are performed by a conventionally known method to form a through-hole conductor 24 on the inner wall of the through-hole 23, and a copper-plated layer is formed on both surfaces of the copper-clad laminate (see FIG. 5(a) ).

其後，用環氧樹脂等的樹脂埋孔材25充填貫穿孔導體24內。再者，利用以往周知的方法進行電解鍍銅，而形成蓋鍍敷層41。其次，將形成於敷銅層板兩面之銅箔上(含蓋鍍敷層41)的鍍銅蝕刻成所期望的形狀，以在敷銅層板的表面及背面分別形成構成金屬配線L1、L11的芯導體層21、22，而獲得芯基板2(參照圖5(b))。此外，較理想為，在貫穿孔23形成步驟後，進行去除加工部分的污跡之去污處理。 Thereafter, the through-hole conductor 24 is filled with a resin buried via 25 such as an epoxy resin. Further, the lid plating layer 41 is formed by electrolytic copper plating by a conventionally known method. Next, the copper plating on the copper foil (including the cap plating layer 41) formed on both sides of the copper-clad laminate is etched into a desired shape to form the metal wirings L1, L11 on the surface and the back surface of the copper-clad laminate, respectively. The core conductor layers 21 and 22 are obtained to obtain the core substrate 2 (see FIG. 5(b)). Further, it is preferable that after the step of forming the through hole 23, the stain removing treatment for removing the stain of the processed portion is performed.

(增設步驟：圖6) (Additional steps: Figure 6)

將以作為樹脂絕緣層31、131的環氧樹脂為主成分的薄膜狀絕緣樹脂材料分別重疊而配置在芯基板2的表面及背面。用真空壓接熱壓機將該積層物加壓加熱，一邊使薄膜狀絕緣樹脂材料熱硬化，一邊壓接。其次，使用以往周知的雷射加工裝置進行雷射照射，而在樹脂絕緣層31、131分別形成通路孔42a、142a(參照圖6(a))。 The film-shaped insulating resin materials containing the epoxy resin as the resin insulating layers 31 and 131 as main components are superposed on each other and placed on the front and back surfaces of the core substrate 2. The laminate was heated under pressure by a vacuum pressure bonding hot press, and the film-shaped insulating resin material was thermally cured while being pressure-bonded. Next, laser irradiation is performed using a conventionally known laser processing apparatus, and via holes 42a and 142a are formed in the resin insulating layers 31 and 131, respectively (see FIG. 6(a)).

繼之，將樹脂絕緣層31、131的表面粗化後，進行無電解鍍敷，以在包含通路孔42a，142a內壁的樹脂絕緣層31、131上形成無電解鍍銅層。其次，將感光性樹脂積層在樹脂絕緣層31、131上所形成的無電解鍍銅層上，進行曝光‧顯影，以將樹脂遮罩MR1、MR11形成為所期望的形狀。然後，以該樹脂遮罩MR1、MR11作為遮罩，藉由電解鍍敷，進行鍍銅，而獲得所期望的鍍銅圖案(金屬配線L2、L12)(參照圖6(b))。 Then, after roughening the surfaces of the resin insulating layers 31 and 131, electroless plating is performed to form an electroless copper plating layer on the resin insulating layers 31 and 131 including the inner walls of the via holes 42a and 142a. Next, a photosensitive resin is laminated on the electroless copper plating layer formed on the resin insulating layers 31 and 131, and exposure and development are performed to form the resin masks MR1 and MR11 into a desired shape. Then, the resin masks MR1 and MR11 are used as masks, and copper plating is performed by electrolytic plating to obtain desired copper plating patterns (metal wirings L2 and L12) (see FIG. 6(b)).

(凸鍍敷層形成步驟：圖7) (Protruding Plating Layer Formation Step: Figure 7)

其次，在沒有剝離樹脂遮罩MR1、MR11的情況下積層光阻劑，進行曝光‧顯影，以將樹脂遮罩MR2、MR12形成為所期望的形狀。然後，以該樹脂遮罩MR2、MR12作為遮罩，藉由電解鍍敷，進行鍍銅，而獲得所期望的鍍銅圖案(參照圖7(a))。 Next, when the resin masks MR1 and MR11 are not peeled off, a photoresist is laminated, and exposure and development are performed to form the resin masks MR2 and MR12 into a desired shape. Then, the resin masks MR2 and MR12 are used as masks, and copper plating is performed by electrolytic plating to obtain a desired copper plating pattern (see FIG. 7(a)).

接著，剝離樹脂遮罩MR1、MR2、MR11、MR12，去除存在於樹脂遮罩MR1、MR11下的無電解鍍銅層，而在導體層32、132上分別形成具有連接端子T1、墊P1的導體層34、及具有連接端子T11的導體層134(參照圖7(b))。 Next, the resin masks MR1, MR2, MR11, and MR12 are peeled off, and the electroless copper plating layer existing under the resin masks MR1 and MR11 is removed, and conductors having the connection terminals T1 and P1 are formed on the conductor layers 32 and 132, respectively. The layer 34 and the conductor layer 134 having the connection terminal T11 (see FIG. 7(b)).

(充填步驟：圖8) (filling step: Figure 8)

其次，在構成增層3的表層的複數個連接端子T1之間充填充填構件4，直到充填構件4低於連接端子T1的主面F的位置。此外，為了將充填構件4充填於連接端子T1之間，較佳為預先將連接端子T1的表面(特別是側面)粗化。連接端子T1的表面，可藉由例如用MEC Etch Bond(日本MEC股份有限公司)等的蝕刻液進行處理來進行粗化。又，作為取代將各連接端子T1的表面粗化，亦可在將Sn(錫)、Ti(鈦)、Cr(鉻)、Ni(鎳)的任一金屬元素塗佈於各連接端子T1的表面以形成金屬層後，在該金屬層上實施耦合劑處理，而使其與充填構件4的黏著性提升。 Next, the filling member 4 is filled between the plurality of connection terminals T1 constituting the surface layer of the buildup layer 3 until the filling member 4 is lower than the position of the main surface F of the connection terminal T1. Further, in order to fill the filling member 4 between the connection terminals T1, it is preferable to roughen the surface (particularly the side surface) of the connection terminal T1 in advance. The surface of the connection terminal T1 can be roughened by, for example, treatment with an etching solution such as MEC Etch Bond (Japan MEC Co., Ltd.). Further, instead of roughening the surface of each connection terminal T1, any metal element of Sn (tin), Ti (titanium), Cr (chromium), or Ni (nickel) may be applied to each connection terminal T1. After the surface is formed into a metal layer, a couplant treatment is performed on the metal layer to improve adhesion to the filling member 4.

作為將充填構件4充填於連接端子T1間的方法，可採用各種方法。以下，就將該充填構件4充填於連 接端子T1間的充填方法進行說明。此外，以下的第1~第4充填方法中，關於塗佈作為充填構件4之絕緣性樹脂的方法，可使用印刷、積層(laminate)、輥塗佈、旋轉塗佈等各種方法。 As a method of filling the filling member 4 between the connection terminals T1, various methods can be employed. Hereinafter, the filling member 4 is filled in the company A method of filling between the terminals T1 will be described. Further, in the following first to fourth filling methods, various methods such as printing, laminate, roll coating, and spin coating can be used as the method of applying the insulating resin as the filling member 4.

(第1充填方法) (first filling method)

此第1充填方法中，係藉由在表層形成有連接端子T1之增層3的表面塗佈較薄的熱硬化性絕緣性樹脂並使其熱硬化之後，將硬化的絕緣性樹脂研磨至比連接端子T1還低，而將充填構件4充填於連接端子T1間。 In the first filling method, a thin thermosetting insulating resin is applied to the surface of the buildup layer 3 having the connection terminal T1 formed on the surface layer, and the thermosetting insulating resin is thermally cured, and then the cured insulating resin is polished to a ratio. The connection terminal T1 is also low, and the filling member 4 is filled between the connection terminals T1.

(第2充填方法) (2nd filling method)

此第2充填方法中，係藉由在表層形成有連接端子T1之增層3的表面塗佈較薄的熱硬化性絕緣性樹脂之後，利用將絕緣性樹脂熔融的溶劑，去除覆蓋連接端子T1上面之多餘的絕緣性樹脂後，使之熱硬化，而將充填構件4充填至連接端子T1間。 In the second filling method, a thin thermosetting insulating resin is applied to the surface of the buildup layer 3 having the connection terminal T1 formed on the surface layer, and then the sealing connection terminal T1 is removed by using a solvent which melts the insulating resin. After the excess insulating resin on the top, it is thermally hardened, and the filling member 4 is filled between the connection terminals T1.

(第3充填方法) (3rd filling method)

在此第3充填方法中，係在表層形成有連接端子T1之增層3的表面塗佈較厚的熱硬化性絕緣性樹脂之後，遮罩半導體元件之安裝區域以外的區域，利用RIE(Reactive Ion Etching：反應離子蝕刻)等對絕緣性樹脂施以乾式蝕刻直到其高度低於連接端子T1，藉此方式，將充填構件4充填於連接端子T1間。此外，此第3充填方法中，將充填構件4充填於連接端子T1間時，充填構件4與阻焊劑層5係一體形成。 In the third filling method, a thick thermosetting insulating resin is applied to the surface of the buildup layer 3 having the connection terminal T1 formed on the surface layer, and then a region other than the mounting region of the semiconductor element is masked, and RIE (Reactive) is used. Ion Etching: reactive ion etching or the like applies dry etching to the insulating resin until the height thereof is lower than the connection terminal T1, whereby the filling member 4 is filled between the connection terminals T1. Further, in the third filling method, when the filling member 4 is filled between the connection terminals T1, the filling member 4 and the solder resist layer 5 are integrally formed.

(第4充填方法) (fourth filling method)

圖9為第4充填方法的說明圖。以下，參照圖9，就第4充填方法進行說明。第4充填方法中，係在表層形成有配線導體T1之增層3的表面塗佈較厚的光硬化性絕緣性樹脂後(參照圖9(a))，遮罩之後應作為阻焊劑層的開口5a的區域的內側區域以將絕緣性樹脂曝光‧顯影，而使應作為開口5a的外側區域之絕緣性樹脂進行光硬化(參照圖9(b))。其次，將此製造途中的配線基板100於碳酸鈉水溶液(濃度1重量%)中進行短時間(未感光部的絕緣性樹脂表面稍微膨潤的程度的時間)的浸漬(參照圖9(c))。然後，進行水洗以使膨潤的絕緣性樹脂乳化(參照圖9(d))。其次，將已膨潤‧乳化的絕緣性樹脂從製造途中的配線基板100去除(參照圖9(e))。將上述浸漬及水洗分別重複進行一次或複數次，直到未光硬化之絕緣性樹脂上端的位置低於各配線導體T1上端的位置為止。然後，藉由熱或紫外線使絕緣性樹脂硬化。此外，此第4充填方法中，將充填構件4充填於連接端子T1間時，充填構件4與阻焊劑層5係一體形成。 Fig. 9 is an explanatory diagram of a fourth filling method. Hereinafter, a fourth filling method will be described with reference to Fig. 9 . In the fourth filling method, a thick photocurable insulating resin is applied to the surface of the buildup layer 3 on which the wiring conductor T1 is formed on the surface layer (see FIG. 9( a )), and the mask should be used as a solder resist layer. The inner region of the region of the opening 5a is developed by exposing the insulating resin to light, and the insulating resin to be the outer region of the opening 5a is photocured (see FIG. 9(b)). Then, the wiring substrate 100 in the middle of the production process is immersed in a sodium carbonate aqueous solution (concentration: 1% by weight) for a short period of time (the time when the surface of the insulating resin is not slightly swelled by the photosensitive portion) (see FIG. 9(c)). . Then, it is washed with water to emulsify the swollen insulating resin (see FIG. 9(d)). Next, the swelled and emulsified insulating resin is removed from the wiring substrate 100 during the manufacturing process (see FIG. 9(e)). The immersion and the water washing are repeated one or more times, respectively, until the position of the upper end of the insulating resin which is not photohardened is lower than the position of the upper end of each of the wiring conductors T1. Then, the insulating resin is cured by heat or ultraviolet rays. Further, in the fourth filling method, when the filling member 4 is filled between the connection terminals T1, the filling member 4 and the solder resist layer 5 are integrally formed.

(阻焊劑層步驟：圖10) (Solder resist layer step: Figure 10)

分別將薄膜狀阻焊劑加壓且積層於充填構件4及增層13的表面。將積層的薄膜狀阻焊劑加以曝光‧顯影，而獲得：阻焊劑層5，其形成有使各連接端子T1的表面及側面露出之NSMD形狀的開口5a；和阻焊劑層14，其形成有使各連接端子T11的表面的一部分露出之SMD形狀的開口14a。此外，在充填步驟中採用上述第3、第4 充填方法的情況時，由於充填構件4及阻焊劑層5係一體形成，故在此步驟中，沒有必要積層阻焊劑層5。 The film-shaped solder resist is pressed and laminated on the surfaces of the filling member 4 and the buildup layer 13, respectively. The laminated film-shaped solder resist is exposed and developed to obtain a solder resist layer 5 having an NSMD-shaped opening 5a exposing the surface and the side surface of each connection terminal T1, and a solder resist layer 14 formed thereon. A part of the surface of each of the connection terminals T11 is exposed to the SMD-shaped opening 14a. In addition, the above third and fourth are used in the filling step. In the case of the filling method, since the filling member 4 and the solder resist layer 5 are integrally formed, it is not necessary to laminate the solder resist layer 5 in this step.

(鍍敷步驟：圖11) (plating step: Figure 11)

其次，利用過硫酸鈉等蝕刻連接端子T1的露出面，以去除連接端子T1表面的氧化膜等雜質，且在連接端子T1的主面F的周圍形成階差L(參照圖3)。然後，藉由使用還原劑的無電解還原鍍敷，在連接端子T1、T11的露出面形成金屬鍍敷層M。藉由無電解置換鍍敷在連接端子T1的露出面形成金屬鍍敷層M時，連接端子T1之露出面的金屬被置換而形成金屬鍍敷層M。因此，即便沒有利用過硫酸鈉等蝕刻連接端子T1的露出面，也可在連接端子T1的主面F的周圍形成階差L。 Then, the exposed surface of the connection terminal T1 is etched by sodium persulfate or the like to remove impurities such as an oxide film on the surface of the connection terminal T1, and a step L is formed around the main surface F of the connection terminal T1 (see FIG. 3). Then, the metal plating layer M is formed on the exposed surfaces of the connection terminals T1 and T11 by electroless reduction plating using a reducing agent. When the metal plating layer M is formed on the exposed surface of the connection terminal T1 by electroless displacement plating, the metal on the exposed surface of the connection terminal T1 is replaced to form the metal plating layer M. Therefore, even if the exposed surface of the connection terminal T1 is not etched by using sodium persulfate or the like, a step L can be formed around the main surface F of the connection terminal T1.

又，在連接端子T1的露出面塗佈焊料時，可依據所塗佈之焊料層的厚度，而選擇以下兩種方法。 Further, when solder is applied to the exposed surface of the connection terminal T1, the following two methods can be selected depending on the thickness of the applied solder layer.

(第1塗佈方法) (first coating method)

將厚度為5~30μm的焊料層塗佈於連接端子T1的露出面時，僅對連接端子T1的露出面實施些微的蝕刻(軟蝕刻)，以去除形成於連接端子T1的露出面之氧化膜。此時，在連接端子T1的主面F的周圍形成階差L。然後，將混合有含Sn(錫)粉末、Ag(銀)、Cu(銅)等金屬的離子性化合物及助焊劑(flux)所得的糊料(例如，HARIMA化成股份有限公司：Super Solder(製品名))，薄薄地塗佈於SMD形狀開口5a內整體，以覆蓋連接端子T1的露出面整面。然後，進行迴焊，在連接端子T1的露出面形成由Sn與Ag、或Sn、Ag及Cu的合金所構成的焊料層。 When a solder layer having a thickness of 5 to 30 μm is applied to the exposed surface of the connection terminal T1, only a slight etching (soft etching) is performed on the exposed surface of the connection terminal T1 to remove the oxide film formed on the exposed surface of the connection terminal T1. . At this time, a step L is formed around the main surface F of the connection terminal T1. Then, a paste obtained by mixing an ionic compound containing a metal such as Sn (tin) powder, Ag (silver), Cu (copper), and a flux (for example, HARIMA Chemical Co., Ltd.: Super Solder (product) The name)) is thinly applied to the entire SMD shape opening 5a so as to cover the entire surface of the exposed surface of the connection terminal T1. Then, reflow is performed, and a solder layer made of an alloy of Sn and Ag or Sn, Ag, and Cu is formed on the exposed surface of the connection terminal T1.

(第2塗佈方法) (Second coating method)

將厚度為10μm以下的焊料層塗佈於連接端子T1的露出面時，僅對連接端子T1的露出面實施些微的蝕刻(軟蝕刻)，以去除形成於連接端子T1的露出面之氧化膜。此時，在連接端子T1的主面F的周圍形成階差L。然後，藉由在連接端子T1的露出面進行無電解Sn(錫)鍍敷而形成鍍錫層，且以覆蓋該鍍錫層整面的方式塗佈助焊劑。然後，進行迴焊，使鍍敷於連接端子T1的鍍錫層熔融而在連接端子T1的主面F形成焊料層。此時，熔融的Sn藉由表面張力，凝聚於連接端子T1的主面F。 When a solder layer having a thickness of 10 μm or less is applied to the exposed surface of the connection terminal T1, only a slight etching (soft etching) is performed on the exposed surface of the connection terminal T1 to remove the oxide film formed on the exposed surface of the connection terminal T1. At this time, a step L is formed around the main surface F of the connection terminal T1. Then, a tin plating layer is formed by electroless Sn (tin) plating on the exposed surface of the connection terminal T1, and the flux is applied so as to cover the entire surface of the tin plating layer. Then, reflow is performed to melt the tin plating layer plated on the connection terminal T1 to form a solder layer on the main surface F of the connection terminal T1. At this time, the molten Sn is condensed on the main surface F of the connection terminal T1 by the surface tension.

(後端步驟：圖2) (back end steps: Figure 2)

藉由焊料印刷，在形成於連接端子T11上的金屬鍍敷層M上塗佈焊料糊之後，以既定的温度和時間進行迴焊，而在連接端子T11上形成焊料球B。 Solder paste is applied onto the metal plating layer M formed on the connection terminal T11 by solder printing, and then reflowed at a predetermined temperature and time to form a solder ball B on the connection terminal T11.

如上所述，在第1實施形態的配線基板100中，未藉由通路而將連接端子T1直接形成於導體層32上沒有經過通路。因此，不需要設置連接端子T1用的連接盤，配線布局的自由度得以提升。又，金屬配線L2之供形成連接端子T1的位置處的寬度W，係小於連接端子T1之與金屬配線L2的寬度方向一致之方向上的長度(徑)W1。因此，可抑制連接端子T1過小，與半導體晶片的連接可靠性降低的情況。 As described above, in the wiring board 100 of the first embodiment, the connection terminal T1 is not directly formed on the conductor layer 32 by the via, and there is no passage. Therefore, it is not necessary to provide a land for connecting the terminal T1, and the degree of freedom in wiring layout can be improved. Further, the width W of the metal wiring L2 at the position where the connection terminal T1 is formed is smaller than the length (diameter) W1 of the connection terminal T1 in the direction in which the width direction of the metal wiring L2 coincides. Therefore, it is possible to suppress the connection terminal T1 from being too small and the connection reliability with the semiconductor wafer to be lowered.

又，供形成連接端子T1的位置處之金屬配線L2的寬度W，為連接端子T1之與金屬配線L2的寬度方向一致之方向上的長度W1的0.5倍以上且小於1.0倍。因 此，可抑制連接端子T1變小且與半導體晶片的連接可靠性降低的情況，同時也可抑制與配線寬度W相比，連接端子T1之與金屬配線L2的寬度方向一致之方向上的長度W1變得太長，致使形成於金屬配線L2上的連接端子T1傾斜或倒塌。 Moreover, the width W of the metal wiring L2 at the position where the connection terminal T1 is formed is 0.5 times or more and less than 1.0 times the length W1 of the connection terminal T1 in the direction in which the width direction of the metal wiring L2 coincides. because In this case, it is possible to suppress the connection terminal T1 from being small and the connection reliability with the semiconductor wafer from being lowered, and also suppressing the length W1 in the direction in which the connection terminal T1 coincides with the width direction of the metal wiring L2 as compared with the wiring width W. It becomes too long, causing the connection terminal T1 formed on the metal wiring L2 to incline or collapse.

又，在供形成連接端子T1的位置，設置有配線寬度W變粗的粗寬度部L2a。因此，即便是金屬配線L2的線寬較窄的情況，或連接端子T1之與金屬配線L2的寬度方向一致之方向上的長度W1較長的情況、即連接端子T1直徑較大的情況，也可在金屬配線L2上直接形成連接端子T1。 Moreover, a thick width portion L2a in which the wiring width W is thick is provided at a position where the connection terminal T1 is formed. Therefore, even when the line width of the metal wiring L2 is narrow, or when the length W1 of the connection terminal T1 in the direction in which the width direction of the metal wiring L2 coincides is long, that is, when the diameter of the connection terminal T1 is large, The connection terminal T1 can be directly formed on the metal wiring L2.

再者，金屬配線L2的粗寬度部L2a在延伸方向上的長度W2，為連接端子T1之與金屬配線L2的延伸方向一致的方向上的長度W1的0.5倍以上且2.0倍以下。因此，可抑制粗寬度部L2a在延伸方向上變長、配線布局的自由度降低的情況。 In addition, the length W2 of the thick portion L2a of the metal wiring L2 in the extending direction is 0.5 times or more and 2.0 times or less the length W1 of the connection terminal T1 in the direction in which the metal wiring L2 extends. Therefore, it is possible to suppress the case where the thick width portion L2a becomes longer in the extending direction and the degree of freedom in wiring layout is lowered.

作為其他功效而言，由於連接端子T1間充填有充填構件4，所以與半導體晶片連接時，可防止在作為充填於半導體晶片和配線基板的間隙之底部填料或NCP(Non-Conductive Paste：非導電膠)、NCF(Non-Conductive Film：非導電膜)的連接端子T1之間發生孔隙(void)。因此，迴焊時，可防止焊料流出而在連接端子之間發生短路(short)。又，由於連接端子T1的露出面積變小，故塗佈於連接端子之焊料的直徑不會變大，可將連接端子T1窄晶片化。 As the other functions, since the connection member T1 is filled with the filling member 4, when it is connected to the semiconductor wafer, it is possible to prevent the underfill or NCP (Non-Conductive Paste) as a gap filled in the semiconductor wafer and the wiring substrate. A void occurs between the connection terminals T1 of NCF (Non-Conductive Film). Therefore, at the time of reflow, it is possible to prevent the solder from flowing out and short-circuiting between the connection terminals. Moreover, since the exposed area of the connection terminal T1 becomes small, the diameter of the solder applied to the connection terminal does not become large, and the connection terminal T1 can be made into a narrow wafer.

此外，在連接端子T1的表面形成金屬鍍敷層M時，可防止連接端子T1間的鍍敷下垂(sagging of plating)、連接端子T1的底部被蝕刻的底切(undercut)。再者，由於係在連接端子T1的第1主面F的外周形成階差L，所以塗佈於連接端子T1之焊料的直徑不會變大，可將連接端子T1進一步窄晶片化。 Further, when the metal plating layer M is formed on the surface of the connection terminal T1, it is possible to prevent the sagging of plating between the connection terminals T1 and the undercut of the bottom of the connection terminal T1 being etched. In addition, since the step L is formed on the outer circumference of the first main surface F of the connection terminal T1, the diameter of the solder applied to the connection terminal T1 does not become large, and the connection terminal T1 can be further narrowed.

又，由於是在將連接端子T1與充填構件4的抵接面粗化後，將充填構件4充填於連接端子T1間，故連接端子T1與充填構件4的黏著強度得以提升。因此，可抑制連接端子1在中途的製造步驟中被剝落之虞。又，藉由將充填構件4的材質設成與阻焊劑層5相同，充填構件4的焊料流動性成為與阻焊劑層5相同的程度，可抑制焊料殘留於充填構件4上而造成連接端子T1間發生短路(short)的情況。 Moreover, since the filling member 4 is filled between the connection terminals T1 after the contact surface of the connection terminal T1 and the filling member 4 is roughened, the adhesion strength between the connection terminal T1 and the filling member 4 is improved. Therefore, it is possible to suppress the peeling of the connection terminal 1 during the manufacturing process in the middle. Further, by setting the material of the filling member 4 to be the same as that of the solder resist layer 5, the solder fluidity of the filling member 4 is the same as that of the solder resist layer 5, and the solder remaining on the filling member 4 can be suppressed to cause the connection terminal T1. A short circuit occurs between them.

又，使充填於連接端子T1間之充填構件4的厚度D2薄於連接端子T1的厚度(高度)D1。亦即，設成連接端子T1稍微從充填構件4的上面突出的狀態。因此，即使在半導體晶片的連接端子的中心、與連接端子T1的中心偏離的情況下，由於半導體晶片的連接端子係與連接端子T1的端部抵接，所以可提升連接端子T1與半導體晶片的連接端子之連接可靠性。 Moreover, the thickness D2 of the filling member 4 filled between the connection terminals T1 is made thinner than the thickness (height) D1 of the connection terminal T1. In other words, the connection terminal T1 is slightly protruded from the upper surface of the filling member 4. Therefore, even in the case where the center of the connection terminal of the semiconductor wafer is deviated from the center of the connection terminal T1, since the connection terminal of the semiconductor wafer abuts the end of the connection terminal T1, the connection terminal T1 and the semiconductor wafer can be lifted. Connection reliability of the connection terminals.

(第1實施形態的變形例) (Modification of the first embodiment)

在參照圖1~圖11所說明的第1實施形態中，係針對將連接端子T1直接形成於導體層32的金屬配線L2上之配線基板100進行說明，惟亦可設成將通路導體 直接形成於導體層的金屬配線上。此第1實施形態的變形例中，係針對將通路導體直接形成於導體層的金屬配線上之配線基板作說明。 In the first embodiment described with reference to FIG. 1 to FIG. 11, the wiring board 100 in which the connection terminal T1 is directly formed on the metal wiring L2 of the conductor layer 32 is described. However, the via conductor may be provided. Directly formed on the metal wiring of the conductor layer. In a modification of the first embodiment, a wiring board in which a via conductor is directly formed on a metal wiring of a conductor layer will be described.

圖12為第1實施形態的變形例之配線基板100A的部分剖面圖。圖13為配線基板100A的配線及通路導體的俯視圖。以下，參照圖12及圖13，針對第1實施形態的變形例之配線基板100A的構成進行說明。此外，與參照圖1~圖11所說明的構成相同的構成，係標註相同的符號而省略重複說明。 Fig. 12 is a partial cross-sectional view showing a wiring board 100A according to a modification of the first embodiment. FIG. 13 is a plan view of a wiring and a via conductor of the wiring board 100A. The configuration of the wiring board 100A according to the modification of the first embodiment will be described below with reference to FIG. 12 and FIG. The same configurations as those described with reference to FIGS. 1 to 11 are denoted by the same reference numerals and the description thereof will not be repeated.

如圖12及圖13所示，配線基板100A係在增層3進一步具備：導體層36，係構成積層於樹脂絕緣層31的金屬配線L3；樹脂絕緣層37，係積層於導體層36；及充填通路43，係直接形成於形成導體層36的金屬配線L3上，且貫通樹脂絕緣層37以連接導體層36、32間。充填通路43具有通路孔43a與藉由鍍敷而充填於通路孔43a內側的通路導體43b。亦即，導體層36、32間係藉由通路導體43b電性連接。 As shown in FIG. 12 and FIG. 13 , the wiring layer 100A further includes a conductor layer 36 that constitutes a metal wiring L3 laminated on the resin insulating layer 31, and a resin insulating layer 37 that is laminated on the conductor layer 36; The filling via 43 is formed directly on the metal wiring L3 on which the conductor layer 36 is formed, and penetrates the resin insulating layer 37 to connect between the conductor layers 36 and 32. The filling passage 43 has a via hole 43a and a via conductor 43b which is filled inside the via hole 43a by plating. That is, the conductor layers 36 and 32 are electrically connected by the via conductor 43b.

又，配線基板100A係在增層13進一步具備：導體層136，係構成積層於樹脂絕緣層131的金屬配線L13；樹脂絕緣層137，係積層於導體層136；及充填通路143，係直接形成於形成導體層136的金屬配線L13上，且貫通樹脂絕緣層137以連接導體層136、132間。充填通路143具有通路孔143a與藉由鍍敷而充填於通路孔143a內側的通路導體143b。亦即，導體層136、132間係藉由通路導體143b電性連接。 Further, the wiring board 100A further includes a conductor layer 136 which is a metal layer L13 laminated on the resin insulating layer 131, a resin insulating layer 137 which is laminated on the conductor layer 136, and a filling via 143 which is directly formed. The metal wiring L13 on the conductor layer 136 is formed and penetrates the resin insulating layer 137 to connect between the conductor layers 136 and 132. The filling passage 143 has a via hole 143a and a via conductor 143b which is filled inside the via hole 143a by plating. That is, the conductor layers 136 and 132 are electrically connected by the via conductors 143b.

圖14為充填通路43、143與金屬配線L3、L13的俯視圖。圖14(a)係在形成充填通路43、143的位置處不具有配線寬度變粗的粗寬度部L3a、L13a之金屬配線L3、L13的俯視圖。圖14(b)係在形成充填通路43、143的位置處具有配線寬度變粗的粗寬度部(第2粗寬度部)L3a、L13a之金屬配線L3、L13的俯視圖。 FIG. 14 is a plan view of the filling passages 43, 143 and the metal wirings L3 and L13. Fig. 14 (a) is a plan view of the metal wirings L3 and L13 having the thick width portions L3a and L13a having a thick wiring width at positions where the filling paths 43 and 143 are formed. (b) of FIG. 14 is a plan view of the metal wirings L3 and L13 having the thick width portions (second thick width portions) L3a and L13a whose wiring widths are thicker at the positions where the filling paths 43 and 143 are formed.

如圖14(a)所示，金屬配線L3、L13上之供形成充填通路43、143之位置處的寬度W，宜小於充填通路43、143之與金屬配線L3、L13的寬度方向一致之方向上的長度(直徑)W1。藉由將金屬配線L3、L13之供形成充填通路43、143之位置處的寬度W，設成小於充填通路43、143之與金屬配線L3、L13的寬度方向一致之方向的長度(直徑)W1，充填通路43、143的寬度不會過細，可抑制導體層36與導體層32及導體層136與導體層132的連接可靠性降低之情形。 As shown in Fig. 14 (a), the width W at the position where the filling vias 43, 143 are formed on the metal wirings L3, L13 is preferably smaller than the direction in which the filling paths 43, 143 coincide with the width direction of the metal wirings L3, L13. The length (diameter) W1 on the upper. The width W at the position where the metal wirings L3 and L13 are formed to fill the vias 43, 143 is set to be smaller than the length (diameter) W1 of the filling vias 43, 143 in the direction in which the width directions of the metal wirings L3 and L13 coincide. The width of the filling passages 43, 143 is not excessively narrow, and the connection reliability between the conductor layer 36 and the conductor layer 32 and the conductor layer 136 and the conductor layer 132 can be suppressed from being lowered.

又，金屬配線L3、L13之供形成充填通路43、143之位置處的寬度W，宜為充填通路43、143之與金屬配線L3、L13的寬度方向一致之方向上的長度W1的0.5倍以上且小於1.0倍。藉由將金屬配線L3、L13之供形成充填通路43、143之位置處的寬度W，設成充填通路43、143之在配線的寬度方向上的長度W1的0.5倍以上且小於1.0倍，可抑制充填通路43、143變細且導體層36與導體層32及導體層136與導體層132的連接可靠性降低的情形，且可抑制充填通路43、143之寬度方向上的長度W1太過長於配線寬度W，致使形成於金屬配線L3、L13上的充填通路43、143傾斜或倒塌。 Further, the width W of the metal wirings L3 and L13 at the positions where the filling paths 43 and 143 are formed is preferably 0.5 times or more the length W1 of the filling passages 43 and 143 in the direction in which the width directions of the metal wirings L3 and L13 coincide with each other. And less than 1.0 times. The width W at the position where the metal wirings L3 and L13 are formed to fill the vias 43 and 143 is set to be 0.5 times or more and less than 1.0 times the length W1 of the filling vias 43 and 143 in the width direction of the wiring. When the filling passages 43 and 143 are thinned and the connection reliability between the conductor layer 36 and the conductor layer 32 and the conductor layer 136 and the conductor layer 132 is lowered, the length W1 in the width direction of the filling passages 43 and 143 can be suppressed from being too long. The wiring width W causes the filling passages 43, 143 formed on the metal wirings L3, L13 to be inclined or collapsed.

又，當在金屬配線L3、L13較細，且在金屬配線L3、L13上直接形成充填通路43、143的情況下，有致使充填通路43、143發生傾斜、倒塌之虞時，如圖14(b)所示，可在供形成充填通路43、143的位置，設置配線寬度W變粗的粗寬度部L3a、L13a。藉由在供形成充填通路43、143的位置，具有配線寬度較粗的粗寬度部L3a、L13a，即便是金屬配線L3、L13的線寬較窄的情況，或充填通路43、143在寬度方向上的長度W1較長的情況、即充填通路43、143的直徑較大的情況，也可在金屬配線L3、L13上直接形成充填通路43、143。 Further, when the metal wirings L3 and L13 are thin and the filling passages 43 and 143 are directly formed on the metal wirings L3 and L13, the filling passages 43 and 143 are inclined and collapsed, as shown in Fig. 14 ( As shown in b), thick width portions L3a and L13a having a thick wiring width W can be provided at positions where the filling passages 43, 143 are formed. The thick width portions L3a and L13a having a thick wiring width are provided at positions where the filling paths 43 and 143 are formed, even when the line widths of the metal wirings L3 and L13 are narrow, or the filling paths 43 and 143 are in the width direction. When the upper length W1 is long, that is, when the diameters of the filling passages 43 and 143 are large, the filling passages 43 and 143 may be directly formed on the metal wirings L3 and L13.

又，金屬配線L3、L13的粗寬度部L3a、L13a在延伸方向的長度W2，宜為充填通路43、143之與金屬配線L3、L13的延伸方向一致的方向上的長度W1的0.5倍以上且2.0倍以下。藉由金屬配線L3、L13在延伸方向上的粗寬度部L3a、L13a的長度W2，設成金屬配線L3、L13之延伸方向之充填通路43、143的長度W1的0.5倍以上且2.0倍以下，可抑制粗寬度部L3a、L13a在延伸方向上變長、配線布局的自由度降低的情況。 Moreover, the length W2 of the thick width portions L3 and L13a of the metal wires L3 and L13 in the extending direction is preferably 0.5 times or more the length W1 of the filling passages 43 and 143 in the direction in which the metal wires L3 and L13 extend. 2.0 times or less. The length W2 of the thick width portions L3a and L13a in the extending direction of the metal wires L3 and L13 is set to be 0.5 times or more and 2.0 times or less the length W1 of the filling paths 43 and 143 in the extending direction of the metal wires L3 and L13. It is possible to suppress the case where the thick width portions L3a and L13a become longer in the extending direction and the degree of freedom in wiring layout is lowered.

又，關於設有粗寬度部L3a、L13a的金屬配線L3、L13，金屬配線L3、L13之供形成充填通路43、143的位置處的寬度W，較佳為小於充填通路43、143之與金屬配線L3、L13的寬度方向一致之方向上的長度(直徑)M1，更佳為充填通路43、143之與金屬配線L3、L13的寬度方向一致的方向上的長度的0.5倍以上且小於1.0倍。 Further, regarding the metal wirings L3 and L13 in which the thick width portions L3a and L13a are provided, the width W at the position where the metal wirings L3 and L13 are formed to fill the filling passages 43, 143 is preferably smaller than the filling passages 43 and 143 and the metal. The length (diameter) M1 in the direction in which the width directions of the wires L3 and L13 match each other is preferably 0.5 times or more and less than 1.0 times the length of the filling paths 43 and 143 in the direction in which the width directions of the metal wires L3 and L13 match. .

圖15及圖16為配線基板100A的製造步驟圖。以下，參照圖15及圖16就配線基板100A的製造方法進行說明。此外，關於增設步驟以外的步驟，係與參照圖1~圖11所說明之配線基板100的製造方法相同。此處，僅說明配線基板100A的製造方法中的增設步驟，關於其他的步驟，則省略重複說明。 15 and 16 are manufacturing steps of the wiring board 100A. Hereinafter, a method of manufacturing the wiring board 100A will be described with reference to FIGS. 15 and 16 . The steps other than the additional steps are the same as those of the wiring substrate 100 described with reference to FIGS. 1 to 11 . Here, only the additional steps in the method of manufacturing the wiring board 100A will be described, and the other steps will not be repeated.

(增設步驟：圖15) (Additional steps: Figure 15)

將以作為樹脂絕緣層31、131的環氧樹脂為主成分的薄膜狀絕緣樹脂材料分別重疊而配置在芯基板2的表面及背面。用真空壓接熱壓機將該積層物加壓加熱，一邊使薄膜狀絕緣樹脂材料熱硬化，一邊壓接。其次，使用以往週知的雷射加工裝置進行雷射照射，而在樹脂絕緣層31、131分別形成通路孔42a、142a(參照圖15(a))。 The film-shaped insulating resin materials containing the epoxy resin as the resin insulating layers 31 and 131 as main components are superposed on each other and placed on the front and back surfaces of the core substrate 2. The laminate was heated under pressure by a vacuum pressure bonding hot press, and the film-shaped insulating resin material was thermally cured while being pressure-bonded. Next, laser irradiation is performed using a conventionally known laser processing apparatus, and via holes 42a and 142a are formed in the resin insulating layers 31 and 131, respectively (see FIG. 15(a)).

繼之，將樹脂絕緣層31、131的表面粗化後，進行無電解鍍敷，以在包含通路孔42a、142a內壁的樹脂絕緣層31、131上形成無電解鍍銅層。其次，將絕緣性感光性樹脂積層在樹脂絕緣層31、131上所形成的無電解鍍銅層上，進行曝光‧顯影，以將樹脂遮罩MR3、MR13形成為所期望的形狀。然後，以該樹脂遮罩MR3、MR13作為遮罩，藉由電解鍍敷，進行鍍銅，而獲得所期望的鍍銅圖案(金屬配線L3、L13)(圖15(b)參照)。 Then, after roughening the surfaces of the resin insulating layers 31 and 131, electroless plating is performed to form an electroless copper plating layer on the resin insulating layers 31 and 131 including the inner walls of the via holes 42a and 142a. Next, an insulating photosensitive resin is laminated on the electroless copper plating layer formed on the resin insulating layers 31 and 131, and exposure and development are performed to form the resin masks MR3 and MR13 into a desired shape. Then, the resin masks MR3 and MR13 are used as masks, and copper plating is performed by electrolytic plating to obtain desired copper plating patterns (metal wirings L3 and L13) (see FIG. 15(b)).

(增設步驟：圖16) (Additional steps: Figure 16)

其次，在沒有剝離樹脂遮罩MR3、MR13的情況下積層絕緣性感光性樹脂，進行曝光‧顯影，以將 樹脂遮罩MR4、MR14形成為所期望的形狀。然後，以該樹脂遮罩MR4、MR14作為遮罩，藉由電解鍍敷，進行鍍銅，而獲得所期望的鍍銅圖案(充填通路43、143)(參照圖16(a))。此外，樹脂遮罩MR3與MR4、及MR13與MR14分別成為絕緣樹脂層37、137。 Next, when the resin masks MR3 and MR13 are not peeled off, the insulating photosensitive resin is laminated, and exposure and development are performed to The resin masks MR4 and MR14 are formed into a desired shape. Then, the resin masks MR4 and MR14 are used as masks, and copper plating is performed by electrolytic plating to obtain desired copper plating patterns (filling paths 43, 143) (see FIG. 16(a)). Further, the resin masks MR3 and MR4, and MR13 and MR14 are insulating resin layers 37 and 137, respectively.

接著，將光阻劑積層於樹脂絕緣層37、137上，進行曝光‧顯影，以將樹脂遮罩MR5、MR15形成為所期望的形狀。然後，此該樹脂遮罩MR5、MR15作為遮罩，藉由電解鍍敷，進行鍍銅，而獲得所期望的鍍銅圖案(金屬配線L2、L12)(參照圖16(b))。 Next, a photoresist is laminated on the resin insulating layers 37 and 137, and exposure and development are performed to form the resin masks MR5 and MR15 into a desired shape. Then, the resin masks MR5 and MR15 are used as masks, and copper plating is performed by electrolytic plating to obtain desired copper plating patterns (metal wirings L2 and L12) (see FIG. 16(b)).

如上所述，第1實施形態之變形例的配線基板100A中，因為在充填通路43、143的形成時沒有進行雷射照射，而是藉由曝光‧顯影形成充填通路43、143用通路孔43a、143b，故無需形成作為雷射照射的擋止件(stopper)的通路連接盤。因此，可將充填通路43、143分別直接形成於形成導體層36、136的金屬配線L3、L13上。 As described above, in the wiring board 100A according to the modification of the first embodiment, since the laser irradiation is not performed at the time of forming the filling passages 43, 143, the via holes 43a for filling the passages 43 and 143 are formed by exposure and development. 143b, so there is no need to form a via lands as a stopper for laser irradiation. Therefore, the filling vias 43, 143 can be formed directly on the metal wirings L3 and L13 forming the conductor layers 36 and 136, respectively.

又，形成導體層36、136的金屬配線L3、L13上之供形成充填通路43、143的位置處的寬度，為充填通路43、143之寬度方向上的長度的0.5倍以上且小於1.0倍。因此，可將充填通路43間及充填通路143間窄晶片化，配線布局的自由度得以提升。又，可抑制充填通路43、143與形成導體層36、136的金屬配線L3、L13、及充填通路43、143與形成導體層32、132的金屬配線L2、L12之連接可靠性降低。 Moreover, the width of the metal wirings L3 and L13 forming the conductor layers 36 and 136 at the positions where the filling paths 43 and 143 are formed is 0.5 times or more and less than 1.0 times the length of the filling passages 43 and 143 in the width direction. Therefore, the gap between the filling passages 43 and the filling passages 143 can be narrowed, and the degree of freedom in wiring layout can be improved. Further, it is possible to suppress a decrease in the connection reliability between the filling vias 43, 143 and the metal wirings L3 and L13 forming the conductor layers 36 and 136 and the filling vias 43, 143 and the metal wirings L2 and L12 forming the conductor layers 32 and 132.

又，如圖14(b)所示，形成配線基板100A的導體層36、136的金屬配線L3、L13，係可在供形成充填通路43、143的位置處，具有配線寬度變粗的粗寬度部L3a、L13a。藉由在供形成充填通路43、143的位置處具有配線寬度變粗的粗寬度部L3a、L13a，可將直徑較大的充填通路43、143直接形成於金屬配線L3、L13上。又，充填通路43、143與形成導體層36、136的金屬配線L3、L13，以及充填通路43、143與形成導體層32、132的金屬配線L2、L12之連接可靠性得以提升。 Further, as shown in FIG. 14(b), the metal wirings L3 and L13 forming the conductor layers 36 and 136 of the wiring board 100A have a thick width in which the wiring width becomes thick at a position where the filling vias 43 and 143 are formed. Parts L3a, L13a. By providing the thick width portions L3a and L13a having a thick wiring width at the positions where the filling passages 43, 143 are formed, the filling passages 43 and 143 having a large diameter can be directly formed on the metal wirings L3 and L13. Further, the connection reliability between the filling vias 43, 143 and the metal wirings L3 and L13 forming the conductor layers 36 and 136, and the filling vias 43, 143 and the metal wirings L2 and L12 forming the conductor layers 32 and 132 is improved.

再者，形成導體層36、136之金屬配線L3、L13的粗寬度部L3a、L13a在延伸方向的長度，可設成充填通路43、143之延伸方向的長度的0.5倍以上且2.0倍以下。藉由形成導體層36、136之金屬配線L3、L13的粗寬度部L3a、L13a在延伸方向的長度，設成充填通路43、143之延伸方向的長度的0.5倍以上且2.0倍以下，粗寬度部L3a、L13a在延伸方向的長度不會過長，可抑制配線布局的自由度降低。 In addition, the lengths of the thick width portions L3a and L13a of the metal wirings L3 and L13 forming the conductor layers 36 and 136 in the extending direction may be set to be 0.5 times or more and 2.0 times or less the length of the filling paths 43 and 143 in the extending direction. The length of the thick width portions L3a and L13a of the metal wires L3 and L13 forming the conductor layers 36 and 136 in the extending direction is set to be 0.5 times or more and 2.0 times or less the length of the filling paths 43 and 143 in the extending direction, and the width is wide. The lengths of the portions L3a and L13a in the extending direction are not excessively long, and the degree of freedom in wiring layout can be suppressed from being lowered.

此外，上述說明中，雖將充填通路43、143直接形成於形成導體層36、136的金屬配線L3、L13上，但是關於其他的充填通路例如充填通路42、142，亦可直接形成於形成導體層21、22的金屬配線L1、L11上。 Further, in the above description, the filling vias 43 and 143 are directly formed on the metal wirings L3 and L13 forming the conductor layers 36 and 136. However, other filling vias, for example, the filling vias 42 and 142 may be formed directly on the conductors. The metal wirings L1, L11 of the layers 21, 22 are on.

(第2實施形態) (Second embodiment)

圖17為第2實施形態的配線基板200的俯視圖(表面側)。如圖17所示，較佳為構成，僅在安裝於該 配線基板200之半導體晶片(零件)的安裝區域(零件搭載區域)的外周部配列複數個連接端子T1作為信號用連接端子T1(以虛線記載)，且在安裝區域的中央部配列複數個電源及接地連接盤用連接墊P2(以實線記載)。藉由將連接端子T1作為配線長度較長且配線的引繞難以進行的信號用連接端子T1使用，配線的引繞可容易進行，可提升配線布局的自由度。又，藉由在安裝區域的中央部，配列複數個電源及接地連接盤用連接墊P2，可縮短電源及接地連接盤用配線長度。 FIG. 17 is a plan view (surface side) of the wiring board 200 of the second embodiment. As shown in FIG. 17, it is preferably configured to be mounted only on the In the outer peripheral portion of the mounting region (part mounting region) of the semiconductor wafer (part) of the wiring substrate 200, a plurality of connection terminals T1 are arranged as signal connection terminals T1 (indicated by broken lines), and a plurality of power sources are arranged in the central portion of the mounting region. The grounding pad is connected to the pad P2 (disclosed by the solid line). By using the connection terminal T1 as the signal connection terminal T1 in which the wiring length is long and the wiring is difficult to be used, the wiring can be easily wound, and the degree of freedom in wiring layout can be improved. Further, by arranging a plurality of power supply and ground connection pad connection pads P2 in the central portion of the mounting area, the wiring length of the power supply and the ground connection plate can be shortened.

(第3實施形態) (Third embodiment)

圖18為第3實施形態之配線基板300的俯視圖(表面側)。圖19為圖18的線段I-I之配線基板200的部分剖面圖。以下，參照圖18、圖19，就配線基板300的構成進行說明，而與參照圖1~圖11所說明的第1實施形態的配線基板100相同的構成，係標註相同的符號以省略重複說明。 FIG. 18 is a plan view (surface side) of the wiring board 300 according to the third embodiment. Fig. 19 is a partial cross-sectional view showing the wiring board 200 of the line segment I-I of Fig. 18. In the following, the configuration of the wiring board 300 will be described with reference to FIG. 18 and FIG. 19, and the same components as those of the wiring board 100 of the first embodiment described with reference to FIGS. 1 to 11 are denoted by the same reference numerals to omit overlapping description. .

在參照圖1~圖11所說明的第1實施形態的配線基板100中，將薄膜狀阻焊劑加壓且積層於充填構件4的表面，將此積層的薄膜狀阻焊劑加以曝光‧顯影，而形成有阻焊劑層5。該阻焊劑層5係形成有使各連接端子T1的表面及側面露出之NSMD形狀的開口5a。然而，亦可設成在圖18、圖19未設置阻焊劑層5。此外，關於第3實施形態之配線基板300的效果，係與第1實施形態的配線基板100相同。 In the wiring board 100 of the first embodiment described with reference to FIG. 1 to FIG. 11, a film-shaped solder resist is pressed and laminated on the surface of the filling member 4, and the laminated film-shaped solder resist is exposed and developed. A solder resist layer 5 is formed. The solder resist layer 5 is formed with an opening 5a having an NSMD shape in which the front surface and the side surface of each connection terminal T1 are exposed. However, it is also possible to provide that the solder resist layer 5 is not provided in FIGS. 18 and 19. The effect of the wiring board 300 of the third embodiment is the same as that of the wiring board 100 of the first embodiment.

(第4實施形態) (Fourth embodiment)

圖20為第4實施形態之配線基板400的俯視圖(表面側)。圖21為圖20的區域A的放大俯視圖。以下，參照圖20、圖21，針對配線基板400的構成進行說明，但與參照圖1~圖19說明的第1實施形態~第3實施形態的配線基板100~300相同的構成，係標註相同的符號以省略重複說明。 FIG. 20 is a plan view (surface side) of the wiring board 400 of the fourth embodiment. Fig. 21 is an enlarged plan view of a region A of Fig. 20. In the following, the configuration of the wiring board 400 will be described with reference to FIG. 20 and FIG. 21, but the same configurations as those of the wiring boards 100 to 300 of the first embodiment to the third embodiment described with reference to FIGS. 1 to 19 are denoted by the same reference numerals. The symbols are omitted to omit the repetition.

在此第4實施形態的配線基板400中，將阻焊劑層5的開口5a設成設置於半導體晶片的安裝區域的周邊之所謂的周邊的形狀(peripheral shape)。此外，關於第4實施形態的配線基板400的效果，係與第1實施形態的配線基板100相同。 In the wiring board 400 of the fourth embodiment, the opening 5a of the solder resist layer 5 is formed in a so-called peripheral shape provided around the mounting region of the semiconductor wafer. The effect of the wiring board 400 of the fourth embodiment is the same as that of the wiring board 100 of the first embodiment.

(其他的實施形態) (Other embodiments)

在參照圖1~圖21說明的配線基板100、100A、200~400中，分別充填於連接端子T1間之充填構件4的上面係成為平坦(flat)，充填構件4的上面不一定要為平坦(flat)，例如，如圖22所示，亦可作成充填構件4的上面為帶有圓形之所謂的內圓角(fillet)狀，可獲得同樣的效果。 In the wiring boards 100, 100A, 200 to 400 described with reference to FIGS. 1 to 21, the upper surface of the filling member 4 which is filled between the connection terminals T1 is flat, and the upper surface of the filling member 4 does not have to be flat. For example, as shown in Fig. 22, the upper surface of the filling member 4 may be a so-called fillet shape having a circular shape, and the same effect can be obtained.

以上，雖舉出具體例來詳細說明本發明，但本發明不限定於上述內容，只要不脫離本發明的範疇，便可進行各種變形或變更。例如，上述具體例中，係針對配線基板100、100A、200~400經由焊料球B與母板等連接的BGA基板之形態作說明，但亦可設成：將作為設置有銷或連接盤來取代焊料球B之所謂的PGA(Pin Grid Array：針柵陣列)基板或LGA(Land Grid Array：連接盤平面柵格陣列)基板的配線基板100、100A、200~400與母板等連接。 The present invention has been described in detail by way of specific examples, and the invention is not limited thereto, and various modifications and changes can be made without departing from the scope of the invention. For example, in the above-described specific example, the form of the BGA substrate to which the wiring boards 100, 100A, and 200 to 400 are connected via the solder ball B and the mother board is described. However, it may be set as a pin or a land. The so-called PGA (Pin) that replaces the solder ball B The wiring substrates 100, 100A, 200 to 400 of the Grid Array: Grid Array substrate or LGA (Land Grid Array) substrate are connected to a mother board or the like.

又，連接端子T1從俯視觀之，係呈圓形的柱狀形狀，但亦可為其他的形狀，例如：俯視看起來呈四角的四角柱形狀或俯視看起來呈三角的三角柱形狀。又，第1、第3實施形態皆如圖17所示，係構成為在安裝於配線基板100、100A、300之半導體晶片(零件)的安裝區域(零件搭載區域)的外周側配列連接端子T1作為信號用連接端子T1，在安裝區域的中央側配置電源及接地連接盤用連接墊P2。 Further, the connection terminal T1 has a circular columnar shape in plan view, but may have another shape, for example, a quadrangular prism shape which looks like a four-corner shape in a plan view or a triangular prism shape which looks triangular in a plan view. In addition, as shown in FIG. 17, the first and third embodiments are configured such that the connection terminals T1 are arranged on the outer peripheral side of the mounting region (component mounting region) of the semiconductor wafer (component) mounted on the wiring boards 100, 100A, and 300. As the signal connection terminal T1, the power supply and the ground connection pad connection pad P2 are disposed on the center side of the mounting region.

再者，本實施例中，採用第1充填方法和第2充填方法時，係在形成充填構件4之後再形成阻焊劑層5，惟亦可設成在形成阻焊劑層5之後再將充填構件4充填於連接端子T1間。 Further, in the present embodiment, when the first filling method and the second filling method are employed, the solder resist layer 5 is formed after the filling member 4 is formed, but it is also possible to provide the filling member after the formation of the solder resist layer 5 4 is filled between the connection terminals T1.

AM‧‧‧對準遮罩 AM‧‧ Alignment mask

T1‧‧‧連接端子 T1‧‧‧ connection terminal

4‧‧‧充填構件 4‧‧‧Filling components

5‧‧‧阻焊劑層 5‧‧‧Solder layer

5a、5b‧‧‧開口 5a, 5b‧‧‧ openings

Claims (9)

一種配線基板，係具有分別積層有一層以上的絕緣層及導體層之積層體，該配線基板的特徵為，具備：形成於前述積層體上的複數個配線；及直接形成於前述複數個配線的至少一部分的配線上之柱狀連接端子；形成前述至少一部分的配線的前述連接端子之位置處的寬度，小於前述連接端子之前述寬度方向上的長度，前述至少一部分的配線係在形成有前述連接端子的位置，具有配線寬度變粗的第1粗寬度部。 A wiring board having a laminated body in which one or more insulating layers and a conductor layer are laminated, the wiring board having a plurality of wirings formed on the laminated body and directly formed on the plurality of wirings a columnar connection terminal on at least a part of the wiring; a width at a position of the connection terminal forming the at least one portion of the wiring is smaller than a length in the width direction of the connection terminal, and at least a part of the wiring is formed with the connection The position of the terminal has a first thick width portion in which the wiring width is thick. 如申請專利範圍第1項之配線基板，其中，形成前述至少一部分的配線的前述連接端子之位置處的寬度，為前述連接端子之前述寬度方向上的長度的0.5倍以上且小於1.0倍。 In the wiring board according to the first aspect of the invention, the width of the connection terminal forming the wiring of at least a part of the wiring is 0.5 times or more and less than 1.0 times the length of the connection terminal in the width direction. 如申請專利範圍第1項之配線基板，其中，前述第1粗寬度部的前述至少一部分的配線的延伸方向上之長度，為前述連接端子之前述延伸方向上的長度的0.5倍以上且2.0倍以下。 The wiring board according to the first aspect of the invention, wherein the length of the wiring in the extending direction of the at least one portion of the first thick portion is 0.5 times or more and 2.0 times the length of the connecting terminal in the extending direction. the following. 一種配線基板，係具有分別積層有一層以上的絕緣層及導體層之積層體，該配線基板的特徵為，具備：形成於前述積層體上的複數個配線；及 直接形成於前述複數個配線的至少一部分的配線上之柱狀連接端子；形成前述至少一部分的配線的前述連接端子之位置處的寬度，小於前述連接端子之前述寬度方向上的長度，又具備覆蓋前述複數個配線，以使前述連接端子的至少一部分露出的阻焊劑層。 A wiring board having a laminated body in which one or more insulating layers and a conductor layer are laminated, and the wiring board is characterized by comprising: a plurality of wirings formed on the laminated body; a columnar connection terminal formed directly on the wiring of at least a part of the plurality of wires; a width at a position of the connection terminal forming the at least one of the wires is smaller than a length in the width direction of the connection terminal, and is covered The plurality of wires are solder resist layers that expose at least a portion of the connection terminals. 如申請專利範圍第4項之配線基板，其中，前述連接端子的至少一部分係從前述阻焊劑層的表面突出。 The wiring board of claim 4, wherein at least a part of the connection terminal protrudes from a surface of the solder resist layer. 一種配線基板，係具有分別積層有一層以上的絕緣層及導體層之積層體，該配線基板的特徵為，具備：形成於前述積層體上的複數個配線；及直接形成於前述複數個配線的至少一部分的配線上之柱狀連接端子；形成前述至少一部分的配線的前述連接端子之位置處的寬度，小於前述連接端子之前述寬度方向上的長度，僅在設定於前述積層體上的矩形零件搭載區域的外周部配置複數個前述連接端子作為信號用連接端子，且在前述零件搭載區域的中央部，配列複數個電源及接地連接盤用連接墊。 A wiring board having a laminated body in which one or more insulating layers and a conductor layer are laminated, the wiring board having a plurality of wirings formed on the laminated body and directly formed on the plurality of wirings a columnar connection terminal on at least a part of the wiring; a width at a position of the connection terminal forming the wiring of at least a part of the wiring is smaller than a length in the width direction of the connection terminal, and only a rectangular part set on the laminated body A plurality of the connection terminals are disposed as signal connection terminals in the outer peripheral portion of the mounting region, and a plurality of power supply and ground connection pads are disposed in a central portion of the component mounting region. 一種配線基板，係具有分別積層有一層以上的絕緣層及導體層之積層體，該配線基板的特徵為， 具備：形成於前述積層體上的複數個配線；及直接形成於前述複數個配線的至少一部分的配線上之柱狀連接端子；形成前述至少一部分的配線的前述連接端子之位置處的寬度，小於前述連接端子之前述寬度方向上的長度，前述積層體係交替積層複數個前述導體層與複數個前述絕緣層而成，並具備通路導體，該通路導體係直接形成於形成前述導體層的複數個配線上且貫通前述絕緣層而將前述導體層間連接；形成前述導體層的配線之形成有前述通路導體的位置處的寬度，為前述通路導體之前述寬度方向上的長度的0.5倍以上且小於1.0倍。 A wiring board having a laminated body in which one or more insulating layers and a conductor layer are laminated, and the wiring board is characterized in that a plurality of wirings formed on the laminated body; and a columnar connection terminal formed directly on the wiring of at least a part of the plurality of wirings; and a width at a position of the connection terminal forming the at least one portion of the wiring is smaller than The length of the connection terminal in the width direction, the laminated system alternately stacks a plurality of the plurality of conductor layers and the plurality of the insulating layers, and includes a via conductor, and the via guiding system is directly formed on the plurality of wirings forming the conductor layer The conductor layers are connected to each other through the insulating layer, and the width of the wiring forming the conductor layer at the position where the via conductor is formed is 0.5 times or more and less than 1.0 times the length of the via conductor in the width direction. . 如申請專利範圍第7項之配線基板，其中，形成前述導體層的配線，係在形成有前述通路導體的位置處，具有配線寬度變粗的第2粗寬度部。 The wiring board of the seventh aspect of the invention, wherein the wiring forming the conductor layer has a second thick width portion having a thick wiring width at a position where the via conductor is formed. 如申請專利範圍第8項之配線基板，其中，形成前述導體層之前述配線的第2粗寬度部在延伸方向上的長度，為前述通路導體在前述延伸方向上的長度的0.5倍以上且2.0倍以下。 The wiring board according to the eighth aspect of the invention, wherein the length of the second thick portion of the wiring forming the conductor layer in the extending direction is 0.5 times or more and 2.0 times the length of the via conductor in the extending direction. Less than the following.
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