JPH04221881A - Manufacture of printed circuit board - Google Patents

Abstract

PURPOSE:To provide a manufacturing method of a printed circuit board which can reduce the number of plating leads to an irreducible minimum limit when many chip components and a bare chip IC are placed in mixture, eliminate degradation in reliability of connection, wire in high density, maintain electric characteristic and reduce a manufacturing cost. CONSTITUTION:A method of manufacturing a printed circuit board 1 on which chip components 13 to be electrically connected by soldering and a bare chip IC 10 to be electrically connected by wire bonding are mounted. The method has a step of plating nickel and gold on a conductor pattern 5 by electroless plating after the pattern 5 is formed on the board 1 by a subtractive method, etc., a step of covering a region except a region R for mounting the IC 10 with plating resist, and a step of plating gold on the pattern 5 of the part except the resist by electroless plating.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a printed wiring board on which chip components are electrically connected by soldering and bare chip ICs are electrically connected by wire bonding.

0002

[Prior Art] Conventionally, when mounting electronic components such as flat package ICs, chip resistors, and chip capacitors on a printed circuit board, a predetermined pattern is printed on the printed circuit board using cream solder, and the electronic components are placed there. After that, the electronic components were mounted on the printed circuit board by heating with an infrared heater or the like to reflow the cream solder. In this case, nickel-gold plating is performed by electroless plating or electrolytic plating to prevent rust on the copper pattern.

Furthermore, in order to mount a bare chip IC on a printed circuit board and perform wire bonding using gold wire, it is necessary to apply nickel-gold plating to the pad portion by electrolytic plating or electroless plating. In this case, nickel needs to have a thickness of 5 to 10 μm in order to have the hardness to withstand the heat and pressure applied during wire bonding, and gold needs to have a high purity of 99.99% or more, and the thickness is 0. It is necessary that the thickness is .3 to 0.5 μm or more.

0004

However, in recent years, chip components such as resistors and capacitors have been mixedly mounted on the periphery of bare chip ICs by wire bonding. In this case, if the bare chip IC and a few resistors, capacitors, etc. are placed around it, plated leads are provided to all the pads of the bare chip IC and chip components, and nickel is electrolytically plated.
Can be gold plated. However, for example, in the case of hybrid IC applications, where a large number of resistors, capacitors, etc. are required, and a bare chip IC must be mounted together with these resistors, capacitors, etc., there are the following constraints. ■
Since wiring is complicated and detouring is difficult, it is difficult to provide plated leads to all pads of a chip component. Furthermore, if the printed circuit board is made larger, the wiring length becomes longer, which makes it easier to pick up noise and deteriorates electrical characteristics such as increased propagation delay. Furthermore, multi-layering increases the cost. ■0.3~0.0.
After applying 5 μm gold plating, solder printing is performed on top of it.
Heating for solder reflow causes the solder to diffuse into the gold plating layer, forming a thick diffusion layer and reducing the reliability of soldering. The overall effect of this decrease in reliability becomes greater as the number of chip components increases. Therefore,
In order to prevent the above diffusion of solder, gold plating is required to have a thickness of 0.1 μm or less on pads on which chip components are placed, and to avoid creating a thick diffusion layer, and also for wire bonding of bare chip ICs. A thickness of 0.3 to 0.5 μm is required.

Under such conditions, when electronic components are mounted on a printed circuit board by reflowing the cream solder, nickel-gold plating by electrolytic plating requires attaching a plating lead for plating and making the circuit independent after plating. Therefore, it is necessary to divide the plated leads, and there is a problem in that it is undesirable to perform such an operation over the entire printed circuit board because it increases the cost.

SUMMARY OF THE INVENTION Therefore, an object of the present invention is to provide a method that does not require many plated leads and does not reduce connection reliability when a large number of chip components and bare chip ICs are mounted together.
Moreover, it is an object of the present invention to provide a method for manufacturing a printed wiring board that allows high-density wiring, maintains electrical characteristics, and reduces manufacturing costs.

[0007]

[Means for Solving the Problems] In order to achieve the above object, the present invention provides a printed circuit board made of an insulating material, on which chip components are electrically connected by soldering, and electrical connections are made by wire bonding. A method of manufacturing a printed wiring board on which a bare chip IC is mounted includes forming a conductor pattern on the printed circuit board and then plating nickel and gold on the conductor pattern by electroless plating, and an area where the bare chip IC is mounted. The gist of this method is a method for manufacturing a printed wiring board, which includes the steps of covering the area other than the plating resist with a plating resist, and applying gold plating to the conductor pattern in the area other than the plating resist by electrolytic plating.

[0008]

[Operation] First, after a conductor pattern is formed on a printed circuit board, nickel and gold are plated on the entire conductor pattern by electroless plating, and then the area except the area where the bare chip IC is mounted is covered with a plating resist. ,
Subsequently, areas other than the plating resist are plated with gold by electrolytic plating. As a result, a printed wiring board is formed on which both chip components, which are electrically connected by soldering, and bare chip ICs, which are electrically connected by wire bonding, can be mounted under favorable conditions.

[0009]

[Embodiment] An embodiment embodying the present invention will be described below with reference to FIGS. 1 to 10 for each step. (1) A process of plating nickel and gold by electroless plating. As shown in FIG. 6, first, through-holes 2 are formed in a printed circuit board 1 made of a copper-clad glass epoxy laminate using an NC drill, and then, as shown in FIG. 7, electroless copper plating and electrolytic copper plating are applied. By doing so, a copper plating layer 3 is formed. In place of the above-mentioned glass epoxy laminate, a laminate of composite, glass polyimide, glass triazine, paper epoxy, Teflon, etc. can be used. next,
As shown in FIG. 8, an etching resist layer 4 is formed using a dry film on the conductive pattern portion, and then etching is performed as shown in FIG. Subsequently, as shown in FIG. 10, the etching resist layer 4 is peeled off to form a conductor pattern 5.

Next, as shown in FIG. 2, a nickel plating layer 6 is formed on the conductor pattern 5 by electroless plating using a commercially available nickel (Ni)-phosphorus (P) plating bath. Form to a thickness of 5 μm. and,
A gold plating layer 7 with a thickness of about 0.05 μm is formed on the nickel plating layer 6 using a commercially available displacement gold plating bath. Note that as a method for forming the conductor pattern 5 of this printed circuit board 1, in addition to the above-mentioned subtractive method using etching, a semi-additive method or a full-additive method can also be adopted. Further, as the electroless nickel plating bath, a nickel-boron bath or the like can be used instead of the nickel-phosphorus plating bath, and a reduced gold plating bath can also be used instead of the displacement gold plating bath. However, when using this reduced gold plating bath, it is important to keep the treatment time short and to prevent the gold plating from becoming much thicker than 0.1 μm.

As mentioned above, in this process, 0.1 μm of gold is deposited on the conductor pattern 5 and the pad portion of the chip component.
m or less, so even if cream solder is applied on top of it and heated for reflow, a thick diffusion layer will not be created between the solder and the gold, and there will be no so-called solder erosion. Excellent attachment reliability. Furthermore, since the thickness of the gold plating can be made thinner than before, costs can be reduced accordingly. Furthermore, since the entire conductive pattern 5 is covered with gold, migration of copper melting from the conductive pattern 5 can be prevented. (2) A step of covering the area other than the area where the bare chip IC is mounted with a plating resist.

As shown in FIGS. 3 and 5, a solder resist layer 9 was printed by screen printing on the gold-plated printed circuit board 1 except for the pad portions 8a and 8b. As shown in FIGS. 1 and 5, a chip component 13 is mounted on one pad portion 8a, and a chip component 13 is mounted on the other pad portion 8b.
One end of the gold wire 14 is connected to the bare chip IC 10, and the other end thereof is wire-bonded. As the solder resist layer 9, an epoxy resin applied by a screen printing method, a film-like photocurable acrylic resin used as an adhesive, a liquid photocurable acrylic resin used as an adhesive, or the like can be used. Next, a dry film plating resist layer 11 was formed in a region other than the region R where the bare chip IC 10 is mounted.

The step of applying the solder resist layer 9 may be performed either before or after gold plating by electrolytic plating, which will be described later, as long as it is after applying nickel and gold to the entire conductor pattern 5 by electroless plating. (3) Process of applying gold plating by electrolytic plating. As shown in FIG. 4, the part of the bare chip IC 10 mounted on the printed circuit board 1 on which the dry film plating resist layer 11 is not applied is electrolytically plated using a plating lead (not shown) to a thickness of 0.5 μm. A gold plating layer 12 was applied. Next, as shown in FIG. 1, after peeling off the dry film plating resist layer 11, external processing was performed. Then, the bare chip IC 10 was mounted by wire bonding using the gold wire 14, thereby obtaining a desired printed wiring board.

[0014] Through this process of applying the gold plating layer 12 by electrolytic plating, the thickness of the gold plating layer 12 is 0.3 μm.
Since the above can be ensured, wire bonding can be performed with high reliability. As described above, according to the printed wiring board manufacturing method of this embodiment, a large number of chip components 13
When a bare chip IC 10 and a bare chip IC 10 are mounted together, it is only necessary to attach the plated leads to the pad part 8b for the bare chip IC 10, and there is no need to attach them to the pad part 8a for the chip component 13, so the number of plated leads can be minimized. There is no need to enlarge the printed circuit board 1 or make it multi-layered for plated leads. Therefore, noise,
Deterioration of electrical characteristics such as propagation speed can be prevented, and manufacturing costs can be reduced. Furthermore, high-density wiring can be achieved by the amount of unnecessary plated leads.

[0015]

[Effects of the Invention] According to the present invention, when a large number of chip components and bare chip ICs are mounted together, the number of plating leads for electrolytic plating can be minimized, and the reliability of the connection does not deteriorate. Moreover, it has excellent effects in that high-density wiring is possible, electrical characteristics can be maintained, and manufacturing costs can be reduced.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing an embodiment of the present invention, and is a cross-sectional view showing a printed wiring board on which a bare chip IC is mounted.

FIG. 2 is a cross-sectional view showing a state in which a gold plating layer is formed on a conductor pattern portion by electroless plating.

FIG. 3 is a cross-sectional view showing a state in which a plating resist is applied to a portion other than the area where a bare chip IC is mounted.

FIG. 4 is a cross-sectional view showing a state in which gold plating is applied by electrolytic plating to an area where a bare chip IC is mounted.

[Figure 5] Chip components and bare chip IC on a printed circuit board
FIG.

FIG. 6 is a cross-sectional view showing a state in which through holes are provided in the printed circuit board.

[Figure 7] Electroless copper plating is applied to the printed circuit board in Figure 6.
FIG. 3 is a cross-sectional view showing a state in which a copper plating layer is formed.

FIG. 8 is a cross-sectional view showing a state in which an etching resist layer is provided on a portion of a conductor pattern.

9 is a sectional view showing the printed circuit board of FIG. 8 after being etched; FIG.

10 is a cross-sectional view showing the printed circuit board of FIG. 9 after the etching resist layer has been peeled off.

[Explanation of symbols]

1 Printed circuit board, 5 Conductor pattern, 10 Bare chip IC, 11 Dry film plating resist layer as plating resist layer, 13 Chip component, R
Area for mounting bare chip ICs

Claims (1)

[Claims] 1. A chip component (1) that is electrically connected by soldering on a printed circuit board (1) made of an insulating material.
13) and a bare chip IC (10) that is electrically connected by wire bonding, after forming a conductor pattern (5) on the printed circuit board (1), (5) Step of plating nickel and gold by electroless plating on the area (R) where the bare chip IC (10) is mounted;
a step of covering the area except for with a plating resist (11);
A method for manufacturing a printed wiring board, comprising the step of applying gold plating to a portion of the conductor pattern (5) other than the plating resist (11) by electrolytic plating.