JPS60149195A - Method of producing printed circuit board - Google Patents

Method of producing printed circuit board

Info

Publication number
JPS60149195A
JPS60149195A JP522584A JP522584A JPS60149195A JP S60149195 A JPS60149195 A JP S60149195A JP 522584 A JP522584 A JP 522584A JP 522584 A JP522584 A JP 522584A JP S60149195 A JPS60149195 A JP S60149195A
Authority
JP
Japan
Prior art keywords
hole
printed wiring
wiring board
wall surface
board
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP522584A
Other languages
Japanese (ja)
Other versions
JPH0336319B2 (en
Inventor
勝美 馬渕
柳瀬 一英
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Ibiden Co Ltd
Original Assignee
Ibiden Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ibiden Co Ltd filed Critical Ibiden Co Ltd
Priority to JP522584A priority Critical patent/JPS60149195A/en
Publication of JPS60149195A publication Critical patent/JPS60149195A/en
Publication of JPH0336319B2 publication Critical patent/JPH0336319B2/ja
Granted legal-status Critical Current

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  • Printing Elements For Providing Electric Connections Between Printed Circuits (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。
(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【発明の詳細な説明】 本発明は、プリント配線基板の外形の側壁面に選択的に
導体を形成したプリント配線基板の製造方法に関する。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for manufacturing a printed wiring board in which a conductor is selectively formed on the outer side wall surface of the printed wiring board.

従来プリント配線基板の側壁面に導体を形成したプリン
ト配線基板としては、第1図の斜視図に示すようにスル
ホールを形成した後に、該スルホールを縦方向に切断し
て開口導体(2)を形成したプリント配線基板が、例え
ば実開昭50−92356号により開示されている。か
かる基板の製造方法としては、プリント基板の外形線上
に穴を明け、スルホールメッキを施した後、金型の打ち
抜き加工などにより基板の厚さ方向、すなわち該基板の
水平方向に対してほぼ垂直方向に切断してスルホールの
一部を切シ離し、残る穴の一部分をもってプリント基板
の導体を形成する方法が採用されている。
Conventionally, as a printed wiring board in which a conductor is formed on the side wall surface of the printed wiring board, a through hole is formed as shown in the perspective view of Fig. 1, and then the through hole is cut vertically to form an open conductor (2). A printed wiring board is disclosed, for example, in Japanese Utility Model Application Publication No. 50-92356. The manufacturing method for such a board is to drill holes on the outline of the printed circuit board, apply through-hole plating, and then punch out holes in the thickness direction of the board, that is, in a direction substantially perpendicular to the horizontal direction of the board, by punching a mold. A method has been adopted in which a portion of the through hole is separated by cutting, and the remaining portion of the hole is used to form the conductor of the printed circuit board.

また別の方法としては、第2図の斜視図に示すように側
壁面に形成された導体の一部分に切り込み(3)を入れ
、プリント基板の側壁面に絶縁され、かつ独立したパタ
ーンを形成する方法がある。
Another method is to make a cut (3) in a part of the conductor formed on the side wall surface, as shown in the perspective view of FIG. 2, to form an insulated and independent pattern on the side wall surface of the printed circuit board. There is a way.

しかしながら、前記従来例のいずれにおいてもスルホー
ルの切断時又は側壁面上の導体の一部分に切り込みを入
れる際にスルホールあるいは導体の一部分が剥れ、いわ
ゆるカエリを発生する欠点があった。このような欠点は
、特に基板の厚さが厚くなるに従ってスルホールの切断
は回部となり、メッキのハガレ、カエリが顕著となり製
品の歩留りに著しく悪い影響を与えるなどの欠点があっ
た。
However, all of the conventional examples described above have the disadvantage that when cutting the through-hole or cutting a portion of the conductor on the side wall surface, a portion of the through-hole or the conductor peels off, resulting in so-called burrs. These drawbacks include the fact that as the thickness of the substrate increases, the through-holes are cut more frequently, causing noticeable peeling and burring of the plating, which has a significant negative impact on the yield of the product.

このような欠点を解消する一例として特公昭56−54
648号公報により、「時計用回路基板のTlt?iU
形成方法」が提案されている、この発明によれば、時計
用回路基板に一定の間隔をおいて一対の小孔を設ける工
程と、これら各小孔の少くとも一部を覆うような径を有
する大孔を設ける工程と、スルホールメッキ後に大孔と
小孔の一部を残して他の部分を除去する切り離し工程と
により、切断するスルホールと金型の打ち抜き線とが交
差する角、すなわち交差角を適切な値とする方法が示さ
れている。それによって、大孔の左右に設けられた小孔
が交差角を調整することになりスルホール(大孔)を打
ち抜き加工する際に該部分のパターンすなわちメッキ層
の剥れを防止するものである、しかしながら、プリント
配線板は最近高密度実装が要求されるに伴い増々微細化
しており、パターン間隔が狭くなる傾向があるため、前
記方法のように大孔とその左右両端に設けた小孔との3
つの穴を設けることは微細化、高密度化に適合しなくな
り好しくない方法である。また、前記大孔と小孔の重な
り部分からプリント配線基板の基材中のガラスクロス及
び銅箔の切り残り部分がヒゲ状に突出し、この突出した
ヒゲにもスルホールメッキが形成されるためスルホール
メッキ前に突出したヒゲを除去する余分の工4♀を要す
る欠点がある。
As an example of resolving these shortcomings,
According to Publication No. 648, "Tlt?iU of circuit board for watch"
According to the invention, a pair of small holes are formed at a certain interval on a watch circuit board, and a diameter is formed to cover at least a part of each of the small holes. The corner where the through hole to be cut and the punching line of the mold intersect, that is, the intersection It shows how to set the angles to appropriate values. As a result, the intersecting angle of the small holes provided on the left and right sides of the large hole is adjusted, which prevents the pattern, that is, the plating layer, from peeling off when punching the through hole (large hole). However, as printed wiring boards are becoming increasingly finer due to the recent demand for high-density packaging, the pattern spacing tends to become narrower. 3
Providing two holes is not suitable for miniaturization and high density, and is an undesirable method. In addition, uncut portions of the glass cloth and copper foil in the base material of the printed wiring board protrude from the overlapping portion of the large hole and the small hole in the shape of whiskers, and through-hole plating is also formed on these protruding whiskers, so through-hole plating is performed. There is a drawback that it requires an extra step of 4♀ to remove the beard that protrudes from the front.

本発明はプリント配線基板の外周側壁に導電回路を形成
した基板を製造することを目的とし、前記従来技術の欠
点を解消するとともに安価かつ高収率の方法を提供する
ものである。
The object of the present invention is to manufacture a printed wiring board having a conductive circuit formed on its outer peripheral side wall, and to solve the drawbacks of the prior art and provide an inexpensive and high-yield method.

以下本発明のプリント配線基板の製造方法を図面に基づ
いて具体的に説明する、 第3図はプリント配線用基板に穴を明けた状態を示す斜
視図であり、該穴(5)は製品の外周となる部分すなわ
ち実線上の外形線部の穴の一部がかかるように穿孔した
穴であり、最終製品において基板側壁面の導体部になる
。第3図において、(4)はプリント配線用基材であり
、この基材としてはガラスエポキシ樹脂基板、紙フエノ
ール樹脂基板、紙エポキシ樹脂基板、ポリイミド樹脂基
板、及びトリアジン樹脂基板などがあり、これら基材の
片面又は両面には予め銅箔等の導電皮膜が積層接着され
ているものであってもよい。
The method for manufacturing a printed wiring board of the present invention will be explained in detail below based on the drawings. Fig. 3 is a perspective view showing a state in which a hole is made in the printed wiring board, and the hole (5) is a hole in the product. This hole is drilled so as to cover a part of the hole on the outer circumference, that is, on the solid line, and will become a conductor on the side wall surface of the board in the final product. In Fig. 3, (4) is a substrate for printed wiring, and examples of this substrate include glass epoxy resin substrates, paper phenol resin substrates, paper epoxy resin substrates, polyimide resin substrates, and triazine resin substrates. A conductive film such as copper foil may be laminated and adhered to one or both surfaces of the base material in advance.

次に前記のような穴を明けた基板の少くとも穴の壁面を
含む基板全面に7般的に知られた手段により無電解メッ
キのための触媒を付与する。
Next, a catalyst for electroless plating is applied to the entire surface of the substrate having holes as described above, including at least the wall surfaces of the holes, by a generally known method.

次いで無電解メッキのための触媒を付与した前記基板の
製品外周部分にかかる穴の一部を含む基板を切断除去し
基板の外形の側壁面に穴壁面を露出させる。
Next, the substrate including a portion of the hole extending over the product outer peripheral portion of the substrate coated with a catalyst for electroless plating is cut and removed to expose the hole wall surface on the side wall surface of the outer shape of the substrate.

第4図は基板の外形線に沿って製品部以外を除去した状
態の斜視図であり、この図において、(6)は壁面に無
電解メッキのための触媒を付与した穴であり、外形の側
壁面に穴の壁面が露出した状態を示すものである。第5
図は基板の外形線に沿って基板の一部を溝状に除去した
状態を示す斜視図であり、最終製品の導体部に相当する
触媒を付与した穴周辺の一部を除去することにより溝部
(8)を形成したものである、この図において、製品予
定部(9)は橋絡部(10)Kよって外周部のプリント
配線用基板(7)に支持されている。第5図のように製
品予定部(9)が橋絡部(10)により外周部のプリン
ト配線用基板(7)に支持されていることにより、これ
以後の工程において大型のプリント配線用基板の状態で
の該基板の取り扱いが可能なため作業性が著しく簡便と
なる利点がある。前記穴周辺部の基板を除去する方法と
しては、金型による打ち抜き又はルータ−・エンドミル
等による切削加工や、レーザー加工による方法などがあ
るが特に限定されるものではない。第6図は、第4図及
び第5図の穴周辺部を拡大した斜視図であり穴(6)に
は無電解メッキのための触媒が付与されている。しかし
、穴と穴との間の外形の側壁面(11)には触媒が付与
さ力2ていないため、以後の無電解メッキの工程におい
て外形の側壁面(11)には金属層が析出せず、穴と穴
との間は、電気的に絶縁化された状態と々る。前記の穴
周辺部の基板を除去する工程においては無電解メッキの
ための触媒が穴の壁面から脱落することはない、 次に穴周辺部を除去した基板を無電解メッキ液に浸漬し
少くとも穴壁面を含む基板表面に無電解メッキにより金
属を析出する。無電解メッキとしては特に限定されるも
のではないが、好しくは銅メッキ、ニッケルメッキなど
がよい。また、スルホールの信頼性をより向上させるた
めに、さらに電気メッキを施してもよい。
Figure 4 is a perspective view of the board with parts other than the product part removed along the outline. In this figure, (6) is a hole in which a catalyst for electroless plating is applied to the wall, and This shows a state in which the wall surface of the hole is exposed on the side wall surface. Fifth
The figure is a perspective view showing a state in which a part of the board has been removed in the form of a groove along the outline of the board. In this figure, the intended product part (9) is supported by the printed wiring board (7) at the outer periphery by the bridge part (10)K. As shown in Fig. 5, the planned product part (9) is supported by the printed wiring board (7) on the outer periphery by the bridge part (10), so that in the subsequent process, a large printed wiring board can be used. Since the substrate can be handled in this state, the workability is significantly simplified. Methods for removing the substrate around the hole include punching with a mold, cutting with a router/end mill, etc., and laser processing, but are not particularly limited. FIG. 6 is an enlarged perspective view of the vicinity of the hole in FIGS. 4 and 5, and the hole (6) is provided with a catalyst for electroless plating. However, since the catalyst is not applied to the side wall surface (11) of the outer shape between the holes, a metal layer is not deposited on the side wall surface (11) of the outer shape in the subsequent electroless plating process. First, the space between the holes remains electrically insulated. In the step of removing the substrate around the hole, the catalyst for electroless plating does not fall off the wall of the hole.Next, the substrate from which the area around the hole has been removed is immersed in an electroless plating solution. Metal is deposited on the substrate surface including the hole wall surface by electroless plating. The electroless plating is not particularly limited, but copper plating, nickel plating, etc. are preferable. Moreover, in order to further improve the reliability of the through holes, electroplating may be further applied.

次にスルホールメッキを施した後の該基板表面に感光性
樹脂被膜を施し、露光、現仰等の公知の手段によりネガ
パターンを形成する。第7図はネガパターンを形成した
状態を示す斜視図であり、この図[おいて(12)は感
光性樹脂被膜であシ(13)は外形の側壁面の導体部を
示し、(14)は基板上面(7) 回路パターンである
。さらに、スルホールメッキ層とは異なる金14メッキ
、例えばハンダ、スズ。
Next, a photosensitive resin film is applied to the surface of the substrate after through-hole plating, and a negative pattern is formed by known means such as exposure and exposure. FIG. 7 is a perspective view showing a state in which a negative pattern has been formed. is the circuit pattern on the top surface (7) of the board. Furthermore, gold-14 plating different from the through-hole plating layer, such as solder and tin.

金などのメッキにエリ、第7図における穴(13)及び
回路(14)に金属層を施し、該穴を含む回路を形成し
た後に前記感光性樹脂被膜を取り除き、前記異金属をエ
ツチングレジストとしてエツチングを行い所望の導電回
路を形成する。
A metal layer is applied to the hole (13) and the circuit (14) in FIG. 7 by plating with gold or the like, and after forming a circuit including the hole, the photosensitive resin film is removed and the foreign metal is used as an etching resist. Etching is performed to form the desired conductive circuit.

外形の側壁面に導体を形成する別の方法としては、プリ
ント配線用基板に穴明けをした後、無電解メッキのため
の触媒を伺与し基板表向に感光性樹脂被膜を施しポジパ
ターンを形成する。この場合側面導体部に相当する穴は
感光性樹脂被膜で完全に慎tている。第8図はこの状態
の基板断面因を示すものである。この図において(15
)は感光性樹脂膜であり、(16)は銅箔等の導電被膜
である。
Another method of forming a conductor on the side wall surface of the external shape is to drill holes in the printed wiring board, apply a catalyst for electroless plating, and apply a photosensitive resin film to the surface of the board to form a positive pattern. Form. In this case, the holes corresponding to the side conductor portions are completely covered with a photosensitive resin coating. FIG. 8 shows the cause of the cross section of the substrate in this state. In this figure (15
) is a photosensitive resin film, and (16) is a conductive film such as copper foil.

次いでエツチングにより回路パターンを形成する。Next, a circuit pattern is formed by etching.

この際、穴の壁面の無電解メッキ用触媒は感光性&j脂
被被膜より完全に覆われているためエツチング液が浸入
せず、従ってエツチングはされない。
At this time, since the electroless plating catalyst on the wall surface of the hole is completely covered by the photosensitive resin film, the etching solution does not penetrate, and therefore, no etching occurs.

次に穴周辺部の基板の一部を取り除き、外形の側壁面に
触媒が付与された穴壁面ff:露出させ、その後該基板
を無電解メッキ液中に浸漬し、少くとも穴壁面を含む基
板表面に無電解メッキにより金属を析出させ、基板の側
面の導体部を有する所望の回路パターンを形成する。該
基板にさらに電気メッキに行う方法としては、第9図に
示すように基板(7)の橋絡部(lのの表面に電気メツ
キ用のリード引き出し線としての回路パターン(17)
を設け、このリード引き出し線は製品部のパターンと短
絡させるためのリード線としての回路パターン(18)
と連結させることにより、リード引き出し線(17) 
’e通して全てのパターン及び穴の側壁面の導体部への
電気メッキが可能である。電気メツキ後に短絡用のリー
ド線(18)はエツチングやザグリ加工等により切離さ
れて製品部の回路パターン間は絶縁状態となる。
Next, a part of the substrate around the hole is removed to expose the hole wall surface ff to which the catalyst has been applied to the outer side wall surface, and then the substrate is immersed in an electroless plating solution, and the substrate including at least the hole wall surface is exposed. Metal is deposited on the surface by electroless plating to form a desired circuit pattern including conductor portions on the side surfaces of the substrate. As a method of further electroplating the board, as shown in FIG.
This lead wire is a circuit pattern (18) as a lead wire for shorting with the pattern of the product part.
By connecting with the lead lead wire (17)
Electroplating of the conductor parts on the side walls of all patterns and holes is possible through 'e. After electroplating, the shorting lead wire (18) is separated by etching, counterboring, etc., and the circuit patterns of the product are insulated.

第10図は本発明の製造方法により外形の側壁面に導体
を形成したプリント配線基板の斜視図の一例である。こ
の図において、(20)は側面の導体部である。
FIG. 10 is an example of a perspective view of a printed wiring board in which a conductor is formed on the outer side wall surface by the manufacturing method of the present invention. In this figure, (20) is a conductor portion on the side surface.

以上本発明の製造方法によれば、プリント配線用基板の
穴に無電解メッキ用の触媒を付与した後に穴の一部を切
断除去し、その後にスルホールメッキを行うことにより
外形の側壁面に良好な導体を選択的に形成することがで
き、従来法にふ・けるスルホールの切断の際にスルホー
ルメッキ層のハガレやカエリが発生する欠点′ff解消
し、プリント配線基板の歩留りを著しく向上させること
ができる。
As described above, according to the manufacturing method of the present invention, after applying a catalyst for electroless plating to the holes of a printed wiring board, a part of the holes is cut and removed, and then through-hole plating is performed, so that the side wall surface of the external shape is improved. This method eliminates the disadvantage of peeling and burring of the through-hole plating layer when cutting through-holes in conventional methods, and significantly improves the yield of printed wiring boards. I can do it.

【図面の簡単な説明】[Brief explanation of drawings]

第1図及び第2図は従来のプリント配線基板の斜視図で
あり、第3図から第7図及び第10図は本発明によるプ
リント配線基板の斜視図、第8図は同基板の縦断面図、
第9図は同基板の平面図である。 (1)・・・・・・・・・・ プリント配線基板(2)
・・・・・・・・・・側面導体部(3)・・・・・・・
・・切り込み (4)・・・・・・・・・・プリント配線用基板(5)
・・・・・・・・・・・穴 (6)・・・・・・・・・・壁面に無電解メッキ用触媒
を付与した穴(7)・・・・・・・・・・・プリント配
線用基板(8)・・・・・・・−・・・・溝部 (9)・・・・・・・・・・・・製品部(10)・・・
・・・・・・橋絡部 (11)・・・・・・・・外形の側壁面(絶縁層)(1
2)・・・・・・・・感光性樹脂被膜(13)・・・・
・・・・・側面の導体部(14)・・・・・・・・回路
パターン(15)・・・・・・・・感光性樹脂膜(16
)・・・・・・・・導電皮膜 (19) ・・・・・・・・・基板上の回路パターン(
20)−・・・・・・・・側面の導体層特許出願人 イビデン株式会社 代表者多賀潤一部
1 and 2 are perspective views of a conventional printed wiring board, FIGS. 3 to 7, and 10 are perspective views of a printed wiring board according to the present invention, and FIG. 8 is a longitudinal section of the same board. figure,
FIG. 9 is a plan view of the same substrate. (1)・・・・・・・・・ Printed wiring board (2)
......Side conductor part (3)...
...Notch (4) ...... Printed wiring board (5)
・・・・・・・・・・・・ Hole (6)・・・・・・・・・ Hole with electroless plating catalyst applied to the wall (7)・・・・・・・・・・・・Printed wiring board (8)...Groove section (9)...Product section (10)...
...Bridging part (11) ...... Side wall surface of external shape (insulating layer) (1
2)...Photosensitive resin coating (13)...
......Side conductor part (14)...Circuit pattern (15)...Photosensitive resin film (16)
)......Conductive film (19)......Circuit pattern on the board (
20) - ・・・・・・・・・・・・・・・・・・・・・・Patent applicant Jun Taga, representative of IBIDEN Co., Ltd.

Claims (1)

【特許請求の範囲】[Claims] 1o プリント配線用基板の所望の位置に、一部が製品
外周となる部分にかかるような穴を含む穴を明け、次い
で少くとも前記穴の壁面と該プリント配線基板表面とに
無電解メッキのための触媒を付与した後、前記の穴を含
むプリント配線用基板の製品外周の一部を除去し、プリ
ント配線用基板の外形の側壁面に前記穴の壁面の一部を
露出させ、次いで少くとも触媒を付与した穴の壁面とプ
リント配線基板表面とに無電解メッキを析出させること
によってプリント配線用基板の外周にかかる穴の壁面に
選択的に導体を形成することを特徴とするプリント配線
基板の製造方法。
1o Drill a hole in a desired position of the printed wiring board, including a hole that partially covers the outer periphery of the product, and then apply electroless plating to at least the wall of the hole and the surface of the printed wiring board. After applying the catalyst, a part of the product outer periphery of the printed wiring board including the hole is removed to expose a part of the wall surface of the hole on the side wall surface of the outer shape of the printed wiring board, and then at least A printed wiring board characterized in that a conductor is selectively formed on the wall surface of a hole extending around the outer periphery of a printed wiring board by depositing electroless plating on the wall surface of the hole provided with a catalyst and on the surface of the printed wiring board. Production method.
JP522584A 1984-01-13 1984-01-13 Method of producing printed circuit board Granted JPS60149195A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP522584A JPS60149195A (en) 1984-01-13 1984-01-13 Method of producing printed circuit board

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP522584A JPS60149195A (en) 1984-01-13 1984-01-13 Method of producing printed circuit board

Publications (2)

Publication Number Publication Date
JPS60149195A true JPS60149195A (en) 1985-08-06
JPH0336319B2 JPH0336319B2 (en) 1991-05-31

Family

ID=11605245

Family Applications (1)

Application Number Title Priority Date Filing Date
JP522584A Granted JPS60149195A (en) 1984-01-13 1984-01-13 Method of producing printed circuit board

Country Status (1)

Country Link
JP (1) JPS60149195A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62169493A (en) * 1986-01-22 1987-07-25 株式会社日立製作所 Manufacture of printed wiring board
JPS62189791A (en) * 1986-02-15 1987-08-19 株式会社日立製作所 Wiring board
JP2011134681A (en) * 2009-12-25 2011-07-07 Panasonic Electric Works Co Ltd Male type connector block, female type connector block and connector

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5715495A (en) * 1980-07-01 1982-01-26 Matsushita Electric Ind Co Ltd Method of producing printed circuit board
JPS5766696A (en) * 1980-10-13 1982-04-22 Kanto Kasei Kogyo Method of producing printed circuit board

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5715495A (en) * 1980-07-01 1982-01-26 Matsushita Electric Ind Co Ltd Method of producing printed circuit board
JPS5766696A (en) * 1980-10-13 1982-04-22 Kanto Kasei Kogyo Method of producing printed circuit board

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62169493A (en) * 1986-01-22 1987-07-25 株式会社日立製作所 Manufacture of printed wiring board
JPS62189791A (en) * 1986-02-15 1987-08-19 株式会社日立製作所 Wiring board
JP2011134681A (en) * 2009-12-25 2011-07-07 Panasonic Electric Works Co Ltd Male type connector block, female type connector block and connector

Also Published As

Publication number Publication date
JPH0336319B2 (en) 1991-05-31

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