JPH0563941B2 - - Google Patents
Info
- Publication number
- JPH0563941B2 JPH0563941B2 JP9174134A JP7413491A JPH0563941B2 JP H0563941 B2 JPH0563941 B2 JP H0563941B2 JP 9174134 A JP9174134 A JP 9174134A JP 7413491 A JP7413491 A JP 7413491A JP H0563941 B2 JPH0563941 B2 JP H0563941B2
- Authority
- JP
- Japan
- Prior art keywords
- process diagram
- forming
- plating layer
- circuit
- hole
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W90/00—Package configurations
- H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
- H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
- H10W90/754—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked insulating package substrate, interposer or RDL
Landscapes
- Structure Of Printed Boards (AREA)
Description
【0019】 実施例 ３
本例は、実施例２の製造方法において、回路パ
ターン及び導体回路の形成工程（図６、図７）
を、変えた例である。これを、図９〜図１１を用
いて説明する。
即ち、上記実施例２の回路パターン形成工程
（図６）において、図９に示すごとく、感光性樹
脂層４５によりネガテイプパターンを形成し、ハ
ンダ、ニツケル、錫、金などの異金属メツキ（図
示略）により、回路パターンを作る。そして、該
異金属メツキをエツチングレジストとして、図１
０に示すごとく、エツチングにより所望の導体回
路９６を形成する。
その後は、図１１に示すごとく、凹部９１のス
ルーホールメツキ層１の表面に金メツキ層２を被
覆する。
上記のごとく、本例によれば、実施例２と同様
の効果を得ることができる。Example 3 This example describes the process of forming circuit patterns and conductor circuits (FIGS. 6 and 7) in the manufacturing method of Example 2.
This is an example of changing . This will be explained using FIGS. 9 to 11. That is, in the circuit pattern forming step (FIG. 6) of Example 2, a negative tape pattern is formed using the photosensitive resin layer 45 as shown in FIG. ) to create a circuit pattern. Then, using the different metal plating as an etching resist, as shown in FIG.
0, a desired conductive circuit 96 is formed by etching. Thereafter, as shown in FIG. 11, the surface of the through-hole plating layer 1 in the recess 91 is coated with the gold plating layer 2. As described above, according to this example, the same effects as in Example 2 can be obtained.
【図１】実施例１におけるプリント配線基板の断
面図。FIG. 1 is a cross-sectional view of a printed wiring board in Example 1.
【図２】実施例１におけるプリント配線基板に電
子部品を搭載した状態の断面図。FIG. 2 is a cross-sectional view of a state in which electronic components are mounted on a printed wiring board in Example 1.
【図３】実施例２の製造方法における有機系樹脂
基板の断面図。FIG. 3 is a cross-sectional view of an organic resin substrate in the manufacturing method of Example 2.
【図４】実施例２におけるザグリ加工工程図。FIG. 4 is a counterbore machining process diagram in Example 2.
【図５】実施例２におけるスルーホールメツキ層
形成工程図。FIG. 5 is a process diagram for forming a through-hole plating layer in Example 2.
【図６】実施例２における回路パターン形成工程
図。FIG. 6 is a circuit pattern forming process diagram in Example 2.
【図７】実施例２における導体回路形成工程図。FIG. 7 is a process diagram for forming a conductor circuit in Example 2.
【図８】実施例２における金メツキ層形成工程
図。FIG. 8 is a process diagram for forming a gold plating layer in Example 2.
【図９】実施例３におけるネガテイブパターン形
成工程図。FIG. 9 is a negative pattern forming process diagram in Example 3.
【図10】実施例３における導体回路形成工程図。FIG. 10 is a process diagram for forming a conductor circuit in Example 3.
【図11】実施例３における金メツキ層形成工程
図。FIG. 11 is a process diagram for forming a gold plating layer in Example 3.
【図12】ザグリ加工した凹部及びスルーホールの
断面説明図。[Fig. 12] Cross-sectional explanatory diagram of a counterbored recess and through hole.
１…スルーホールメツキ層、 １０…プリント配線基板、 ２…金メツキ層、 ５…電子部品、 ５１…ボンデイングワイヤー、 ９０…有機系樹脂基板、 ９１…凹部、 ９１５…垂直壁面、 ９２…スルーホール、 ９３…繊維、 ９６…導体回路。 1...Through hole plating layer, 10...Printed wiring board, 2...Gold plating layer, 5...Electronic parts, 51...bonding wire, 90...Organic resin substrate, 91... recess, 915...Vertical wall surface, 92...Through hole, 93...Fiber, 96...Conductor circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3074134A JPH0555401A (en) | 1982-10-12 | 1991-03-13 | Printed wiring board |
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP57178663A JPS5967686A (en) | 1982-10-12 | 1982-10-12 | Printed circuit board and method of producing same |
| JP3074134A JPH0555401A (en) | 1982-10-12 | 1991-03-13 | Printed wiring board |
Related Parent Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP57178663A Division JPS5967686A (en) | 1982-10-12 | 1982-10-12 | Printed circuit board and method of producing same |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH0555401A JPH0555401A (en) | 1993-03-05 |
| JPH0563941B2 true JPH0563941B2 (en) | 1993-09-13 |
Family
ID=26415269
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP3074134A Granted JPH0555401A (en) | 1982-10-12 | 1991-03-13 | Printed wiring board |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0555401A (en) |
Families Citing this family (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6753638B2 (en) | 2000-02-03 | 2004-06-22 | Calient Networks, Inc. | Electrostatic actuator for micromechanical systems |
| US7728339B1 (en) | 2002-05-03 | 2010-06-01 | Calient Networks, Inc. | Boundary isolation for microelectromechanical devices |
| US7737368B2 (en) | 2005-09-30 | 2010-06-15 | Sanyo Electric Co., Ltd. | Circuit board and method of manufacturing circuit board |
| JP4562632B2 (en) * | 2005-09-30 | 2010-10-13 | 三洋電機株式会社 | Circuit board and circuit board manufacturing method |
-
1991
- 1991-03-13 JP JP3074134A patent/JPH0555401A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0555401A (en) | 1993-03-05 |
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