JPH05343608A - Hybrid integrated circuit device - Google Patents
Hybrid integrated circuit deviceInfo
- Publication number
- JPH05343608A JPH05343608A JP15223492A JP15223492A JPH05343608A JP H05343608 A JPH05343608 A JP H05343608A JP 15223492 A JP15223492 A JP 15223492A JP 15223492 A JP15223492 A JP 15223492A JP H05343608 A JPH05343608 A JP H05343608A
- Authority
- JP
- Japan
- Prior art keywords
- wiring board
- integrated circuit
- circuit device
- hybrid integrated
- wiring
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01078—Platinum [Pt]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/191—Disposition
- H01L2924/19101—Disposition of discrete passive components
- H01L2924/19105—Disposition of discrete passive components in a side-by-side arrangement on a common die mounting substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/191—Disposition
- H01L2924/19101—Disposition of discrete passive components
- H01L2924/19107—Disposition of discrete passive components off-chip wires
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/14—Structural association of two or more printed circuits
- H05K1/141—One or more single auxiliary printed circuits mounted on a main printed circuit, e.g. modules, adapters
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/22—Secondary treatment of printed circuits
- H05K3/28—Applying non-metallic protective coatings
Landscapes
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は混成集積回路装置に係わ
り、特に高密度、高集積化が可能な混成集積回路装置に
関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a hybrid integrated circuit device, and more particularly to a hybrid integrated circuit device capable of high density and high integration.
【０００２】[0002]
【従来の技術】混成集積回路装置（ハイブリッドＩＣ）
は、基本的には、配線基板に能動素子や受動素子等の電
子部品を搭載するとともに、前記電子部品の電極と配線
層とをワイヤで電気的に接続し、かつ前記配線基板にリ
ードを接続し、前記リードの外端を除く全体をパッケー
ジで封止することによって製造される。2. Description of the Related Art Hybrid integrated circuit device (hybrid IC)
Basically mounts electronic components such as active elements and passive elements on the wiring board, electrically connects the electrodes of the electronic component and the wiring layer with wires, and connects the leads to the wiring board. Then, the whole of the lead except the outer ends is sealed with a package.
【０００３】一方、混成集積回路装置においても、生産
性向上, ＩＣ自動実装向上の観点からリードフレームを
使用する技術が開発されている。たとえば、特開昭６１
−１０２６３号公報には、リードフレームを使用した構
造のハイブリッドＩＣについて開示されている。このハ
イブリッドＩＣは、リードフレームのランド部（支持
板）上に多層配線基板が固定された構造となっている。
また、このハイブリッドＩＣは、最上層の配線基板に設
けられたボンディングパッドと、リードとがワイヤで接
続される構造となっている。On the other hand, also in a hybrid integrated circuit device, a technique of using a lead frame has been developed from the viewpoint of improving productivity and improving IC automatic mounting. For example, JP-A-61
No. 10263 discloses a hybrid IC having a structure using a lead frame. This hybrid IC has a structure in which a multilayer wiring board is fixed on a land portion (support plate) of a lead frame.
Further, this hybrid IC has a structure in which the bonding pad provided on the uppermost wiring substrate is connected to the lead by a wire.
【０００４】一方、特開昭６０−１６０１３５号公報に
は、シリコンのマザーボード上に半導体素子を複数マウ
ントし、このマザーボードをリードフレームのタブ（ラ
ンド）上にのせて組み立てを行う例が開示されている。On the other hand, JP-A-60-160135 discloses an example in which a plurality of semiconductor elements are mounted on a silicon mother board and the mother boards are mounted on tabs (lands) of a lead frame for assembly. There is.
【０００５】他方、工業調査会発行「電子材料」１９９
１年４月号、Ｐ２２〜Ｐ２８には、ファインピッチＳＭ
Ｔの最新動向について記載されている。この文献には、
ＩＣ，ＬＳＩパッケージについては，現在０．４ｍｍピ
ッチ品までが実用されていること、従来のリードフレー
ムタイプ（フレーム厚０．１５ｍｍｔ前後）では，０．
３ｍｍピッチ（リード幅０．１５ｍｍ前後）程度が限界
となるであろうことが記載されている。On the other hand, "Electronic Materials" 199 issued by the Industrial Research Committee
Fine pitch SM in April 22nd, P22-P28
The latest trends of T are described. In this document,
Regarding IC and LSI packages, up to 0.4 mm pitch products are currently in practical use. In the conventional lead frame type (frame thickness around 0.15 mmt),
It is described that about 3 mm pitch (lead width of about 0.15 mm) will be the limit.
【０００６】[0006]
【発明が解決しようとする課題】表面実装（ＳＭＴ）の
進歩により、従来技術による混成集積回路装置における
配線基板への実装も高密度化の傾向にある。本発明者
は、リードフレームの一部に配線基板を固定して製造す
る混成集積回路装置において、前記配線基板をマザーボ
ードと考え、このマザーボード上にサブアッセンブリと
しての混成集積回路装置を搭載すれば、マザーボード領
域の有効利用が図れることを思いたち本発明をなした。Due to the progress of surface mounting (SMT), the density of mounting on a wiring board in a hybrid integrated circuit device according to the prior art tends to increase. In the hybrid integrated circuit device manufactured by fixing a wiring substrate to a part of a lead frame, the present inventor considers the wiring substrate as a mother board, and if the hybrid integrated circuit device as a sub-assembly is mounted on this mother board, The present invention was made with the intention that the motherboard area can be effectively used.
【０００７】本発明の目的は混成集積回路装置の高密度
・高集積化を図ることにある。本発明の前記ならびにそ
のほかの目的と新規な特徴は、本明細書の記述および添
付図面からあきらかになるであろう。An object of the present invention is to increase the density and integration of a hybrid integrated circuit device. The above and other objects and novel features of the present invention will be apparent from the description of the present specification and the accompanying drawings.
【０００８】[0008]
【課題を解決するための手段】本発明の混成集積回路装
置は、受動素子や能動素子を搭載したマザーボードとし
ての配線基板に混成集積回路装置からなるサブアッセン
ブリが搭載されている。また、前記配線基板の周縁には
複数のリードが取り付けられている。前記リードの外端
部を除く全体はレジンモールドによるパッケージで被わ
れている。また、前記サブアッセンブリは配線基板と、
この配線基板の主面に搭載された受動素子や能動素子
と、前記配線基板の周面を除き前記受動素子および能動
素子を被うレジンモールドによるパッケージとからなっ
ている。また、サブアッセンブリの配線基板の主面周縁
部分にはボンディングパッドが露出するようになってい
る。そして、前記ボンディングパッドと、前記リードが
取り付けられた配線基板の配線層とがワイヤで電気的に
接続されている構造となっている。In the hybrid integrated circuit device of the present invention, a sub-assembly including the hybrid integrated circuit device is mounted on a wiring board as a mother board on which passive elements and active elements are mounted. Further, a plurality of leads are attached to the periphery of the wiring board. The whole of the lead except the outer ends is covered with a resin mold package. Also, the sub-assembly is a wiring board,
It is composed of a passive element and an active element mounted on the main surface of the wiring board, and a resin mold package covering the passive element and the active element except the peripheral surface of the wiring board. Further, the bonding pad is exposed at the peripheral portion of the main surface of the wiring board of the sub-assembly. The bonding pad and the wiring layer of the wiring board to which the lead is attached are electrically connected by a wire.
【０００９】[0009]
【作用】上記した手段によれば、本発明の混成集積回路
装置は、マザーボードとしての配線基板に受動素子や能
動素子以外に受動素子や能動素子を封止してなる混成集
積回路装置からなるサブアッセンブリが搭載されている
ため、マザーボードとしての配線基板の搭載領域に高密
度実装が可能となり、配線基板の搭載領域が有効に使用
できる。また、前記サブアッセンブリはワイヤを用いて
マザーボードとしての配線基板の配線層に電気的に接続
される構造となっていることから、前記ボンディングパ
ッドのピッチを２００〜３００μｍ前後と狭くすること
ができるため、前記サブアッセンブリは多端子化あるい
は小型化できることになり、混成集積回路装置の高密度
化，高集積化が達成できる。According to the above-mentioned means, the hybrid integrated circuit device of the present invention comprises a sub integrated circuit device comprising a wiring board as a mother board, in which passive elements and active elements are sealed in addition to passive elements and active elements. Since the assembly is mounted, high-density mounting is possible in the mounting area of the wiring board as a mother board, and the mounting area of the wiring board can be used effectively. Moreover, since the sub-assembly has a structure in which it is electrically connected to the wiring layer of the wiring board as a mother board by using wires, the pitch of the bonding pads can be narrowed to around 200 to 300 μm. Since the sub-assembly can be multi-terminaled or miniaturized, high density and high integration of the hybrid integrated circuit device can be achieved.
【００１０】[0010]
【実施例】以下図面を参照して本発明の一実施例につい
て説明する。図１は本発明の一実施例による混成集積回
路装置の要部を示す斜視図、図２は同じく混成集積回路
装置の断面図、図３は同じくサブアッセンブリの断面
図、図４は本発明の混成集積回路装置の製造に用いるリ
ードフレームの平面図、図５は本発明の混成集積回路装
置の製造において配線基板の一面に電子部品を搭載した
状態を示す断面図、図６は同じくトランスファモールド
されたリードフレームを示す断面図である。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. 1 is a perspective view showing an essential part of a hybrid integrated circuit device according to an embodiment of the present invention, FIG. 2 is a sectional view of the hybrid integrated circuit device, FIG. 3 is a sectional view of a subassembly of the same, and FIG. 4 is a sectional view of the present invention. FIG. 5 is a plan view of a lead frame used for manufacturing the hybrid integrated circuit device, FIG. 5 is a cross-sectional view showing a state in which electronic parts are mounted on one surface of a wiring substrate in manufacturing the hybrid integrated circuit device of the present invention, and FIG. 6 is also transfer molded. It is a sectional view showing a lead frame.
【００１１】本発明の混成集積回路装置は図２に示すよ
うに、厚膜基板やプリント基板（ＰＣＢ，ＣＯＢ）等か
らなるマザーボードとなる配線基板１を有し、この配線
基板１の表裏面に受動素子や能動素子等からなる電子部
品が搭載されているが、混成集積回路装置からなるサブ
アッセンブリ２が搭載されていることが特徴である。図
では説明の便宜上各部品はそれぞれ１〜２点程度のみを
示してあるが、実際には多数である。前記配線基板１の
上面には、サブアッセンブリ２，チップ抵抗３，ＩＣ４
が搭載され、裏面には２つのサブアッセンブリ２とチッ
プ抵抗３が搭載されている。これらの電子部品は配線基
板１の表面に設けられた配線層（メタライズ層）５上に
図示しない接合材を介して固定されている。また、前記
配線基板１の周縁には面実装型のリード７が固定されて
いる。また、これらリード７や配線層５、さらには電子
部品と配線層５とはワイヤ９によって電気的に接続され
ている。また、図示はしないが、前記配線基板１におい
て、その表裏面の配線層５はスルーホールに充填された
導体を介して所定部が電気的に接続されている。また、
前記配線基板１の表裏面全体は、リード７の外端部を残
してトランスファモールドによるパッケージ８によって
被われている。As shown in FIG. 2, the hybrid integrated circuit device of the present invention has a wiring board 1 which is a mother board made of a thick film substrate, a printed circuit board (PCB, COB) or the like, and the wiring board 1 has front and back surfaces. Although electronic components such as passive elements and active elements are mounted, it is characterized in that the sub-assembly 2 including a hybrid integrated circuit device is mounted. In the figure, for convenience of explanation, each part is shown only with one or two points, but in reality, there are many parts. On the upper surface of the wiring board 1, the sub-assembly 2, the chip resistor 3, the IC 4
Is mounted, and two sub-assemblies 2 and chip resistors 3 are mounted on the back surface. These electronic components are fixed on a wiring layer (metallized layer) 5 provided on the surface of the wiring board 1 via a bonding material (not shown). A surface mount type lead 7 is fixed to the peripheral edge of the wiring board 1. The leads 7, the wiring layer 5, and further the electronic components and the wiring layer 5 are electrically connected by wires 9. Further, although not shown, in the wiring board 1, predetermined portions are electrically connected to the wiring layers 5 on the front and back surfaces of the wiring board 1 through the conductors filled in the through holes. Also,
The entire front and back surfaces of the wiring board 1 are covered with a package 8 formed by transfer molding except the outer ends of the leads 7.
【００１２】前記サブアッセンブリ２は、図３にも示す
ように厚膜基板やプリント基板（ＰＣＢ，ＣＯＢ）等か
らなる配線基板１０を基にして製造されている。すなわ
ち、配線基板１０の主面には配線層（メタライズ層）１
１が設けられているとともに、この配線層１１上には、
チップ抵抗１２やＩＣ１３が搭載されている。このサブ
アッセンブリ２においても、実際は多数の電子部品が搭
載されているが、図では受動素子，能動素子をそれぞれ
１つ示す。また、図において、電子部品を固定する接合
材については省略してある。As shown in FIG. 3, the sub-assembly 2 is manufactured on the basis of a wiring board 10 made of a thick film board, a printed board (PCB, COB) or the like. That is, the wiring layer (metallization layer) 1 is formed on the main surface of the wiring substrate 10.
1 is provided, and on the wiring layer 11,
A chip resistor 12 and an IC 13 are mounted. Although a large number of electronic components are actually mounted in this sub-assembly 2, one passive element and one active element are shown in the figure. Further, in the drawing, a bonding material for fixing the electronic component is omitted.
【００１３】前記ＩＣ１３の図示しない電極と配線層１
１はワイヤ１４で接続されている。また、前記配線基板
１０の主面周縁部分を除く主面は、トランスファモール
ドによって形成されたパッケージ１５によって被われて
いる。そして、このパッケージ１５で被われない配線基
板１０の主面周縁部分には、図１に示すように、配線層
１１で形成されたボンディングパッド１７が並んでい
る。このボンディングパッド１７は、ワイヤボンディン
グに必要最小限の幅となり、たとえば、８０〜１００μ
ｍ程度の幅となっている。また、ボンディングパッド１
７のピッチは２００〜３００μｍ以下と狭くできる。こ
れにより、サブアッセンブリ２における外部端子の狭ピ
ッチ化が可能となり、高集積・高密度化，外部端子の多
端子化（多ピン化），配線基板１０の小型化によるサブ
アッセンブリ２の小型化が達成できる。Electrodes (not shown) of the IC 13 and the wiring layer 1
1 are connected by a wire 14. The main surface of the wiring board 10 excluding the peripheral portion of the main surface is covered with a package 15 formed by transfer molding. Then, as shown in FIG. 1, bonding pads 17 formed of the wiring layer 11 are arranged in a peripheral portion of the main surface of the wiring substrate 10 which is not covered with the package 15. The bonding pad 17 has a minimum width necessary for wire bonding, and is, for example, 80 to 100 μm.
The width is about m. Also, the bonding pad 1
The pitch of 7 can be as narrow as 200 to 300 μm or less. As a result, the pitch of the external terminals in the sub-assembly 2 can be reduced, the integration and density can be increased, the number of external terminals can be increased (the number of pins can be increased), and the size of the wiring board 10 can be reduced to reduce the size of the sub-assembly 2. Can be achieved.
【００１４】つぎに、このような混成集積回路装置の製
造について説明する。この混成集積回路装置の製造にお
いては、図４に示すようなパターンのリードフレーム２
５が用意される。リードフレーム２５は、０．１ｍｍ〜
０．２５ｍｍの厚さのＦｅ−Ｎｉ系合金あるいはＣｕ合
金等からなる金属板をエッチングまたは精密プレスによ
ってパターニングすることによって形成される。リード
フレーム２５は複数の単位リードパターンを一方向に直
列に並べた形状となっている。単位リードパターンは、
一対の平行に延在する外枠２６と、この一対の外枠２６
を連結しかつ外枠２６に直交する方向に延在する一対の
内枠２７とによって形成される枠２８内に形成されてい
る。Next, the manufacture of such a hybrid integrated circuit device will be described. In manufacturing this hybrid integrated circuit device, the lead frame 2 having a pattern as shown in FIG.
5 is prepared. The lead frame 25 is 0.1 mm
It is formed by patterning a metal plate made of a Fe-Ni alloy or Cu alloy having a thickness of 0.25 mm by etching or precision pressing. The lead frame 25 has a shape in which a plurality of unit lead patterns are arranged in series in one direction. The unit read pattern is
A pair of outer frames 26 extending in parallel, and this pair of outer frames 26
And a pair of inner frames 27 extending in a direction orthogonal to the outer frame 26.
【００１５】一方、前記枠２８の各外枠２６および内枠
２７の内側からは、相互に平行となって枠２８の中央に
延在する複数のリード７が設けられている。このリード
７は、枠２８の四隅に張り出した支持片２９間に亘って
設けられた細いダム３０と交差するパターンとなってい
る。そして、このダム３０によって各リード７はその途
中を支持されている。前記ダム３０は後述するトランス
ファモールド時、溶けたレジンの流出を阻止するダムと
して作用する。また、このダム３０の内側の片持梁状の
リード部分をインナーリード３１と呼称し、外側の部分
をアウターリード３２と呼称している。前記インナーリ
ード３１の先端は、特に限定はされないが、一段階段状
に変形している。また、前記外枠２６には、図示しない
がガイド孔が設けられている。このガイド孔は、リード
フレーム２５の移送や位置決め等のガイドとして利用さ
れる。なお、前記リードフレーム２５は必要に応じて所
望個所にメッキが施される。On the other hand, a plurality of leads 7 extending parallel to each other and extending to the center of the frame 28 are provided from the inside of each outer frame 26 and inner frame 27 of the frame 28. The lead 7 has a pattern that intersects with a thin dam 30 provided between supporting pieces 29 protruding at four corners of the frame 28. Each lead 7 is supported by the dam 30 along the way. The dam 30 functions as a dam that prevents the melted resin from flowing out during transfer molding described later. Further, the cantilevered lead portion inside the dam 30 is referred to as an inner lead 31, and the outer portion is referred to as an outer lead 32. The tip of the inner lead 31 is not particularly limited, but is deformed in a step shape. Further, the outer frame 26 is provided with a guide hole (not shown). The guide hole is used as a guide for transferring and positioning the lead frame 25. Incidentally, the lead frame 25 is plated at a desired portion if necessary.
【００１６】混成集積回路装置の製造においては、前記
リードフレーム２５が用意された後、図４に示されるよ
うに、前記インナーリード３１の各先端がマザーボード
となる配線基板１の主面周縁部分に重なるようにして接
合材によって固定される。その後、図５に示されるよう
に、前記リードフレーム２５の裏側を上にして、前記配
線基板１の表面に電子部品が搭載される。この図では、
２つのサブアッセンブリ２と、１つのチップ抵抗３が配
線基板１の所定配線層５上に図示しない接合材を介して
固定される。また、サブアッセンブリ２のボンディング
パッド１７と配線基板１の配線層５がワイヤ９によって
電気的に接続される。なお、本発明ではサブアッセンブ
リ２を別作業として製造し、その後にサブアッセンブリ
２をマザーボードとなる配線基板１に搭載することか
ら、配線基板１おける配線領域の有効活用が図れる。In the manufacture of the hybrid integrated circuit device, after the lead frame 25 is prepared, the tips of the inner leads 31 are provided on the peripheral portion of the main surface of the wiring board 1 serving as a mother board, as shown in FIG. It is fixed by the bonding material so as to overlap. Thereafter, as shown in FIG. 5, electronic components are mounted on the surface of the wiring board 1 with the back side of the lead frame 25 facing upward. In this figure,
Two subassemblies 2 and one chip resistor 3 are fixed on a predetermined wiring layer 5 of the wiring board 1 via a bonding material (not shown). The bonding pad 17 of the subassembly 2 and the wiring layer 5 of the wiring board 1 are electrically connected by the wire 9. In the present invention, since the sub-assembly 2 is manufactured as a separate work and then the sub-assembly 2 is mounted on the wiring board 1 which is a mother board, the wiring area of the wiring board 1 can be effectively utilized.
【００１７】つぎに、図６に示されるように、前記リー
ドフレーム２５は再度裏返しにされた後、電子部品が搭
載されていないマザーボードとしての配線基板１の表面
に電子部品が搭載される。この図ではそれぞれ１つとな
るサブアッセンブリ２，チップ抵抗３，ＩＣ４が、配線
基板１の所定の配線層５上に図示しない接合材を介して
固定される。また、サブアッセンブリ２のボンディング
パッド１７やＩＣ４の電極が、配線基板１の配線層５に
ワイヤ９を介して電気的に接続される。Next, as shown in FIG. 6, after the lead frame 25 is turned inside out again, electronic components are mounted on the surface of the wiring board 1 as a mother board on which no electronic components are mounted. In this figure, one sub-assembly 2, a chip resistor 3, and an IC 4 are fixed to each other on a predetermined wiring layer 5 of the wiring board 1 via a bonding material (not shown). Further, the bonding pad 17 of the subassembly 2 and the electrode of the IC 4 are electrically connected to the wiring layer 5 of the wiring board 1 via the wire 9.
【００１８】つぎに、組立が終了したリードフレーム２
５は、トランスファモールド装置によって封止される。
モールドは配線基板１からインナーリード３１の先端部
分に亘って行われるため、図６に示されるように、各電
子部品はパッケージ８によって封止されることになる。
その後、不要リードフレーム部分の切断除去が行われる
とともに、リード成形が行われ、図２に示されるような
ガルウイング型の混成集積回路装置が製造される。Next, the assembled lead frame 2
5 is sealed by a transfer mold device.
Since the molding is performed from the wiring board 1 to the tip portions of the inner leads 31, each electronic component is sealed by the package 8 as shown in FIG.
Thereafter, the unnecessary lead frame portion is cut and removed, and lead molding is performed to manufacture a gull-wing type hybrid integrated circuit device as shown in FIG.
【００１９】[0019]
【発明の効果】（１）本発明の混成集積回路装置は、マ
ザーボードとなる配線基板の表面に混成集積回路装置か
らなるサブアッセンブリを搭載した構造となっているこ
とから、サブアッセンブリを搭載した配線基板の配線領
域の有効活用が計られるため高集積化が図られるという
効果が得られる。(1) Since the hybrid integrated circuit device of the present invention has a structure in which the sub-assembly composed of the hybrid integrated circuit device is mounted on the surface of the wiring board serving as the mother board, the wiring in which the sub-assembly is mounted is mounted. Since the wiring area of the substrate is effectively used, the effect of achieving high integration can be obtained.
【００２０】（２）上記（１）により、本発明の混成集
積回路装置はサブアッセンブリの搭載によってより高集
積・高密度化が達成できるという効果が得られる。(2) Due to the above (1), the hybrid integrated circuit device of the present invention has an effect that higher integration and higher density can be achieved by mounting the sub-assembly.
【００２１】（３）本発明の混成集積回路装置は、マザ
ーボードとなる配線基板の表面に混成集積回路装置から
なるサブアッセンブリを搭載した構造となっているとと
もに、前記サブアッセンブリはその外部端子がワイヤボ
ンディングによってマザーボードの導体層と接続される
構造となっている。したがって、サブアッセンブリのボ
ンディングパッドの狭ピッチ化が可能となり、サブアッ
センブリの配線基板の小型化が達成できるという効果が
得られる。(3) The hybrid integrated circuit device of the present invention has a structure in which a sub-assembly composed of the hybrid integrated circuit device is mounted on the surface of a wiring board serving as a mother board, and the sub-assembly has a wire whose external terminal is a wire. The structure is such that it is connected to the conductor layer of the motherboard by bonding. Therefore, the pitch of the bonding pads of the sub-assembly can be reduced, and the size of the wiring board of the sub-assembly can be reduced.
【００２２】（４）上記（３）により、本発明の混成集
積回路装置は搭載するサブアッセンブリの狭ピッチ化が
可能となることによって、サブアッセンブリの高密度・
高集積化が可能となるという効果が得られる。(4) According to the above (3), the pitch of the sub-assembly mounted in the hybrid integrated circuit device of the present invention can be reduced, so that the high density of the sub-assembly can be achieved.
The effect that high integration is possible is obtained.
【００２３】（５）本発明の混成集積回路装置は、マザ
ーボードにサブアッセンブリを搭載するが、サブアッセ
ンブリはレジンパッケージ構造となり、保持も容易かつ
確実であることから自動搭載も可能となり、他の電子部
品の自動搭載とも相俟って組立性も良好となるという効
果が得られる。(5) In the hybrid integrated circuit device of the present invention, the sub-assembly is mounted on the mother board. The sub-assembly has a resin package structure, and since it is easy and secure to hold, it can be automatically mounted. Combined with the automatic mounting of parts, the effect that the assemblability is good can be obtained.
【００２４】（６）上記（１）〜（５）により、本発明
によれば混成集積回路装置の高密度・高集積化，小型化
が達成できるという相乗効果が得られる。(6) By virtue of the above items (1) to (5), according to the present invention, there can be obtained a synergistic effect that the hybrid integrated circuit device can achieve high density, high integration and miniaturization.
【００２５】以上本発明者によってなされた発明を実施
例に基づき具体的に説明したが、本発明は上記実施例に
限定されるものではなく、その要旨を逸脱しない範囲で
種々変更可能であることはいうまでもない、たとえば、
前記実施例では、外部端子がワイヤによってマザーボー
ドとなる配線基板の配線層に接続される例を示したが、
サブアッセンブリの配線基板の裏面に外部端子を配列
し、マザーボードとなる配線基板の配線層にフェイスダ
ウンボンディングする構造であってもよい。この場合も
外部端子の狭ピッチ化が可能となる。また、フェイスダ
ウン用の外部端子となるサブアッセンブリの場合には、
ワイヤボンディングが不要となる。したがって、この場
合には、マザーボードとなる配線基板の一面にワイヤボ
ンディングを行わない電子部品のみを搭載し、その後に
配線基板を裏返して他の配線基板面に電子部品を搭載す
るようにすれば、下面側にワイヤが存在しないことか
ら、作業性が良くなる。Although the invention made by the present inventor has been specifically described based on the embodiments, the invention is not limited to the above embodiments, and various modifications can be made without departing from the scope of the invention. Needless to say, for example,
In the above-mentioned embodiment, the example in which the external terminal is connected to the wiring layer of the wiring board which becomes the mother board by the wire,
The structure may be such that external terminals are arranged on the back surface of the wiring board of the sub-assembly, and face down bonding is performed on the wiring layer of the wiring board serving as the mother board. Also in this case, the pitch of the external terminals can be narrowed. Also, in the case of a sub-assembly that becomes an external terminal for face down,
No wire bonding is required. Therefore, in this case, if only the electronic components that are not wire-bonded are mounted on one surface of the wiring board to be the motherboard, then the wiring board is turned over and the electronic components are mounted on the other wiring board surfaces, Since there is no wire on the lower surface side, workability is improved.
【００２６】以上の説明では主として本発明者によって
なされた発明をその背景となった利用分野であるリード
フレームを用いた混成集積回路装置の製造技術に適用し
た場合について説明したが、それに限定されるものでは
ない。本発明は少なくともマザーボードを用いる構造の
混成集積回路装置の製造技術には適用できる。In the above description, the case where the invention made by the present inventor is mainly applied to the manufacturing technology of the hybrid integrated circuit device using the lead frame, which is the field of application which is the background of the invention, has been described. Not a thing. INDUSTRIAL APPLICABILITY The present invention can be applied to at least a manufacturing technique of a hybrid integrated circuit device having a structure using a motherboard.
【図１】本発明の一実施例による混成集積回路装置の要
部を示す斜視図である。FIG. 1 is a perspective view showing a main part of a hybrid integrated circuit device according to an embodiment of the present invention.
【図２】本発明による混成集積回路装置の断面図であ
る。FIG. 2 is a cross-sectional view of a hybrid integrated circuit device according to the present invention.
【図３】本発明におけるサブアッセンブリの断面図であ
る。FIG. 3 is a sectional view of a subassembly according to the present invention.
【図４】本発明の混成集積回路装置の製造に用いるリー
ドフレームの平面図である。FIG. 4 is a plan view of a lead frame used for manufacturing the hybrid integrated circuit device of the present invention.
【図５】本発明の混成集積回路装置の製造において配線
基板の一面に電子部品を搭載した状態を示す断面図であ
る。FIG. 5 is a cross-sectional view showing a state in which electronic components are mounted on one surface of a wiring board in manufacturing the hybrid integrated circuit device of the present invention.
【図６】本発明の混成集積回路装置の製造におけるトラ
ンスファモールドされたリードフレームを示す断面図で
ある。FIG. 6 is a sectional view showing a transfer-molded lead frame in the manufacture of the hybrid integrated circuit device of the present invention.
１…配線基板、２…サブアッセンブリ、３…チップ抵
抗、４…ＩＣ、５…配線層、７…リード、９…ワイヤ、
１０…配線基板、１１…配線層、１２…チップ抵抗、１
３…ＩＣ、１４…ワイヤ、１５…パッケージ、１７…ボ
ンディングパッド、２５…リードフレーム、２６…外
枠、２７…内枠、２８…枠、２９…支持片、３０…ダ
ム、３１…インナーリード、３２…アウターリード。1 ... Wiring board, 2 ... Subassembly, 3 ... Chip resistance, 4 ... IC, 5 ... Wiring layer, 7 ... Lead, 9 ... Wire,
10 ... Wiring board, 11 ... Wiring layer, 12 ... Chip resistance, 1
3 ... IC, 14 ... Wire, 15 ... Package, 17 ... Bonding pad, 25 ... Lead frame, 26 ... Outer frame, 27 ... Inner frame, 28 ... Frame, 29 ... Supporting piece, 30 ... Dam, 31 ... Inner lead, 32 ... Outer lead.
───────────────────────────────────────────────────── フロントページの続き (72)発明者 赤澤 生朗 埼玉県入間郡毛呂山町大字旭台15番地 日 立東部セミコンダクタ株式会社内 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Ikuro Akazawa 15 Asahidai, Moroyama-cho, Iruma-gun, Saitama Nihon Tobu Semiconductor Co., Ltd.
Claims (1)
が固定された複数のリードと、前記配線基板に搭載され
た能動素子および受動素子とを有し、前記リードの外端
部を除く部分がパッケージによって封止されてなる混成
集積回路装置であって、前記配線基板には受動素子と能
動素子とが内蔵された混成集積回路装置からなるサブア
ッセンブリが搭載されてなることを特徴とする混成集積
回路装置。1. A wiring board, a plurality of leads whose inner ends are fixed to a peripheral edge of the wiring board, active elements and passive elements mounted on the wiring board, and outer ends of the leads. A hybrid integrated circuit device in which a portion other than the above is sealed by a package, wherein the wiring board is mounted with a subassembly including a hybrid integrated circuit device in which a passive element and an active element are incorporated. Hybrid integrated circuit device.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP15223492A JP3029736B2 (en) | 1992-06-11 | 1992-06-11 | Manufacturing method of hybrid integrated circuit device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP15223492A JP3029736B2 (en) | 1992-06-11 | 1992-06-11 | Manufacturing method of hybrid integrated circuit device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH05343608A true JPH05343608A (en) | 1993-12-24 |
| JP3029736B2 JP3029736B2 (en) | 2000-04-04 |
Family
ID=15536021
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP15223492A Expired - Lifetime JP3029736B2 (en) | 1992-06-11 | 1992-06-11 | Manufacturing method of hybrid integrated circuit device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP3029736B2 (en) |
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5527740A (en) * | 1994-06-28 | 1996-06-18 | Intel Corporation | Manufacturing dual sided wire bonded integrated circuit chip packages using offset wire bonds and support block cavities |
| US5677569A (en) * | 1994-10-27 | 1997-10-14 | Samsung Electronics Co., Ltd. | Semiconductor multi-package stack |
| US5780926A (en) * | 1996-02-17 | 1998-07-14 | Samsung Electronics Co., Ltd. | Multichip package device having a lead frame with stacked patterned metallization layers and insulation layers |
| JP2002343922A (en) * | 2001-05-18 | 2002-11-29 | Nec Kyushu Ltd | Method for manufacturing semiconductor device |
| JP2003100985A (en) * | 2001-09-26 | 2003-04-04 | Sanyo Electric Co Ltd | Circuit module |
| WO2005038917A1 (en) * | 2003-10-20 | 2005-04-28 | Genusion Inc. | Package structure and packaging method of semiconductor device |
| KR100708050B1 (en) * | 2002-02-20 | 2007-04-16 | 앰코 테크놀로지 코리아 주식회사 | semiconductor package |
-
1992
- 1992-06-11 JP JP15223492A patent/JP3029736B2/en not_active Expired - Lifetime
Cited By (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5527740A (en) * | 1994-06-28 | 1996-06-18 | Intel Corporation | Manufacturing dual sided wire bonded integrated circuit chip packages using offset wire bonds and support block cavities |
| US5545922A (en) * | 1994-06-28 | 1996-08-13 | Intel Corporation | Dual sided integrated circuit chip package with offset wire bonds and support block cavities |
| US5677569A (en) * | 1994-10-27 | 1997-10-14 | Samsung Electronics Co., Ltd. | Semiconductor multi-package stack |
| US5780926A (en) * | 1996-02-17 | 1998-07-14 | Samsung Electronics Co., Ltd. | Multichip package device having a lead frame with stacked patterned metallization layers and insulation layers |
| JP2002343922A (en) * | 2001-05-18 | 2002-11-29 | Nec Kyushu Ltd | Method for manufacturing semiconductor device |
| JP2003100985A (en) * | 2001-09-26 | 2003-04-04 | Sanyo Electric Co Ltd | Circuit module |
| KR100708050B1 (en) * | 2002-02-20 | 2007-04-16 | 앰코 테크놀로지 코리아 주식회사 | semiconductor package |
| WO2005038917A1 (en) * | 2003-10-20 | 2005-04-28 | Genusion Inc. | Package structure and packaging method of semiconductor device |
| US7723835B2 (en) | 2003-10-20 | 2010-05-25 | Genusion, Inc. | Semiconductor device package structure |
Also Published As
| Publication number | Publication date |
|---|---|
| JP3029736B2 (en) | 2000-04-04 |
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