JPS61125066A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPS61125066A JPS61125066A JP59246008A JP24600884A JPS61125066A JP S61125066 A JPS61125066 A JP S61125066A JP 59246008 A JP59246008 A JP 59246008A JP 24600884 A JP24600884 A JP 24600884A JP S61125066 A JPS61125066 A JP S61125066A
- Authority
- JP
- Japan
- Prior art keywords
- chip
- resistor
- substrate
- terminating resistor
- layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49866—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers characterised by the materials
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49866—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers characterised by the materials
- H01L23/49877—Carbon, e.g. fullerenes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
- H01L23/64—Impedance arrangements
- H01L23/647—Resistive arrangements
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
Landscapes
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Wire Bonding (AREA)
Abstract
Description
【発明の詳細な説明】
〔技術分野〕
本発明は半導体装置に関し、特に、ロジック（論理）Ｌ
、ＳＩ（高集積回路）チップの出力に必要な終端抵抗の
配置技術およびその抵抗体構成技術に関する。[Detailed Description of the Invention] [Technical Field] The present invention relates to a semiconductor device, and particularly to a logic L
, relates to a technique for arranging a termination resistor necessary for outputting an SI (highly integrated circuit) chip and a technique for configuring the resistor.
論理ＬＳＩチップを使ったマルチチップモジュールの製
法の一つに、いわゆるＣＣＢ （コンドロールド・コラ
ップス・リフローチップ）方式がある。One of the manufacturing methods for multi-chip modules using logic LSI chips is the so-called CCB (Condroded Collapse Reflow Chip) method.
これは、一般に、半導体素子（チップ）のポンディング
パッドにバンプ（突起電極）を取り付け。This generally involves attaching bumps (protruding electrodes) to the bonding pads of a semiconductor element (chip).
セルファラインの配線基板に接合する技術である。This is a technology for bonding to Selfaline's wiring board.
バンプは、一般に、５ｂ−ｒ＋ｂを用いて半球状にチッ
プに突設される。Bumps are generally provided on the chip in a hemispherical shape using 5b-r+b.
この接合技術は、従来から、一般に次のようにして行わ
れている。This joining technique has conventionally been generally performed as follows.
すなわち、ＬＳＩチップのにバンプと、基板に設けられ
た（ｉｔ号配線とを当該バンブ全屈を溶融させて接合す
る。その際、バンプと信号配線との接着性（半田付は性
）を良くするために、一般に。That is, the bumps on the LSI chip and the (IT) wiring provided on the board are bonded by melting the entire bend of the bumps.At this time, the adhesion (soldering) between the bumps and the signal wiring is made to be good. In order to, in general.
基板の１８号配線上に、順次、Ｃｒ−Ｃｕ−Ａｕより成
る重ね膜構造のｆ！！極を形成している。The f! ! forming a pole.
ところで、上記のごとく、論理Ｌｓ■チップ特にＥＣＬ
（エミッ久結合形論理回路）ＬＳ丁チップのマルチチ
ップ化を行う場合には、出力端子に必要な終端抵抗（一
般に５０Ωが使われる）の配置が問題となる。By the way, as mentioned above, the logic Ls■ chip especially the ECL
(Emitter-coupled logic circuit) When converting LS chips into multiple chips, the placement of the termination resistor (generally 50Ω is used) required for the output terminal becomes a problem.
この終端抵抗の配置につき、各種の様式が考えられる。Various styles can be considered for the arrangement of this terminating resistor.
これを第３図により説明する。尚第３図にて、１１はＬ
ＳＩチップ側を示し、１２は当該チップ内の回路素子（
１−ランジスタ）、１３は配線基板（マルチチップモジ
ュール基板）側を示し。This will be explained with reference to FIG. In Figure 3, 11 is L
The SI chip side is shown, and 12 indicates the circuit elements (
1-transistor), 13 indicates the wiring board (multi-chip module board) side.
１４は信号配線、１５は終端抵抗である。14 is a signal wiring, and 15 is a terminating resistor.
このような、チップ１１内からの信号を、バンプにより
接続された基板１３の（８号配線１４に出力する場合、
チップｉＩの外部に設ける終端抵抗１５の配置が問題と
なり、第一の考え方として従来から行われてきた方式は
、チップ１１と基板１３とをパッケージし、核パッケー
ジから引き出しされた出力ピンに終端抵抗を取り付ける
方式である。しかし、ＥＣＬｌｉＥｌ路では、１つの出
力ピンに対し１個の終端抵抗を取り付ける必要があり、
つまり、出力ピンの数に応じて終端抵抗を取り付けなけ
ればならないので、例えば出力ピンが１００ビンとする
と終＠抵抗を１００個取り付けなければならないという
都合がある。When such a signal from inside the chip 11 is output to the No. 8 wiring 14 of the board 13 connected by the bump,
The placement of the terminating resistor 15 provided outside the chip iI became a problem, and the first method that has been used in the past is to package the chip 11 and the substrate 13, and place the terminating resistor on the output pin drawn out from the core package. This is a method of attaching. However, in the ECLliEl path, it is necessary to install one terminating resistor for one output pin.
In other words, it is necessary to attach terminating resistors according to the number of output pins, so if there are 100 output pins, for example, 100 terminating resistors must be attached.
そこで、第二の考え方として、チップ内に終端抵抗を配
置することが考えられる。この場合、終端抵抗を配置す
るためのスペースをチップ内にとらなければならないの
で、チップ面積が増大するという欠点がある。しかも、
Ｊ４端抵抗の形式には。Therefore, a second idea is to place a terminating resistor within the chip. In this case, a space must be provided within the chip for arranging the terminating resistor, resulting in an increase in chip area. Moreover,
The format of the J4 terminal resistor is as follows.
チップ内の他の抵抗と同じ製法を用いることになるので
、チャツプ内に５ｏΩの抵抗を作るということは著しく
チップ面積の増大を招く。Since the same manufacturing method as other resistors in the chip is used, creating a 50Ω resistor in the chip significantly increases the chip area.
第三の考え方として、チップの外に１個別に作った抵抗
素子を並設するということも考えられるが、基板面積と
してチップ搭載面積プラス抵抗素Ｔの搭載面積というこ
とになり、基板面積が大となることを避けられない。A third way to think about it is to install a resistor element made separately outside the chip in parallel, but the board area would be the chip mounting area plus the mounting area of the resistor element T, which would require a large board area. It is inevitable that this will happen.
本発案は、かかる終端抵抗の形成に際し、チップ面積の
増大をおさえ、もとのチップ面積のままで実装可能とし
、個別の抵抗素子を特別に作ったすすることなどを必要
としないで５部品点数を少なくでき、しかも、マルチチ
ップ化に際し、集積度の向上を図ることのできる。終端
抵抗配置、形成技術を提供することにある６
本発明の前記ならびにそのほかの目的と新規な特徴は、
不明Ｊ！吉の記述および添付図面からあきらかになるの
であろう。The present invention suppresses the increase in chip area when forming such a termination resistor, allows it to be mounted using the original chip area, and eliminates the need for specially made individual resistor elements. The number of points can be reduced, and the degree of integration can be improved when multi-chip. 6. The above and other objects and novel features of the present invention are to provide a technology for arranging and forming a terminating resistor.
Unknown J! This will become clear from Yoshi's description and the attached drawings.
本願において開示される発明のうち代表的なものの概要
を荊単に説明すれば、下記のとおりである。A brief overview of typical inventions disclosed in this application is as follows.
すなわち、本発明では、前記ＣＣＢＣ武力おける電極つ
まりＣｒ−Ｃｕ−Ａｕより成る重ね膜構造の電極の構造
に着目し、かかる電極形成の際の当該Ｃｒ膜をバンブと
の接続部からさらに延在させて、基板上に形成させ、そ
の延在部を終端抵抗とすることにより、チップに終端抵
抗を形成するのではないからチップ面積の増大にはなら
ないし。That is, the present invention focuses on the structure of the electrode in the CCBC, that is, the layered film structure electrode made of Cr-Cu-Au, and extends the Cr film further from the connection part with the bump when forming the electrode. By forming the resistor on the substrate and using its extended portion as the terminating resistor, the chip area does not increase because the terminating resistor is not formed on the chip.
また、ディスクリートの抵抗素子を別に作り、チップに
併設するわけではないので、基板搭載面積の増大にもな
らず、基板上に終端抵抗があり、これは従来空きスペー
スとなっていたチップ裏面に形成すればよいので、チッ
プはもとの大きさのままにとどまり、かつ、従来の実装
方式を踏襲すればよいので、個別の抵抗素子を作る場合
などに比して部品点数も少なくでき、しかも実装面積を
拡大せずにマルチチップ化ができるので、集積度の向」
二に寄与することができる。In addition, since the discrete resistance elements are not made separately and attached to the chip, there is no increase in the mounting area on the board, and there is a termination resistor on the board, which is formed on the back of the chip, which was previously an empty space. This allows the chip to remain its original size, and the conventional mounting method can be followed, so the number of components can be reduced compared to the case where individual resistor elements are made, and the mounting process is much faster. Multi-chip configuration is possible without expanding the area, so it is possible to increase the degree of integration.
It can contribute to two things.
次に１本発明の実施例を図面に基づいて説明する。 Next, an embodiment of the present invention will be described based on the drawings.
第１図は本発明の実施例を示す半導体装置の断面図であ
る。第１図にて、ｌは半導体素子（チップ）で、このチ
ップ１は１例えばシリコン単結晶基板から成り１周知の
技術によってこのチップ内には多数の回路素子が形成さ
れ、１つの回路機能が与えられている。回路素子の具体
例は１例えばＭｏＳトラシジスタから成り、これらの回
路素子によって、例えば論理回路やメモリ回路の回路機
能が形成されている。FIG. 1 is a sectional view of a semiconductor device showing an embodiment of the present invention. In Fig. 1, l is a semiconductor element (chip), and this chip 1 is made of, for example, a silicon single crystal substrate.1 A large number of circuit elements are formed within this chip by well-known technology, and one circuit function is performed. It is given. A specific example of the circuit element is, for example, a MoS transistor, and these circuit elements form the circuit functions of, for example, a logic circuit or a memory circuit.
第１図にて、２は、当該チップ１に形成された半田バン
プで、このバンプ２は、バリヤ金属（Ｃｒ −Ｃｕ−Ａ
ｕ） ３を介して半球状に当該チップ１に突設されて
いる。In FIG. 1, 2 is a solder bump formed on the chip 1, and this bump 2 is a barrier metal (Cr-Cu-A
u) Hemispherically protrudes from the chip 1 through 3.
このバンプ２には、かかる半田バンブのほか。This bump 2 includes a solder bump as well.
フリップチップ方式で使われているような金属ボール例
えばＣｕボールなどでもよく、突起状に形成された接続
端子であればよい。A metal ball such as a Cu ball used in the flip-chip method may be used, and any connection terminal formed in a protrusion shape may be used.
第１図にて、４はＡｕ層、５はＣｕ層、６はＣｒ店で、
半田バンブ（半田ボール）２と配線基板７の信号配置ｌ
Ａ８との当該接続部９には、下から順次、ＣｒＭＩ６．
Ｃ層５およびＡ ｕ Ｗｊ４が形成されているほか、本
発明では、このＣｒ層６を当該接続部９からさらに、基
板７上に延在させ、当該延在部１０を終端抵抗としてい
る。In Figure 1, 4 is the Au layer, 5 is the Cu layer, and 6 is the Cr layer.
Signal arrangement l of solder bump (solder ball) 2 and wiring board 7
At the connection part 9 with A8, CrMI6.
In addition to the C layer 5 and A u Wj 4 being formed, in the present invention, this Cr layer 6 is further extended from the connecting portion 9 onto the substrate 7, and the extending portion 10 is used as a terminating resistor.
上記配線基板７は１例えばセラミック基板やプリント基
板により構成されている。The wiring board 7 is made of, for example, a ceramic board or a printed circuit board.
信号配線８は、周知の薄模形成技術などにより形成され
、Ｃｕ、Ａ９などの導電体膜により構成される。The signal wiring 8 is formed by a well-known thin pattern forming technique, and is made of a conductive film such as Cu or A9.
本発明の、信号配線８と半田バンブ２との接続に使用さ
れる電極（接続部）９やＣｒ膜より成る終端抵抗（延在
部）膜１０め形成は、例えば、当該金属を蒸着し、エツ
チングによりパターンを形成することにより行われる。In the present invention, the electrode (connection part) 9 used for connecting the signal wiring 8 and the solder bump 2 and the termination resistor (extension part) film 10 made of a Cr film can be formed by, for example, vapor-depositing the metal, This is done by forming a pattern by etching.
一般に、Ｃｒ−Ｃｕ−Ａｕより成る重ね膜構造を有する
ＣＣＢ方式による電極の形成は、これら金属を順次原着
し、これら金属膜を一括してエツチングしてパターニン
グを行うが１本発明では。Generally, when forming an electrode using the CCB method having a layered film structure of Cr--Cu--Au, these metals are sequentially deposited and patterned by etching these metal films all at once.
例えば、先ずＣｒを蒸着し、エツチングして、上記構造
に見合ったパターニングを行ない、次いで。For example, Cr is first deposited, etched, and patterned to match the above structure, and then.
Ｃｕ、Ａｕを同様に蒸着、エツチング、パターニングを
行なう。Cu and Au are similarly deposited, etched, and patterned.
Ｃｒの比抵抗は１７Ｘ１０−”Ω・ｍであるから、ＣＣ
Ｂ工程におけるＣｒ厚が１５００Ａ位であることを考え
ると、そのシート抵抗は約ｌΩ／口なので、ＥＣＬ回路
上必要される５０Ωの終端抵抗を確保でき、十分実用に
供し得る。Since the specific resistance of Cr is 17×10-”Ω・m, CC
Considering that the Cr thickness in step B is about 1500A, the sheet resistance is about 1Ω/gate, so the 50Ω termination resistance required for the ECL circuit can be secured, and it can be put to practical use.
第１図には、基板７上にチップｌを搭載する図を要部断
面図で示したので、当該基板上に当該チップをマルチに
搭載する図示が省略されているが。In FIG. 1, a main part sectional view is shown in which the chips l are mounted on the substrate 7, so illustration of the mounting of multiple chips on the substrate is omitted.
第２図に、基板７上にチップｌをマルチにマウントする
図を模式的に示した。尚第２図にて、２は半田バンブ、
１０は終端抵抗を示す。FIG. 2 schematically shows how multiple chips I are mounted on the substrate 7. In Figure 2, 2 is a solder bump,
10 indicates a terminating resistor.
第２図に示すように、終端抵抗１０は、基板７上のチッ
プと信号配線とを接続する各電極間の。As shown in FIG. 2, the terminating resistor 10 is provided between each electrode connecting the chip and the signal wiring on the substrate 7.
従来は使用されていなかったスペース内であって。In a space that was previously unused.
チップ１搭載エリア内に設けるとよい６〔効果〕 （１）本発明によれば、マルチチップ化を行うに。It is recommended to install it within the chip 1 mounting area 6 [Effect] (1) According to the present invention, multi-chip implementation is possible.
チップの大きさは何ら変更する必要がない。There is no need to change the size of the chip.
すなわち、例えば、第２図にて、終端抵抗１０をチップ
１内に設けるときは、その分チップ面積が大となってし
まう、一方、終端抵抗１０をチップのディスクリートな
抵抗素子として別に製造し、これをチップ１と並設する
ときには、基板面積を大にしてしまう。That is, for example, in FIG. 2, when the terminating resistor 10 is provided within the chip 1, the chip area increases accordingly.On the other hand, the terminating resistor 10 is manufactured separately as a discrete resistance element of the chip, When this is arranged in parallel with the chip 1, the substrate area becomes large.
本発明では第２図にも示すように、基板７上に終端抵抗
１０を形成するようにしたのでチップ面積に影響を与え
なくて済む。In the present invention, as shown in FIG. 2, the terminating resistor 10 is formed on the substrate 7, so that it does not have to affect the chip area.
しかも第２図に示すように、従来の基板上の空きスペー
スを利用してそこに終＠抵抗を形成することにより、も
ちろん、チップの大きさを変える必要がなく、チップ面
積の増大を図らなくても済む。Moreover, as shown in Figure 2, by forming the terminal resistor there using the empty space on the conventional board, there is of course no need to change the size of the chip, and there is no need to increase the chip area. I can get away with it.
（２）本発明によれば、 Ｃｒ −Ｃｕ−Δαよりなる
電極形成の際に、当該Ｃｒ層をこれらＣｕ。(2) According to the present invention, when forming an electrode made of Cr-Cu-Δα, the Cr layer is replaced with Cu.
Ａｕ膜より単に延在させ、当該延在部を終端抵抗として
利用すればよく、特別にディスクリートの □抵抗素
子を作らなくてもよく、従来のＣＣＢ方式を踏襲すれば
よいので部品数の低減にもなる。It is sufficient to simply extend from the Au film and use the extended part as a terminating resistor, and there is no need to create a special discrete □resistance element, and the conventional CCB method can be followed, reducing the number of components. It will also happen.
（３）仮に、ディスクリートの抵抗素子をチップに並設
するとすれば、高集積化がさまたげられるが、本発明で
は個別の素子を別製するわけでないし、また、本発明に
よればチップ内に終端抵抗を作る場合のごとくチップ面
積が増大しないので、チップをマルチにモジュール化す
る場合に集積度の向上が図られる。(3) If discrete resistance elements were to be arranged in parallel on a chip, high integration would be hindered, but in the present invention, individual elements are not manufactured separately, and according to the present invention, Since the chip area does not increase unlike when creating a terminating resistor, the degree of integration can be improved when making multiple chips into modules.
以上本発明者によってなされた発明を実施例にもとづき
具体的に説明したが１本発明は上記実施例にもとづき具
体的に説明したが、本発明は上記実施例に限定されるも
のではなく、その要旨を逸脱しない範囲で種々変更可能
であることはいうまでもない。The invention made by the present inventor has been specifically explained above based on Examples.1 Although the present invention has been specifically explained based on the above Examples, the present invention is not limited to the above Examples. It goes without saying that various changes can be made without departing from the gist.
例えば前記実施例では終端抵抗をＣ「膜により形成する
例を示したが、これら代えてＷ膜などの他の金属により
形成してもよい。For example, in the above embodiment, an example was shown in which the terminating resistor was formed of a C film, but it may be formed of another metal such as a W film instead.
以上の説明では主として本発明者によってなされた発明
をその背景となった利用分野である半導体装置の終端抵
抗配置、形成技術に適用した場合について説明したが、
そこに限定されるものではなく、例えば、各種電子部品
の終端低抗配置、形成技術などにも適用できる。The above explanation has mainly been about the case where the invention made by the present inventor is applied to the field of application, which is the background of the invention, which is the arrangement and formation technology of termination resistors of semiconductor devices.
The present invention is not limited thereto, and can be applied to, for example, low-resistance termination arrangement and formation techniques for various electronic components.
図面のｆｌｆｉ 、Ｑｔな説明 第１図は本発明の実施例を示す断面図。Flfi of drawings, Qt explanation FIG. 1 is a sectional view showing an embodiment of the present invention.
第２図は本発明におけるマルチチップモジュールの模式
図
第３図はチップと基板の信号配線との関係を示す回路図
である。FIG. 2 is a schematic diagram of a multi-chip module according to the present invention. FIG. 3 is a circuit diagram showing the relationship between chips and signal wiring on a substrate.
■・・・半導体素子（チップ）、２・・・突起状の金属
接続端子（半田バンブ）、３・・バリヤ金属、４・・・
Ａｕ層、５・・・Ｃｕ層、６・・・Ｃｒ暦、７・・・配
線基板。■...Semiconductor element (chip), 2...Protruding metal connection terminal (solder bump), 3...Barrier metal, 4...
Au layer, 5...Cu layer, 6...Cr layer, 7...wiring board.
８・・・７８号配線、９・・−電極（接続部）、１０・
・・絶縁抵抗、１１・・・ＬＳＩチップ側、１２・・・
回路素子（トランジスタ）、１３・・・配線基板側、１
４・・・信号配線、１５・・・終端抵抗
第 ２ 図
第 ３ 図8...No.78 wiring, 9...-electrode (connection part), 10...
...Insulation resistance, 11...LSI chip side, 12...
Circuit element (transistor), 13...wiring board side, 1
4...Signal wiring, 15...Terminal resistor Fig. 2 Fig. 3
Claims (1)
を信号配線を有する配線基板の当該信号配線と接合して
成る実装方式による半導体装置において、前記素子から
前記基板への信号の出力に際し必要な終端抵抗を、前記
基板上に形成し、かつ、当該抵抗を金属膜による抵抗体
により構成したことを特徴とする半導体装置。 ２、金属膜が、接続端子と信号配線との接着性を良くす
るために配線基板上に形成されたＣｒ−Ｃｕ−Ａｕより
成る重ね膜構造の電極を構成する当該Ｃｒ膜より成る、
特許請求の範囲第１項記載の装置。[Scope of Claims] 1. In a semiconductor device using a mounting method in which a terminal of a semiconductor element having a protruding metal connection terminal is joined to a signal wiring of a wiring board having signal wiring, the semiconductor device is provided with A semiconductor device, characterized in that a terminal resistor necessary for outputting a signal to the substrate is formed on the substrate, and the resistor is constituted by a resistor made of a metal film. 2. The metal film is made of the Cr film constituting an electrode with a layered film structure made of Cr-Cu-Au formed on the wiring board to improve the adhesion between the connection terminal and the signal wiring.
An apparatus according to claim 1.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59246008A JPS61125066A (en) | 1984-11-22 | 1984-11-22 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59246008A JPS61125066A (en) | 1984-11-22 | 1984-11-22 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS61125066A true JPS61125066A (en) | 1986-06-12 |
Family
ID=17142083
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP59246008A Pending JPS61125066A (en) | 1984-11-22 | 1984-11-22 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS61125066A (en) |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS63310139A (en) * | 1987-06-12 | 1988-12-19 | Hitachi Ltd | Semiconductor device and its manufacture |
| JP2007103816A (en) * | 2005-10-07 | 2007-04-19 | Nec Electronics Corp | Interconnect substrate and electronic circuit device |
| JP2007103840A (en) * | 2005-10-07 | 2007-04-19 | Nec Electronics Corp | Method of manufacturing electronic circuit device |
| CN1329981C (en) * | 2003-06-30 | 2007-08-01 | 夏普株式会社 | Semiconductor carrier film, and semiconductor device and liquid crystal module using the same |
| US8446004B2 (en) | 2004-06-04 | 2013-05-21 | Cree, Inc. | Power light emitting die package with reflecting lens and the method of making the same |
| US9923128B2 (en) | 2013-08-27 | 2018-03-20 | Lumens Co., Ltd. | Light emitting device package and backlight unit having the same |
-
1984
- 1984-11-22 JP JP59246008A patent/JPS61125066A/en active Pending
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS63310139A (en) * | 1987-06-12 | 1988-12-19 | Hitachi Ltd | Semiconductor device and its manufacture |
| CN1329981C (en) * | 2003-06-30 | 2007-08-01 | 夏普株式会社 | Semiconductor carrier film, and semiconductor device and liquid crystal module using the same |
| US8446004B2 (en) | 2004-06-04 | 2013-05-21 | Cree, Inc. | Power light emitting die package with reflecting lens and the method of making the same |
| US8932886B2 (en) | 2004-06-04 | 2015-01-13 | Cree, Inc. | Power light emitting die package with reflecting lens and the method of making the same |
| JP2007103816A (en) * | 2005-10-07 | 2007-04-19 | Nec Electronics Corp | Interconnect substrate and electronic circuit device |
| JP2007103840A (en) * | 2005-10-07 | 2007-04-19 | Nec Electronics Corp | Method of manufacturing electronic circuit device |
| US9923128B2 (en) | 2013-08-27 | 2018-03-20 | Lumens Co., Ltd. | Light emitting device package and backlight unit having the same |
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