JP2569617B2 - Integrated circuit device - Google Patents

Integrated circuit device

Info

Publication number
JP2569617B2
JP2569617B2 JP62276601A JP27660187A JP2569617B2 JP 2569617 B2 JP2569617 B2 JP 2569617B2 JP 62276601 A JP62276601 A JP 62276601A JP 27660187 A JP27660187 A JP 27660187A JP 2569617 B2 JP2569617 B2 JP 2569617B2
Authority
JP
Japan
Prior art keywords
integrated circuit
package
resistor
circuit device
terminal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP62276601A
Other languages
Japanese (ja)
Other versions
JPH01119047A (en
Inventor
弘行 三沢
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP62276601A priority Critical patent/JP2569617B2/en
Publication of JPH01119047A publication Critical patent/JPH01119047A/en
Application granted granted Critical
Publication of JP2569617B2 publication Critical patent/JP2569617B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554External layer
    • H01L2224/0555Shape
    • H01L2224/05552Shape in top view
    • H01L2224/05554Shape in top view being square
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491Disposition
    • H01L2224/4912Layout
    • H01L2224/49171Fan-out arrangements

Landscapes

  • Parts Printed On Printed Circuit Boards (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Description

【発明の詳細な説明】 [産業上の利用分野] 本発明は集積回路装置に関し、特に回路的に終端抵抗
を必要とする集積回路装置の抵抗素子による終端方法に
関する。
Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an integrated circuit device, and more particularly, to a method of terminating an integrated circuit device requiring a terminating resistor in a circuit by using a resistance element.

[従来の技術] 従来、この種の集積回路装置の入出力端子で抵抗によ
る終端が必要なものは、集積回路装置を実装する基板上
に集積回路装置とは独立した抵抗部品を設置し、これを
集積回路の入出力端子に配線により接続していた。
[Prior Art] Conventionally, for input / output terminals of this type of integrated circuit device requiring termination by a resistor, a resistor component independent of the integrated circuit device is installed on a substrate on which the integrated circuit device is mounted, Is connected to the input / output terminal of the integrated circuit by wiring.

かかる固別抵抗部品を接続する理由は、終端抵抗の抵
抗値自体を実装する基板上の伝送路のインピーダンスと
整合させる必要があり、そのため極めて高い精度の抵抗
値が必要なのに、現在のモノリシック集積回路の中にそ
の種の抵抗を取り込むことは、製造歩留りの低下を招
き、結果的に極めて高い代償を払うことになるためであ
る。
The reason for connecting such discrete resistance components is that it is necessary to match the resistance value of the terminating resistor itself with the impedance of the transmission line on the substrate on which it is mounted, and therefore extremely high precision resistance values are required. Incorporating such a resistor into the device causes a reduction in manufacturing yield, resulting in a very high price.

このため集積回路装置自体の終端抵抗を必要とする端
子は集積回路装置として無終端として構成されていた。
For this reason, the terminal that requires the terminating resistor of the integrated circuit device itself is configured as an unterminated terminal as the integrated circuit device.

[発明が解決しようとする問題点] 上述した従来の集積回路装置の抵抗終端が必要な入出
力端子は無終端状態となっているが、近年において集積
回路装置の高密度化が進んだ結果、装置を実装する基板
には大規模集積回路等が実装される他、コンデンサ等の
他の実装部品は年々少なくなって来ている。その中でこ
の種の終端抵抗が単独部品として残されており、このこ
とは実装基板上の実装密度を高めていく上で大きな妨げ
となっているという欠点がある。
[Problems to be Solved by the Invention] Although the input / output terminals of the above-described conventional integrated circuit device requiring resistor termination are in an unterminated state, in recent years, the density of integrated circuit devices has increased, A large-scale integrated circuit and the like are mounted on a substrate on which the device is mounted, and other mounted components such as capacitors are decreasing year by year. Among them, this kind of terminating resistor is left as a single component, which has a drawback that it is a great hindrance in increasing the mounting density on a mounting board.

一方、この種の抵抗がモノリシック集積回路チップ上
に、他の抵抗素子と同一に形成すると、上述のようにこ
の種の要求精度は極めて厳しいことから製造歩留りを低
下させ、結果的に製品原価が大幅に上ってしまうという
欠点を有する。
On the other hand, if this type of resistor is formed on a monolithic integrated circuit chip in the same manner as other resistive elements, the required accuracy of this type is extremely severe as described above, which lowers the manufacturing yield and consequently lowers the product cost. It has the disadvantage that it rises significantly.

[発明の従来技術に対する相違点] 上述したように従来の集積回路装置では、集積回路装
置内の抵抗終端が必要な入出力端子が無終端であるため
装置の実装基板上に終端抵抗を設置しなければならない
ことに対し、本発明は集積回路装置内に終端抵抗を予め
準備してあるため、装置の実装基板上には特に終端抵抗
を設置する必要がなく、装置の実装基板におけるより高
密度実装が実現可能になるという相違点を有している。
[Differences of the Invention from the Prior Art] As described above, in the conventional integrated circuit device, since the input / output terminals that require the resistive termination in the integrated circuit device are unterminated, a terminating resistor is installed on the mounting board of the device. On the other hand, in the present invention, since the terminating resistor is prepared in the integrated circuit device in advance, it is not necessary to particularly install the terminating resistor on the mounting board of the device. The difference is that implementation is feasible.

[問題点を解決するための手段] 本発明の要旨は、モノリシック集積回路チップと抵抗
素子とを1つのパッケージ基体に搭載した集積回路装置
であって、前記抵抗素子の一端は前記パッケージ基体内
の内部リードを介して終端電位が与えられる前記パッケ
ージ基体外の第一の外部リードに接続され、前記抵抗素
子の他端は、ボンディングワイヤーあるいは前記パッケ
ージ基体外の第二の外部リードを介して前記モノリシッ
ク集積回路チップ上のパッドと必要に応じて接続される
ことである。
[Means for Solving the Problems] The gist of the present invention is an integrated circuit device in which a monolithic integrated circuit chip and a resistance element are mounted on one package base, and one end of the resistance element is provided inside the package base. The other end of the resistance element is connected to a first external lead outside the package base to which a terminal potential is applied via an internal lead, and the other end of the resistive element is connected to the monolithic via a second external lead outside the package base. It is connected to pads on an integrated circuit chip as needed.

[実施例] 実施例1 第1図は本発明の一実施例のパッケージ内の部分拡大
平面図である。モノリシック集積回路チップ1(以下LS
Iチップという)上に配置されたパッド1AはECL入力用パ
ッドであり、パッド2AはECL出力用パッドであり、パッ
ド3AはLSIチップ1内部の出力終端電位供給用電源パッ
ドである。このLSIチップ1はパッケージ内に搭載され
ており、パッド1Aはパッケージの内部リード1Cへ、パッ
ド2Aはパッケージの内部リード2Cへ、パッド3Aはパッケ
ージの内部リード3CへTABリード1B,2B,3Bを介してそれ
ぞれ接続されている。本実施例においてはLSIチップ1
とTABリードで接続される内部リードのすぐ外側にパッ
ケージ層間絶縁膜3をはさみ、独立した内部リードを設
けている。第1図に示す内部リード1D,2D,3Dがそれに相
当する。この内部リード1D,2D,3Dは同じくパッケージ層
間絶縁膜3上に金属薄膜で形成された終端抵抗1E,2E,3E
の片端子にそれぞれ接続されており、これらの終端抵抗
1E,2E,3Eの他の片端子は配線6により共通接続されてい
る。
Embodiment 1 Embodiment 1 FIG. 1 is a partially enlarged plan view inside a package according to an embodiment of the present invention. Monolithic integrated circuit chip 1 (hereinafter LS)
The pad 1A disposed on the I chip) is an ECL input pad, the pad 2A is an ECL output pad, and the pad 3A is an output termination potential supply power supply pad inside the LSI chip 1. This LSI chip 1 is mounted in a package. Pad 1A is connected to internal lead 1C of the package, pad 2A is connected to internal lead 2C of the package, pad 3A is connected to internal lead 3C of the package, and TAB leads 1B, 2B, 3B are connected to internal lead 3C of the package. Connected to each other. In this embodiment, the LSI chip 1
The package interlayer insulating film 3 is interposed immediately outside the internal lead connected by the TAB lead to provide independent internal leads. The internal leads 1D, 2D, and 3D shown in FIG. 1 correspond thereto. The internal leads 1D, 2D, and 3D are terminating resistors 1E, 2E, and 3E similarly formed of a metal thin film on the package interlayer insulating film 3.
Are connected to one terminal of
The other terminals of 1E, 2E, 3E are commonly connected by wiring 6.

本パッケージは多層配線構成としており、内部リード
1Cは配線1Fに接続し、パッケージの外部リード1Gに接続
している。内部リード2Cは配線2Fに接続し、パッケージ
の外部リード2Gに接続している。内部リード3Cは配線3F
に接続し、パッケージの外部リード3Gに接続している。
また、LSIチップ1内部の出力終端電位は本集積回路装
置の出力終端電位と同一と想定しているので、配線6も
配線3Fに接続し、結果的に配線6はパッケージの外部リ
ード3Gに接続されている。
This package has a multi-layer wiring structure, and internal leads
1C is connected to the wiring 1F and to the external lead 1G of the package. The internal lead 2C is connected to the wiring 2F, and is connected to the external lead 2G of the package. Internal lead 3C is wiring 3F
To the external lead 3G of the package.
Since the output terminal potential inside the LSI chip 1 is assumed to be the same as the output terminal potential of the present integrated circuit device, the wiring 6 is also connected to the wiring 3F, and as a result, the wiring 6 is connected to the external lead 3G of the package. Have been.

ECL回路は出力1端子毎に通常50Ωの終端抵抗を設置
するが、集積回路装置などを実装する基板上における伝
送配線路の反射の問題から、実際には該当出力から最も
遠端の入力端子部において終端抵抗を設置することが多
い。よって本実施例においてもECL出力であるパッド2A
に対し終端抵抗は付加せず、ECL入力となるパッド1Aが
接続する内部リード1Cと内部リード1Dとの間をボンディ
ングワイヤ5で接続し、実装基板上で外部リード1Gへ接
続するECL出力の終端抵抗を入力端子部で付加してい
る。
The ECL circuit usually has a termination resistor of 50Ω for each output terminal. However, due to the reflection of the transmission wiring on the board on which the integrated circuit device is mounted, the input terminal section farthest from the corresponding output is actually used. In many cases, a terminal resistor is installed. Therefore, also in this embodiment, the pad 2A which is the ECL output
No termination resistor is added, the internal lead 1C and the internal lead 1D, which are connected to the pad 1A to be the ECL input, are connected with the bonding wire 5 and the ECL output terminal connected to the external lead 1G on the mounting board A resistor is added at the input terminal.

本実施例では直接LSIチップ上の1A,2A,3Aと接続する
パッケージの内部リード1C,2C,3Cのすぐ外側に、配線6
に片端子を共通接続する50Ωの終端抵抗1E,2E,3Eの各々
の他の片端子に接続する内部リード1D,2D,3Dを設けてお
り、終端抵抗の付加が必要な入出力端子にのみ内側の内
部リードと外側の内部リード間をボンディングワイヤに
より接続することにより、終端抵抗を付加することがで
きる。
In this embodiment, the wiring 6 is provided immediately outside the internal leads 1C, 2C, 3C of the package directly connected to 1A, 2A, 3A on the LSI chip.
The internal leads 1D, 2D, and 3D that are connected to each other terminal of each of the 50Ω terminating resistors 1E, 2E, and 3E that commonly connect one terminal are provided only for input / output terminals that require the addition of a terminating resistor. By connecting the inner inner lead and the outer inner lead with a bonding wire, a terminating resistor can be added.

この場合の終端抵抗はパッケージ本体上に金属薄膜で
形成したものであるが、ECL回路の終端抵抗に要求され
る精度は極めて高く、50Ω±1%もしくは±0.1%程度
である。この精度を初期形成時に達成することは極めて
困難であるため、この種のパッケージ上の金属薄膜抵抗
に対し、形成後要求精度を満たすべく、レーザ等による
トリミング加工を施して所望の終端抵抗値とする。
In this case, the terminating resistor is formed of a metal thin film on the package body, but the precision required for the terminating resistor of the ECL circuit is extremely high, about 50Ω ± 1% or ± 0.1%. Since it is extremely difficult to achieve this accuracy at the time of initial formation, the metal thin film resistor on this type of package is trimmed with a laser or the like to meet the required accuracy after formation, and the desired termination resistance value is obtained. I do.

実施例2 第2図は本発明の第2の実施例であるパッケージ内の
部分拡大平面図である。複数の同一集積回路装置は実装
基板に搭載された場合、第1の集積回路装置の一入力端
子部で終端抵抗の付加が必要な場合でも第2の集積回路
装置の同一箇所の入力端子部では終端抵抗が不要となる
場合が往々にしてある。第2図ではLSIチップ上のパッ
ドとは関係なく、パッケージ上に終端抵抗を有する例を
示している。パッケージ内に搭載されたLSIチップ7上
の4A,5A,6Aはそれぞれパッケージの内部リード4C,5C,6C
にボンディングワイヤ4B,5B,6Bにより接続されており、
内部リード4C,5C,6Cはそれぞれ配線4D,5D,6Dによりパッ
ケージの外部リード4E,5E,6Eに接続している。この場合
のパッド4A,5A,6AはすべてECL入力のパッドであるもの
とする。この場合のECL入力端子となる外部リード4E,5
E,6Eについてはすべて終端抵抗が付加されていないもの
となっている。
Embodiment 2 FIG. 2 is a partially enlarged plan view of the inside of a package according to a second embodiment of the present invention. When a plurality of the same integrated circuit devices are mounted on a mounting substrate, even if it is necessary to add a terminating resistor at one input terminal portion of the first integrated circuit device, the same input terminal portion of the second integrated circuit device may be used. It is often the case that terminating resistors are not needed. FIG. 2 shows an example in which a termination resistor is provided on a package irrespective of pads on an LSI chip. 4A, 5A and 6A on the LSI chip 7 mounted in the package are the internal leads 4C, 5C and 6C of the package, respectively.
Are connected by bonding wires 4B, 5B, 6B to
The internal leads 4C, 5C, 6C are connected to the external leads 4E, 5E, 6E of the package by wirings 4D, 5D, 6D, respectively. In this case, all of the pads 4A, 5A, and 6A are pads for ECL input. External leads 4E and 5 to be ECL input terminals in this case
For E and 6E, no terminating resistor is added.

本パッケージ内には金属薄膜で形成された終端抵抗10
が設けられている。この終端抵抗10の片端子は配線7Cに
より引き出され、配線7Dを通じてパッケージの外部リー
ド7Eに接続している。また終端抵抗10の他の片端子は配
線8Cにより引き出され、配線8Dを通じてパッケージの外
部リード8Eに接続している。この終端抵抗10も予め形成
された時点では所望の要求精度を満たさない約50Ωの抵
抗として形成されるが、レーザ等のトリミング処理によ
り、要求精度±1.0%もしくは±0.1%に設定している。
This package contains a terminal resistor 10 made of a thin metal film.
Is provided. One terminal of the terminating resistor 10 is drawn out by a wiring 7C and connected to an external lead 7E of the package through a wiring 7D. The other terminal of the terminating resistor 10 is drawn out by a wiring 8C and is connected to an external lead 8E of the package through a wiring 8D. The terminating resistor 10 is also formed as a resistor of about 50Ω which does not satisfy the required required accuracy when it is formed in advance. However, the required accuracy is set to ± 1.0% or ± 0.1% by a trimming process using a laser or the like.

ECL回路の場合、出力終端抵抗はその出力を有する集
積回路装置により、最も遠端にある負荷の入力端子部に
設けられることが多いことから、一集積回路装置として
は全ての入出力に対応する外部リード毎に高精度の抵抗
を用意しておく必要はなく、終端抵抗の付加が必要であ
る入力端子などの必要に応じ実装基板上の配線接続によ
り付加できれば良いものである。第2図において外部リ
ード4Eに終端抵抗10が必要である場合には、実装基板上
の配線により、外部リード4Eと外部リード8Eを接続し、
外部リード7Eを終端電位電源に接続すれば良い。
In the case of an ECL circuit, the output terminating resistor is often provided at the input terminal section of the load at the farthest end depending on the integrated circuit device having its output, so that one integrated circuit device corresponds to all inputs and outputs It is not necessary to prepare a high-precision resistor for each external lead, and it is only necessary that a terminal resistor can be added by wiring connection on a mounting substrate as needed, such as an input terminal that needs to be added. In FIG. 2, when the terminating resistor 10 is required for the external lead 4E, the external lead 4E and the external lead 8E are connected by wiring on the mounting board,
The external lead 7E may be connected to a terminal potential power supply.

[発明の効果] 以上説明したように本発明は単一のモノリシック集積
回路チップを搭載した集積回路装置において、集積回路
装置のパッケージ本体に回路終端用抵抗素子を形成して
おき、この回路終端用抵抗素子の片端子をパッケージの
第1の外部リードに、他の片端子をパッケージの第2の
外部リードに接続してあることから、集積回路装置を実
装する基板上から終端抵抗として供する単体抵抗部品を
除去でき、その結果、基板上の部品の実装密度が上が
り、装置の小型化を画ることができる効果を有する。
[Effect of the Invention] As described above, the present invention relates to an integrated circuit device equipped with a single monolithic integrated circuit chip, in which a circuit termination resistor element is formed in a package body of the integrated circuit device, and the circuit termination resistor is formed. Since one terminal of the resistance element is connected to the first external lead of the package and the other terminal is connected to the second external lead of the package, a single resistor serving as a terminating resistor from the substrate on which the integrated circuit device is mounted The components can be removed, and as a result, the mounting density of the components on the substrate is increased, and there is an effect that the size of the device can be reduced.

本発明の実施例ではECL回路用の50Ωの終端抵抗の場
合を論じたが、TTL回路のプルアップ抵抗等、他の終端
抵抗の場合に適用しても同様の効果が得られることは言
うまでもない。
In the embodiment of the present invention, the case of the terminating resistor of 50Ω for the ECL circuit is discussed, but it goes without saying that the same effect can be obtained even when applied to other terminating resistors such as a pull-up resistor of a TTL circuit. .

【図面の簡単な説明】[Brief description of the drawings]

第1図は本発明の第1の実施例を示すパッケージ内の部
分拡大平面図、第2図は本発明の第2の実施例であるパ
ッケージ内の部分拡大平面図である。 1,7……LSIチップ、 2,3,4,8,9……パッケージ層間絶縁膜、 5,4B,5B,6B……ボンディングワイヤ、 6,1F,2F,3F,7C,8C,4D,5D,6D,7D,8D……配線、 1A,2A,3A,4A,5A,6A……パッド、 1B,2B,3B……TABリード、 1C,2C,3C,1D,2D,3D,4C,5C,6C……内部リード、 10,1E,2E,3E……終端抵抗、 1G,2G,3G,4E,5E,6E,7E,8E……外部リード。
FIG. 1 is a partially enlarged plan view inside a package showing a first embodiment of the present invention, and FIG. 2 is a partially enlarged plan view inside a package which is a second embodiment of the present invention. 1,7 …… LSI chip, 2,3,4,8,9 …… Package interlayer insulating film, 5,4B, 5B, 6B …… Bonding wire, 6,1F, 2F, 3F, 7C, 8C, 4D, 5D, 6D, 7D, 8D …… Wiring, 1A, 2A, 3A, 4A, 5A, 6A …… Pad, 1B, 2B, 3B …… TAB lead, 1C, 2C, 3C, 1D, 2D, 3D, 4C, 5C, 6C …… Internal lead, 10,1E, 2E, 3E …… Terminal resistor, 1G, 2G, 3G, 4E, 5E, 6E, 7E, 8E …… External lead.

Claims (1)

(57)【特許請求の範囲】(57) [Claims] 【請求項1】モノリシック集積回路チップと抵抗素子と
を1つのパッケージ基体に搭載した集積回路装置であっ
て、前記抵抗素子の一端は前記パッケージ基体内の内部
リードを介して終端電位が与えられる前記パッケージ基
体外の第一の外部リードに接続され、前記抵抗素子の他
端は、ボンディングワイヤーあるいは前記パッケージ基
体外の第二の外部リードを介して前記モノリシック集積
回路チップ上のパッドと必要に応じて接続されることを
特徴とする集積回路装置
1. An integrated circuit device having a monolithic integrated circuit chip and a resistance element mounted on a single package base, wherein one end of the resistance element is supplied with a terminal potential via an internal lead in the package base. The other end of the resistive element is connected to a first external lead outside the package base, and the other end of the resistance element is connected to a pad on the monolithic integrated circuit chip via a bonding wire or a second external lead outside the package base, if necessary. Integrated circuit device connected
JP62276601A 1987-10-30 1987-10-30 Integrated circuit device Expired - Lifetime JP2569617B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62276601A JP2569617B2 (en) 1987-10-30 1987-10-30 Integrated circuit device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62276601A JP2569617B2 (en) 1987-10-30 1987-10-30 Integrated circuit device

Publications (2)

Publication Number Publication Date
JPH01119047A JPH01119047A (en) 1989-05-11
JP2569617B2 true JP2569617B2 (en) 1997-01-08

Family

ID=17571715

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62276601A Expired - Lifetime JP2569617B2 (en) 1987-10-30 1987-10-30 Integrated circuit device

Country Status (1)

Country Link
JP (1) JP2569617B2 (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2812358B2 (en) * 1996-03-18 1998-10-22 日本電気株式会社 LSI package and LSI package manufacturing method

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5815264A (en) * 1981-07-21 1983-01-28 Nec Corp Multichip package
JPS58109275U (en) * 1982-01-19 1983-07-25 株式会社リコー hybrid integrated circuit
JPS59182947U (en) * 1983-05-24 1984-12-06 ロ−ム株式会社 semiconductor equipment
JPS6284970U (en) * 1985-11-15 1987-05-30
JPS62122372U (en) * 1986-01-24 1987-08-03

Also Published As

Publication number Publication date
JPH01119047A (en) 1989-05-11

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