JPH0621348A - Semiconductor element - Google Patents
Semiconductor elementInfo
- Publication number
- JPH0621348A JPH0621348A JP17737191A JP17737191A JPH0621348A JP H0621348 A JPH0621348 A JP H0621348A JP 17737191 A JP17737191 A JP 17737191A JP 17737191 A JP17737191 A JP 17737191A JP H0621348 A JPH0621348 A JP H0621348A
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor element
- resistor
- film
- element chip
- circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Abstract
Description
【0001】[0001]
【産業上の利用分野】本発明は半導体素子に関し、特に
外付け部品として抵抗、コンデンサ等の受動素子が必要
とされる半導体素子に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor element, and more particularly to a semiconductor element that requires passive elements such as resistors and capacitors as external parts.
【0002】[0002]
【従来の技術】従来の半導体素子は半導体基板に不純物
を導入してダイオードやトランジスタ等の能動素子を構
成しているが、抵抗値の大きな抵抗や大容量のコンデン
サを形成するには所要の面積が必要とされるため、これ
ら受動素子を含む回路を実現することは困難であった。
このため、従来では図3に示すようなハイブリッド構造
として所要の回路を構成している。即ち、配線基板11
上に導体膜で回路パターン12を形成し、この回路パタ
ーン12上に半導体素子チップ1を搭載し、或いはチッ
プコンデンサ13を搭載し、ボンディングワイヤ14や
半田15により回路パターン12への電気接続を行って
いる。又、回路パターン12の一部に抵抗膜を形成する
ことで抵抗16を構成している。2. Description of the Related Art A conventional semiconductor element is an active element such as a diode or a transistor formed by introducing impurities into a semiconductor substrate. However, a required area is required to form a resistor having a large resistance value or a large-capacity capacitor. Therefore, it has been difficult to realize a circuit including these passive elements.
Therefore, conventionally, a required circuit is configured as a hybrid structure as shown in FIG. That is, the wiring board 11
The circuit pattern 12 is formed on the conductor film, the semiconductor element chip 1 is mounted on the circuit pattern 12, or the chip capacitor 13 is mounted, and electrical connection to the circuit pattern 12 is performed by the bonding wire 14 and the solder 15. ing. Further, the resistor 16 is formed by forming a resistive film on a part of the circuit pattern 12.
【0003】[0003]
【発明が解決しようとする課題】このような従来の構成
では、抵抗値の大きな抵抗や大容量のコンデンサ等の受
動素子を含む回路を構成する場合には必ずハイブリッド
構造にしなければならないため、半導体装置の全体構造
が複雑になるとともに外形が大きくなり、しかも高価に
なるという問題がある。本発明の目的は、素子チップ単
独で値の大きな受動素子を含む回路の構成が可能な半導
体素子を提供することにある。In such a conventional structure, when a circuit including passive elements such as a resistor having a large resistance value and a large-capacity capacitor is formed, a hybrid structure must be used. There is a problem that the entire structure of the device becomes complicated, the outer shape becomes large, and the cost becomes high. An object of the present invention is to provide a semiconductor element capable of forming a circuit including a passive element having a large value with an element chip alone.
【0004】[0004]
【課題を解決するための手段】本発明の半導体素子は、
半導体素子チップの裏面に絶縁膜、薄膜導体、薄膜抵抗
等を用いて受動素子を一体形成している。この受動素子
としては抵抗或いはコンデンサが構成される。The semiconductor device of the present invention comprises:
A passive element is integrally formed on the back surface of the semiconductor element chip by using an insulating film, a thin film conductor, a thin film resistor and the like. A resistor or a capacitor is configured as the passive element.
【0005】[0005]
【作用】本発明によれば、半導体素子チップの裏面に抵
抗やコンデンサ等の受動素子が一体に形成されるため、
受動素子を含む回路を半導体素子チップ単独で構成する
ことが可能となる。According to the present invention, since passive elements such as resistors and capacitors are integrally formed on the back surface of the semiconductor element chip,
It is possible to configure the circuit including the passive element by the semiconductor element chip alone.
【0006】[0006]
【実施例】次に、本発明について図面を参照して説明す
る。図1は本発明の第1実施例を示す断面図である。半
導体素子チップ1は半導体基板の表面側に所定の不純物
を拡散して素子を形成し、かつ表面上に形成した絶縁膜
や内部配線により所要の回路を構成している。そして、
その回路の一部にはボンディングパッド2を形成し、半
導体素子チップ1の表面に露出させている。一方、半導
体素子チップ1の裏面にはシリコン酸化膜等の絶縁膜3
を形成し、この絶縁膜3によって半導体基板とは絶縁さ
れた状態でタンタル薄膜によりタンタル抵抗5を形成
し、これらタンタル抵抗5を所要パターンに形成した回
路パターン4により相互に電気接続した構成としてい
る。DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described with reference to the drawings. FIG. 1 is a sectional view showing a first embodiment of the present invention. The semiconductor element chip 1 forms an element by diffusing predetermined impurities on the surface side of the semiconductor substrate, and forms a required circuit by an insulating film and internal wiring formed on the surface. And
A bonding pad 2 is formed on a part of the circuit and is exposed on the surface of the semiconductor element chip 1. On the other hand, an insulating film 3 such as a silicon oxide film is formed on the back surface of the semiconductor element chip 1.
Is formed, the tantalum resistor 5 is formed of a tantalum thin film in a state of being insulated from the semiconductor substrate by the insulating film 3, and these tantalum resistors 5 are electrically connected to each other by a circuit pattern 4 formed into a required pattern. .
【0007】この構成によれば、半導体素子チップ1の
裏面に抵抗が構成でき、この抵抗は半導体素子チップ1
の裏面の略全面積を使用することができるため、大きな
抵抗値の抵抗を構成することが容易となる。このため、
大抵抗値の抵抗を含む半導体回路を半導体素子チップ単
独で構成することができる。According to this structure, a resistor can be formed on the back surface of the semiconductor element chip 1, and this resistor is used.
Since it is possible to use substantially the entire area of the back surface of the device, it becomes easy to form a resistor having a large resistance value. For this reason,
A semiconductor circuit including a resistor having a large resistance value can be configured by a semiconductor element chip alone.
【0008】図2は本発明の第2実施例の断面図であ
る。この実施例は、第1実施例と同様に、半導体素子チ
ップ1の表面にボンディングパッド2を形成する一方、
半導体素子チップ1の裏面の絶縁膜3上にタンタル抵抗
5を形成し、更に回路パターン4と、誘電体膜6、及び
上部金属膜7を形成している。この構成では、回路パタ
ーン4或いはタンタル抵抗5と、誘電体膜6と、上部金
属膜7とでコンデンサが構成できるため、半導体素子チ
ップ1の裏面に大抵抗値の抵抗と大容量のコンデンサが
構成でき、これら受動素子を含む回路を半導体素子チッ
プ単独で構成することができる。FIG. 2 is a sectional view of a second embodiment of the present invention. In this embodiment, similar to the first embodiment, the bonding pad 2 is formed on the surface of the semiconductor element chip 1,
A tantalum resistor 5 is formed on the insulating film 3 on the back surface of the semiconductor element chip 1, and a circuit pattern 4, a dielectric film 6 and an upper metal film 7 are further formed. In this configuration, since the circuit pattern 4 or the tantalum resistor 5, the dielectric film 6, and the upper metal film 7 can form a capacitor, a resistor having a large resistance value and a capacitor having a large capacitance are formed on the back surface of the semiconductor element chip 1. Therefore, the circuit including these passive elements can be configured by the semiconductor element chip alone.
【0009】[0009]
【発明の効果】以上説明したように本発明は、半導体素
子チップの裏面に絶縁膜、薄膜抵抗、薄膜導体等により
大きな値の抵抗や大容量のコンデンサを一体形成するの
で、大抵抗及び大容量コンデンサの半導体素子への取込
みが可能となり、半導体素子チップ単独で所要の回路が
構成でき、半導体装置のハイブリッド化を不要とするこ
とができる。As described above, according to the present invention, since a large-value resistor or large-capacity capacitor is integrally formed on the back surface of a semiconductor element chip by an insulating film, a thin-film resistor, a thin-film conductor, etc. The capacitor can be incorporated into the semiconductor element, a required circuit can be configured by the semiconductor element chip alone, and it is not necessary to hybridize the semiconductor device.
【図1】本発明の第1実施例の断面図である。FIG. 1 is a sectional view of a first embodiment of the present invention.
【図2】本発明の第2実施例の断面図である。FIG. 2 is a sectional view of a second embodiment of the present invention.
【図2】従来のハイブリッド半導体装置の断面図であ
る。FIG. 2 is a cross-sectional view of a conventional hybrid semiconductor device.
1 半導体素子チップ 2 ボンディングパ
ッド 3 絶縁膜 4 回路パターン 5 タンタル抵抗 6 誘電体膜 7 上部金属膜1 Semiconductor Element Chip 2 Bonding Pad 3 Insulating Film 4 Circuit Pattern 5 Tantalum Resistor 6 Dielectric Film 7 Upper Metal Film
─────────────────────────────────────────────────────
─────────────────────────────────────────────────── ───
【手続補正書】[Procedure amendment]
【提出日】平成5年7月14日[Submission date] July 14, 1993
【手続補正1】[Procedure Amendment 1]
【補正対象書類名】明細書[Document name to be amended] Statement
【補正対象項目名】図面の簡単な説明[Name of item to be corrected] Brief description of the drawing
【補正方法】変更[Correction method] Change
【補正内容】[Correction content]
【図面の簡単な説明】[Brief description of drawings]
【図1】本発明の第1実施例の断面図である。FIG. 1 is a sectional view of a first embodiment of the present invention.
【図2】本発明の第2実施例の断面図である。 FIG. 2 is a sectional view of a second embodiment of the present invention.
【図3】 従来のハイブリッド半導体装置の断面図であ
る。 FIG. 3 is a cross-sectional view of a conventional hybrid semiconductor device.
【符号の説明】 1 半導体素子チップ 2 ボンディングパッド 3 絶縁膜 4 回路パターン 5 タンタル抵抗 6 誘電体膜 7 上部金属膜[Explanation of reference numerals] 1 semiconductor element chip 2 bonding pad 3 insulating film 4 circuit pattern 5 tantalum resistance 6 dielectric film 7 upper metal film
Claims (2)
膜、薄膜導体、薄膜抵抗等を用いて受動素子を一体形成
したことを特徴とする半導体素子。1. A semiconductor element in which a passive element is integrally formed by using an insulating film, a thin film conductor, a thin film resistor and the like formed on the back surface of a semiconductor element chip.
請求項1の半導体素子。2. The semiconductor device according to claim 1, wherein the passive device is a resistor or a capacitor.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP17737191A JPH0621348A (en) | 1991-06-22 | 1991-06-22 | Semiconductor element |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP17737191A JPH0621348A (en) | 1991-06-22 | 1991-06-22 | Semiconductor element |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH0621348A true JPH0621348A (en) | 1994-01-28 |
Family
ID=16029788
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP17737191A Pending JPH0621348A (en) | 1991-06-22 | 1991-06-22 | Semiconductor element |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH0621348A (en) |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100443954B1 (en) * | 2000-08-11 | 2004-08-11 | 가시오게산키 가부시키가이샤 | Semiconductor device |
JP2009524917A (en) * | 2006-03-06 | 2009-07-02 | インテル・コーポレーション | Chip-level integrated high-frequency passive device, manufacturing method thereof, and system including the same |
US7675210B2 (en) | 2005-03-11 | 2010-03-09 | Panasonic Corporation | Hydrodynamic bearing and method for manufacturing the same, and spindle motor and method for manufacturing the same |
-
1991
- 1991-06-22 JP JP17737191A patent/JPH0621348A/en active Pending
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100443954B1 (en) * | 2000-08-11 | 2004-08-11 | 가시오게산키 가부시키가이샤 | Semiconductor device |
US7675210B2 (en) | 2005-03-11 | 2010-03-09 | Panasonic Corporation | Hydrodynamic bearing and method for manufacturing the same, and spindle motor and method for manufacturing the same |
JP2009524917A (en) * | 2006-03-06 | 2009-07-02 | インテル・コーポレーション | Chip-level integrated high-frequency passive device, manufacturing method thereof, and system including the same |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
IE53663B1 (en) | Hybrid integrated circuit device | |
TW434747B (en) | Semiconductor device | |
EP1100096A4 (en) | Electronic device and manufacture thereof | |
US4714981A (en) | Cover for a semiconductor package | |
JPH0621348A (en) | Semiconductor element | |
JPH10321791A (en) | Operational amplifier | |
JPS6227544B2 (en) | ||
JPH0262069A (en) | Semiconductor device | |
JP2007335842A (en) | Chip type electronic component | |
JPH01286353A (en) | Hybrid integrated circuit | |
JPS61148859A (en) | Hybrid integrated circuit device and manufacture thereof | |
JP2529037Y2 (en) | Composite board structure | |
JPH012345A (en) | Semiconductor integrated circuit device | |
JP2569617B2 (en) | Integrated circuit device | |
JPH05211279A (en) | Hybrid integrated circuit | |
JPS5936922Y2 (en) | Hybrid integrated circuit device | |
JPS5923408Y2 (en) | Composite circuit components | |
JPH01283896A (en) | Hybrid integrated circuit | |
JPS6380543A (en) | Integrated circuit device | |
JPS63239970A (en) | Semiconductor device | |
JPH0563140A (en) | Structure of hybrid integrated circuit | |
JPS62119964A (en) | Composite circuit device | |
JPH0693489B2 (en) | Method for manufacturing transistor device | |
JPH0714668U (en) | Circuit board device | |
JPH01199441A (en) | Integrated circuit package |