JPS63239970A - Semiconductor device - Google Patents

Abstract

PURPOSE:To prevent noise voltages by shortening wiring distances and to make it possible to decrease the mounting man-hours of a smoothing capacitor, by arranging electrode metal layers, which are connected to a power source wiring and a grounding wiring, and laminated bodies, between which a dielectric material is provided, on an integrated circuit chip, on the surface of which the power source wiring and the grounding wiring are provided. CONSTITUTION:A power source wiring 13 and a grounding wiring 14 are provided on the surface of an integrated circuit chip 11. At least one electrode metal layer 17 is connected to the power source wiring 13 and arranged on the integrated circuit chip 11. At least one electrode metal layer 23 is connected to the grounding wiring 14 and faces the electrode metal layer 17 through a dielectric material 21. A capacitor, which comprises the electrode metal layers 17 and 23 and the dielectric material 21, is mounted on the integrated circuit chip 11. For example, the electrode metal layer 17 is connected to the power source wiring 13 in the chip by way of a connecting part 18. The electrode metal layer 23 is connected to the grounding wiring 14 in the chip through a connecting part 24, a metal layer 19 and a connecting part 20. They form laminated bodies, in which the polyimide resin film 21 is provided between the electrode metal layers 17 and 23. Thus the capacitor for the power source circuit is constituted.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor device suitable for use in electronic equipment requiring high-speed signal transmission.

[Conventional technology]

FIG. 3 is a sectional view showing an embodiment of a conventional semiconductor device. In the figure, 1 is an insulating substrate 5a.

5b, 5c, and 5d are conductive parts disposed on the insulator substrate 1; 3 is an integrated circuit chip mounted on the conductive part 5c and has front IT source wiring and ground wiring; 4) power wiring of the integrated circuit chip 3; A lead wire 6 connects the conductive portion 5b to the ground wiring of the integrated circuit chip 3 and the conductive portion 5d. Furthermore, 2 is a capacitor,
The -1 terminal of the capacitor is connected to the conductive part 5b, and the other terminal is grounded via the conductive part 5at-.

A conventional semiconductor device is constructed as described above, and the capacitor 2 functions as a smoothing capacitor for the power supply port path of the integrated circuit chip 3.

[Problem that the invention seeks to solve]

However, in the conventional L-connected semiconductor device described above, the power supply wiring of the integrated circuit chip 3 is formed on the surface, and the distance between the close conductor parts 5b and 5c is not zero even if it is the minimum. The length of the lead wire 4 that connects the power supply wiring of the circuit chip 3 and the capacitor 2 becomes long, and no matter how short it is formed, it is not possible to reduce the height of the integrated circuit chip 3 by even □. Next, there is a drawback that noise voltage is generated in the lead wire 4.

However, in addition to the integrated circuit chip 3, it is necessary to mount the same number of capacitors as the power supply wiring on the integrated circuit chip 3 on all boards, etc., so if there are a large number of power supply wiring, it will take more man-hours for mounting, and productivity will decrease. The problem is that it's bad.

[Elaborate means to solve problems]

In this invention, an electrode metal layer connected to the power supply wiring, an electrode metal layer connected to the ground wiring, and a dielectric material between these are formed on an integrated circuit chip having all power wiring and ground wiring on the surface. This is an arrangement in which a t-laminate is interposed.

[For production]

In the present invention, the laminate constitutes the entire smoothing capacitor of the power supply circuit of the integrated circuit chip.

〔Example〕

Embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a sectional view showing one embodiment of the present invention.

In the figure, 11 is an integrated circuit chip, 12 is a circuit formation surface on the integrated circuit chip, 13 is an intra-chip power supply wiring formed on the bottom of the Impm molding, and 14 is an intra-chip ground wiring formed within the circuit formation 12. . Reference numeral 15 indicates a polyimide resin film formed on the circuit forming surface 12, and reference numerals 16a and 16b indicate in-chip power supply wiring 13.
A through hole 17 is formed to expose a part of the in-chip ground wiring 14, 17 is an electrode metal layer formed on the polyimide resin film 15 including a portion of the through hole IBa, and 18 is a portion of the through hole 16a. 19 is a friend metal layer formed on the polyimide resin film 15 including the through hole 16b, and 20 is the connection portion of the electrode metal layer 1T connected to the in-chip power supply wiring 13. The connection part 21 of the metal layer 19 connected to the internal ground wiring 14 is L with a flat surface on the electrode metal layer 17.19.
Nine polyimide resin films are formed; 22 is a through hole formed on the polyimide resin film 21 to fully expose a part of the metal layer 19; 23 is a through hole 22 on the polyimide resin film 21; an electrode metal layer formed of 2
4 is a connecting portion of the electrode metal layer 23 connected to the metal layer 19 at the through hole 220 portion.

In this device, the electrode metal layer 17 is connected to the in-chip power supply wiring via the connection part 18 that is a part of the electrode metal layer 17,
The electrode metal layer 23 includes a connecting portion 24 and a metal layer 19. These are connected to the in-chip ground wiring 14 via the connecting portion 20! A laminate is produced in which a polyimide resin film 21, which is a dielectric material, is interposed between polar metal layers 17 and 23, thereby forming a capacitor 't-groove of a power supply circuit.

Next, another embodiment f of the present invention will be described using FIG. 2.

Note that in FIG. 2, the same or corresponding parts as in FIG.

In this embodiment, 30 is a polyimide resin film formed on the circuit forming surface 12, 31 is connected to the in-chip power supply wiring 1s13 and is disposed on the circuit forming surface 12, and has three electrode metal layers; is a 93-layer electrode gold IA layer connected to the in-chip ground wiring 14 and disposed facing the electrode metal layer with a polyimide resin film 30 interposed therebetween. In order to completely manufacture this groove structure, a polyimide resin film 30 is placed on the circuit forming surface 12 as shown in FIG. Electrode metal layer 32.
Polyimide resin film 30. Electrode metal) lt31r, sequentially stack ↓ j → and repeat until the electrode metals /431 and 32 each become a layer.

In this second embodiment, the laminate of the polyimide resin film 30 and the electrode metal layers 31 and 32 is formed on the circuit forming surface 1.
Inner lead bonding (ILB) region 2 is formed on one side excluding gold, for example, an area of 5 m 40,000, and the electrode metal layer 31, 32 is made of polyimide resin @ 4 squares on each side.
It is assumed that the film thickness of No. 30 is 5 μm. The capacitance t (
C) can be obtained using the following formula.

ε. S C hawk□晦ε.

ε, : relative dielectric constant, d: distance, S: area, ε, : g electric constant.

Here, g, = 8.852 x 10” (C/V
・m).

ε. =3.5. S=(4X10)m', dx5X10m
Therefore, the capacitance is C-4969F. Therefore, the integrated circuit chip 11 has a power supply smoothing capacitor of 496 pF mounted on the power supply circuit.

In addition, the length of the wiring from the internal power supply wiring 13 to the smoothing capacitor is less than 1 μm, which is less than one-fifth of the length of the case where all the smoothing capacitors are externally connected, and the noise generated in the power supply wiring is less than 1 μm. 'Voltage can be prevented. Further, since the polyimide resin finger film 30 has a heat resistance of 300 degrees Celsius or more, it can sufficiently withstand the high temperature of soldering when the integrated circuit chip 11 is soldered.

In this example, only one smoothing capacitor is provided corresponding to one power supply circuit, but if multiple power supply circuits are provided in an integrated circuit chip, it is also possible to mount all of the plurality of smoothing capacitors. It is.

〔Effect of the invention〕

As explained above, in the present invention, since the smoothing capacitor for the power supply is formed entirely on the circuit formation surface of the integrated circuit chip,
The wiring distance between the power supply circuit and the smoothing capacitor can be sufficiently shortened, which has the effect of preventing noise voltage. Furthermore, since the integrated circuit chip and the smoothing capacitor are integrally formed, the mounting of the integrated circuit chip also serves as the mounting of the smoothing capacitor at the same time, which has the effect of reducing the number of mounting steps.

[Brief explanation of the drawing]

FIG. 1 is a sectional view showing a first embodiment of the present invention, FIG. 2 is a Wr side view showing a second embodiment of the invention, and FIG. 3 is a sectional view showing an embodiment of the prior art. be. 11...Integrated circuit chip, 12...Circuit forming surface, 13...Source wiring inside the chip, 14...Grounding arrangement inside the chip, 15, 21, 30...Polyimide system Resin H116a, 16b, 22...e through hole k, 1
7,23,31.32-...electrode metal layer, 19...
・Metal layer, 18°20.24...Connection part.

Claims (1)

[Claims] an integrated circuit chip having a power supply wiring and a ground wiring on its surface; at least one electrode metal layer connected to the power supply wiring and disposed on the integrated circuit chip; and connected to the ground wiring and the electrode metal layer. What is claimed is: 1. A semiconductor device comprising at least one electrode metal layer that faces the electrode metal layer with a dielectric material interposed therebetween, and a capacitor made of the electrode metal layer and the dielectric material is mounted on the integrated circuit chip.