JPH0336791A - Multilayer circuit ceramic board - Google Patents

Multilayer circuit ceramic board

Info

Publication number
JPH0336791A
JPH0336791A JP17157289A JP17157289A JPH0336791A JP H0336791 A JPH0336791 A JP H0336791A JP 17157289 A JP17157289 A JP 17157289A JP 17157289 A JP17157289 A JP 17157289A JP H0336791 A JPH0336791 A JP H0336791A
Authority
JP
Japan
Prior art keywords
layers
power source
requiring
large current
meshlike
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP17157289A
Other versions
JP2664485B2 (en
Inventor
Taichi Kon
Yukiharu Ono
Toyoji Yasuda
Original Assignee
Nippon Telegr & Teleph Corp <Ntt>
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Telegr & Teleph Corp <Ntt> filed Critical Nippon Telegr & Teleph Corp <Ntt>
Priority to JP17157289A priority Critical patent/JP2664485B2/en
Publication of JPH0336791A publication Critical patent/JPH0336791A/en
Application granted granted Critical
Publication of JP2664485B2 publication Critical patent/JP2664485B2/en
Anticipated expiration legal-status Critical
Application status is Expired - Fee Related legal-status Critical

Links

Abstract

PURPOSE: To increase the density of viahole pitch and to decrease an electric resistance of a voltage supply layer by increasing the viahole pitch of a meshlike power source layer requiring a large current than that of a meshlike power source layer not requiring a large current.
CONSTITUTION: A plurality of meshlike power source layers E1, E2, E3, D4, D5 are disposed in division of layers in a laminated ceramic board 1. The layers E1, E2, E3 are disposed on the rear face side of the board 1, and used as power source layers requiring a large current. On the other hand, the layers D4, D5 are disposed on the front face side of the board 1, and used as power source layers not requiring a large current. They are connected to signal interconnections S or the layers D4, D5 or E1, E2, E3 through viaholes 2S, 2D, 2E. Here, the viahole pitch PE of the layers E1, E2, E3 is increased twice as large as that PD of the layers D4, D5.
COPYRIGHT: (C)1991,JPO&Japio
JP17157289A 1989-07-03 1989-07-03 Ceramic multilayer wiring board Expired - Fee Related JP2664485B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP17157289A JP2664485B2 (en) 1989-07-03 1989-07-03 Ceramic multilayer wiring board

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP17157289A JP2664485B2 (en) 1989-07-03 1989-07-03 Ceramic multilayer wiring board

Publications (2)

Publication Number Publication Date
JPH0336791A true JPH0336791A (en) 1991-02-18
JP2664485B2 JP2664485B2 (en) 1997-10-15

Family

ID=15925636

Family Applications (1)

Application Number Title Priority Date Filing Date
JP17157289A Expired - Fee Related JP2664485B2 (en) 1989-07-03 1989-07-03 Ceramic multilayer wiring board

Country Status (1)

Country Link
JP (1) JP2664485B2 (en)

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5828773A (en) * 1996-01-26 1998-10-27 Harris Corporation Fingerprint sensing method with finger position indication
US5862248A (en) * 1996-01-26 1999-01-19 Harris Corporation Integrated circuit device having an opening exposing the integrated circuit die and related methods
US5963679A (en) * 1996-01-26 1999-10-05 Harris Corporation Electric field fingerprint sensor apparatus and related methods
US6181807B1 (en) 1996-01-23 2001-01-30 Authentec, Inc. Methods and related apparatus for fingerprint indexing and searching
EP1137333A4 (en) * 1998-09-17 2004-03-24 Ibiden Co Ltd Multilayer build-up wiring board
JP2008305944A (en) * 2007-06-07 2008-12-18 Denso Corp Ceramic laminating wiring substrate
US10212805B2 (en) 2016-12-27 2019-02-19 Fujitsu Limited Printed circuit board and electric device

Cited By (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6181807B1 (en) 1996-01-23 2001-01-30 Authentec, Inc. Methods and related apparatus for fingerprint indexing and searching
US5828773A (en) * 1996-01-26 1998-10-27 Harris Corporation Fingerprint sensing method with finger position indication
US5862248A (en) * 1996-01-26 1999-01-19 Harris Corporation Integrated circuit device having an opening exposing the integrated circuit die and related methods
US5956415A (en) * 1996-01-26 1999-09-21 Harris Corporation Enhanced security fingerprint sensor package and related methods
US5963679A (en) * 1996-01-26 1999-10-05 Harris Corporation Electric field fingerprint sensor apparatus and related methods
EP1137333A4 (en) * 1998-09-17 2004-03-24 Ibiden Co Ltd Multilayer build-up wiring board
EP1868423A1 (en) * 1998-09-17 2007-12-19 Ibiden Co., Ltd. Multilayer build-up wiring board
JP2008305944A (en) * 2007-06-07 2008-12-18 Denso Corp Ceramic laminating wiring substrate
US10212805B2 (en) 2016-12-27 2019-02-19 Fujitsu Limited Printed circuit board and electric device

Also Published As

Publication number Publication date
JP2664485B2 (en) 1997-10-15

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Legal Events

Date Code Title Description
LAPS Cancellation because of no payment of annual fees