JP4646370B2 - Printed wiring board and printed wiring board manufacturing method - Google Patents

Description

【００５７】
（１２）レジスト５０を５％ＮａＯＨで剥離除去した後、そのレジスト５０下のＮｉ−Ｃｕ合金層４８を硝酸および硫酸と過酸化水素の混合液を用いるエッチングにて溶解除去し、Ｎｉ−Ｃｕ合金層４８と電解めっき膜５２からなる厚さ１６μｍのスルーホール５６及び導体回路５８（バイアホール６０を含む）を形成する。そして、基板を水洗いし、乾燥した後、エッチング液を基板の両面にスプレイで吹きつけて、スルーホール５６及び導体回路５８（バイアホール６０を含む）の表面をエッチングすることにより、スルーホール５６及び導体回路５８（バイアホール６０を含む）の全表面に粗化面６２を形成する（図４（Ａ））。エッチング液として、イミダゾール銅（ＩＩ）錯体１０重量部、グリコール酸７重量部、塩化カリウム５重量部およびイオン交換水７８重量部を混合したものを使用する。
【００５８】
（１３）エポキシ系樹脂を主成分とする樹脂充填剤６４を、スルーホール５６内に充填し、加熱乾燥を行う。（図４（Ｂ））。
【００５９】
（１４）その後、（６）の工程で用いた熱硬化型エポキシ系樹脂シートを温度５０〜１５０℃まで昇温しながら圧力５ｋｇ／ｃｍ²で真空圧着ラミネートし、層間樹脂絶縁層１４０を設ける（図４（Ｃ））。真空圧着時の真空度は、１０ｍｍＨｇである。ここでは、エポキシ系樹脂を用いるが、シクロオレフィン系樹脂フィルムを用いることも可能である。
【００６０】
（１５）次いで、層間樹脂絶縁層１４０にレーザによりバイアホール用開口１４２を形成する（図４（Ｄ））。
【００６１】
（１６）（９）の工程と同様に日本真空技術株式会社製のＳＶ−４５４０を用いてプラズマ処理を行い、層間樹脂絶縁層１４０の全表面に粗化面１４６を形成する（図５（Ａ））。酸あるいは酸化剤によって粗化処理を施してもよい。また、粗化層は、０．１〜５μｍが望ましい。
【００６２】
（１７）その後、（１０）〜（１２）の工程を繰り返すことにより、層間樹脂絶縁層１４０上に、Ｎｉ−Ｃｕ合金層１４８と電解めっき膜１５２からなる厚さ１６μｍの導体回路１５８（バイアホール１６０を含む）及び粗化面１６２を形成する（図５（Ｂ））。
【００６３】
（１８）次に、ジエチレングリコールジメチルエーテル（ＤＭＤＧ）に６０重量％の濃度になるように溶解させた、クレゾールノボラック型エポキシ樹脂（日本化薬社製）のエポキシ基５０％をアクリル化した感光性付与のオリゴマー（分子量４０００）４６．６７重量部、メチルエチルケトンに溶解させた８０重量％のビスフェノールＡ型エポキシ樹脂（油化シェル社製、商品名：エピコート１００１）１５重量部、イミダゾール硬化剤（四国化成社製、商品名：２Ｅ４ＭＺ−ＣＮ）１．６重量部、感光性モノマーである多官能アクリルモノマー（共栄化学社製、商品名：Ｒ６０４）３重量部、同じく多価アクリルモノマー（共栄化学社製、商品名：ＤＰＥ６Ａ）１．５重量部、分散系消泡剤（サンノプコ社製、商品名：Ｓ−６５）０．７１重量部を容器にとり、攪拌、混合して混合組成物を調整し、この混合組成物に対して光重量開始剤としてベンゾフェノン（関東化学社製）２．０重量部、光増感剤としてのミヒラーケトン（関東化学社製）０．２重量部を加えて、粘度を２５℃で２．０Ｐａ・ｓに調整したソルダーレジスト組成物（有機樹脂絶縁材料）を得る。
なお、粘度測定は、Ｂ型粘度計（東京計器社製、ＤＶＬ−Ｂ型）で６０ｒｐｍの場合はローターＮｏ.４、６ｒｐｍの場合はローターＮｏ.３によった。
【００６４】
（１９）次に、基板３０の両面に、上記ソルダーレジスト組成物を２０μｍの厚さで塗布し、７０℃で２０分間、７０℃で３０分間の条件で乾燥処理を行った後、ソルダーレジスト開口部のパターンが描画された厚さ５ｍｍのフォトマスクをソルダーレジスト層７０に密着させて１０００ｍＪ／ｃｍ²の紫外線で露光し、ＤＭＴＧ溶液で現像処理し、開口７１Ｕ、７１Ｄを形成する（図６（Ａ））。
【００６５】
（２０）次に、ソルダーレジスト層（有機樹脂絶縁層）７０を形成した基板を、塩化ニッケル（２．３×１０^-1ｍｏｌ／ｌ）、次亞リン酸ナトリウム（２．８×１０^-1ｍｏｌ／ｌ）、クエン酸ナトリウム（１．６×１０^-1ｍｏｌ／ｌ）を含むｐＨ＝４．５の無電解ニッケルめっき液に２０分間浸漬して、開口部７１Ｕ、７１Ｄに厚さ５μｍのニッケルめっき層７２を形成する。さらに、その基板を、シアン化金カリウム（７．６×１０^-3ｍｏｌ／ｌ）、塩化アンモニウム（１．９×１０^-1ｍｏｌ／ｌ）、クエン酸ナトリウム（１．２×１０^-1ｍｏｌ／ｌ）、次亜リン酸ナトリウム（１．７×１０^-1ｍｏｌ／ｌ）を含む無電解めっき液に８０℃の条件で７．５分間浸漬して、ニッケルめっき層７２上に厚さ０．０３μｍの金めっき層７４を形成する（図６（Ｂ））。
【００６６】
（２１）この後、ソルダーレジスト層７０の開口部７１Ｕ、７１Ｄに、はんだペーストを印刷して、２００℃でリフローすることにより、半田バンプ（半田体）７６Ｕ、７６Ｄを形成する。これにより、半田バンプ７６Ｕ、７６Ｄを有するプリント配線板１０を得ることができる（図７参照）。
【００６７】
次に、上述した工程で完成したプリント配線板１０へのＩＣチップ９０の載置および、ドータボード９５への取り付けについて、図８を参照して説明する。完成したプリント配線板１０の半田バンプ７６ＵにＩＣチップ９０の半田パッド９２Ｅ、９２Ｐ、９２Ｓが対応するように、ＩＣチップ９０を載置し、リフローを行うことでＩＣチップ９０の取り付けを行う。同様に、プリント配線板１０の半田バンプ７６Ｄにドータボード９５のパッド９４Ｅ、９４Ｐ、９４Ｓが対応するように、リフローすることで、ドータボード９５へプリント配線板１０を取り付ける。
【００６８】
上述した層間樹脂絶縁層４０、１４０を形成する樹脂フィルムには、難溶性樹脂、可溶性粒子、硬化剤、その他の成分が含有されている。それぞれについて以下に説明する。
【００６９】
本発明の製造方法において使用する樹脂フィルムは、酸または酸化剤に可溶性の粒子（以下、可溶性粒子という）が酸または酸化剤に難溶性の樹脂（以下、難溶性樹脂という）中に分散したものである。
なお、本発明で使用する「難溶性」「可溶性」という語は、同一の酸または酸化剤からなる溶液に同一時間浸漬した場合に、相対的に溶解速度の早いものを便宜上「可溶性」と呼び、相対的に溶解速度の遅いものを便宜上「難溶性」と呼ぶ。
【００７０】
上記可溶性粒子としては、例えば、酸または酸化剤に可溶性の樹脂粒子（以下、可溶性樹脂粒子）、酸または酸化剤に可溶性の無機粒子（以下、可溶性無機粒子）、酸または酸化剤に可溶性の金属粒子（以下、可溶性金属粒子）等が挙げられる。これらの可溶性粒子は、単独で用いても良いし、２種以上併用してもよい。
【００７１】
上記可溶性粒子の形状は特に限定されず、球状、破砕状等が挙げられる。また、上記可溶性粒子の形状は、一様な形状であることが望ましい。均一な粗さの凹凸を有する粗化面を形成することができるからである。
【００７２】
上記可溶性粒子の平均粒径としては、０．１〜１０μｍが望ましい。この粒径の範囲であれば、２種類以上の異なる粒径のものを含有してもよい。すなわち、平均粒径が０．１〜０．５μｍの可溶性粒子と平均粒径が１〜３μｍの可溶性粒子とを含有する等である。これにより、より複雑な粗化面を形成することができ、導体回路との密着性にも優れる。なお、本発明において、可溶性粒子の粒径とは、可溶性粒子の一番長い部分の長さである。
【００７３】
上記可溶性樹脂粒子としては、熱硬化性樹脂、熱可塑性樹脂等からなるものが挙げられ、酸あるいは酸化剤からなる溶液に浸漬した場合に、上記難溶性樹脂よりも溶解速度が速いものであれば特に限定されない。
上記可溶性樹脂粒子の具体例としては、例えば、エポキシ樹脂、フェノール樹脂、ポリイミド樹脂、ポリフェニレン樹脂、ポリオレフィン樹脂、フッ素樹脂等からなるものが挙げられ、これらの樹脂の一種からなるものであってもよいし、２種以上の樹脂の混合物からなるものであってもよい。
【００７４】
また、上記可溶性樹脂粒子としては、ゴムからなる樹脂粒子を用いることもできる。上記ゴムとしては、例えば、ポリブタジエンゴム、エポキシ変性、ウレタン変性、（メタ）アクリロニトリル変性等の各種変性ポリブタジエンゴム、カルボキシル基を含有した（メタ）アクリロニトリル・ブタジエンゴム等が挙げられる。これらのゴムを使用することにより、可溶性樹脂粒子が酸あるいは酸化剤に溶解しやすくなる。つまり、酸を用いて可溶性樹脂粒子を溶解する際には、強酸以外の酸でも溶解することができ、酸化剤を用いて可溶性樹脂粒子を溶解する際には、比較的酸化力の弱い過マンガン酸塩でも溶解することができる。また、クロム酸を用いた場合でも、低濃度で溶解することができる。そのため、酸や酸化剤が樹脂表面に残留することがなく、後述するように、粗化面形成後、塩化パラジウム等の触媒を付与する際に、触媒が付与されなたかったり、触媒が酸化されたりすることがない。
【００７５】
上記可溶性無機粒子としては、例えば、アルミニウム化合物、カルシウム化合物、カリウム化合物、マグネシウム化合物およびケイ素化合物からなる群より選択される少なくとも一種からなる粒子等が挙げられる。
【００７６】
上記アルミニウム化合物としては、例えば、アルミナ、水酸化アルミニウム等が挙げられ、上記カルシウム化合物としては、例えば、炭酸カルシウム、水酸化カルシウム等が挙げられ、上記カリウム化合物としては、炭酸カリウム等が挙げられ、上記マグネシウム化合物としては、マグネシア、ドロマイト、塩基性炭酸マグネシウム等が挙げられ、上記ケイ素化合物としては、シリカ、ゼオライト等が挙げられる。これらは単独で用いても良いし、２種以上併用してもよい。
【００７７】
上記可溶性金属粒子としては、例えば、銅、ニッケル、鉄、亜鉛、鉛、金、銀、アルミニウム、マグネシウム、カルシウムおよびケイ素からなる群より選択される少なくとも一種からなる粒子等が挙げられる。また、これらの可溶性金属粒子は、絶縁性を確保するために、表層が樹脂等により被覆されていてもよい。
【００７８】
上記可溶性粒子を、２種以上混合して用いる場合、混合する２種の可溶性粒子の組み合わせとしては、樹脂粒子と無機粒子との組み合わせが望ましい。両者とも導電性が低くいため樹脂フィルムの絶縁性を確保することができるとともに、難溶性樹脂との間で熱膨張の調整が図りやすく、樹脂フィルムからなる層間樹脂絶縁層にクラックが発生せず、層間樹脂絶縁層と導体回路との間で剥離が発生しないからである。
【００７９】
上記難溶性樹脂としては、層間樹脂絶縁層に酸または酸化剤を用いて粗化面を形成する際に、粗化面の形状を保持できるものであれば特に限定されず、例えば、熱硬化性樹脂、熱可塑性樹脂、これらの複合体等が挙げられる。また、これらの樹脂に感光性を付与した感光性樹脂であってもよい。感光性樹脂を用いることにより、層間樹脂絶縁層に露光、現像処理を用いてビア用開口を形成することできる。
これらのなかでは、熱硬化性樹脂を含有しているものが望ましい。それにより、めっき液あるいは種々の加熱処理によっても粗化面の形状を保持することができるからである。
【００８０】
上記難溶性樹脂の具体例としては、例えば、エポキシ樹脂、フェノール樹脂、フェノキシ樹脂、ポリイミド樹脂、ポリフェニレン樹脂、ポリオレフィン樹脂、フッ素樹脂等が挙げられる。これらの樹脂は単独で用いてもよいし、２種以上を併用してもよい。
さらには、１分子中に、２個以上のエポキシ基を有するエポキシ樹脂がより望ましい。前述の粗化面を形成することができるばかりでなく、耐熱性等にも優れてるため、ヒートサイクル条件下においても、金属層に応力の集中が発生せず、金属層の剥離などが起きにくいからである。
【００８１】
上記エポキシ樹脂としては、例えば、クレゾールノボラック型エポキシ樹脂、ビスフェノールＡ型エポキシ樹脂、ビスフェノールＦ型エポキシ樹脂、フェノールノボラック型エポキシ樹脂、アルキルフェノールノボラック型エポキシ樹脂、ビフェノールＦ型エポキシ樹脂、ナフタレン型エポキシ樹脂、ジシクロペンタジエン型エポキシ樹脂、フェノール類とフェノール性水酸基を有する芳香族アルデヒドとの縮合物のエポキシ化物、トリグリシジルイソシアヌレート、脂環式エポキシ樹脂等が挙げられる。これらは、単独で用いてもよく、２種以上を併用してもよい。それにより、耐熱性等に優れるものとなる。
【００８２】
本発明で用いる樹脂フィルムにおいて、上記可溶性粒子は、上記難溶性樹脂中にほぼ均一に分散されていることが望ましい。均一な粗さの凹凸を有する粗化面を形成することができ、樹脂フィルムにビアやスルーホールを形成しても、その上に形成する導体回路の金属層の密着性を確保することができるからである。また、粗化面を形成する表層部だけに可溶性粒子を含有する樹脂フィルムを用いてもよい。それによって、樹脂フィルムの表層部以外は酸または酸化剤にさらされることがないため、層間樹脂絶縁層を介した導体回路間の絶縁性が確実に保たれる。
【００８３】
上記樹脂フィルムにおいて、難溶性樹脂中に分散している可溶性粒子の配合量は、樹脂フィルムに対して、３〜４０重量％が望ましい。可溶性粒子の配合量が３重量％未満では、所望の凹凸を有する粗化面を形成することができない場合があり、４０重量％を超えると、酸または酸化剤を用いて可溶性粒子を溶解した際に、樹脂フィルムの深部まで溶解してしまい、樹脂フィルムからなる層間樹脂絶縁層を介した導体回路間の絶縁性を維持できず、短絡の原因となる場合がある。
【００８４】
上記樹脂フィルムは、上記可溶性粒子、上記難溶性樹脂以外に、硬化剤、その他の成分等を含有していることが望ましい。
上記硬化剤としては、例えば、イミダゾール系硬化剤、アミン系硬化剤、グアニジン系硬化剤、これらの硬化剤のエポキシアダクトやこれらの硬化剤をマイクロカプセル化したもの、トリフェニルホスフィン、テトラフェニルホスフォニウム・テトラフェニルボレート等の有機ホスフィン系化合物等が挙げられる。
【００８５】
上記硬化剤の含有量は、樹脂フィルムに対して０．０５〜１０重量％であることが望ましい。０．０５重量％未満では、樹脂フィルムの硬化が不十分であるため、酸や酸化剤が樹脂フィルムに侵入する度合いが大きくなり、樹脂フィルムの絶縁性が損なわれることがある。一方、１０重量％を超えると、過剰な硬化剤成分が樹脂の組成を変性させることがあり、信頼性の低下を招いたりしてしまうことがある。
【００８６】
上記その他の成分としては、例えば、粗化面の形成に影響しない無機化合物あるいは樹脂等のフィラーが挙げられる。上記無機化合物としては、例えば、シリカ、アルミナ、ドロマイト等が挙げられ、上記樹脂としては、例えば、ポリイミド樹脂、ポリアクリル樹脂、ポリアミドイミド樹脂、ポリフェニレン樹脂、メラニン樹脂、オレフィン系樹脂等が挙げられる。これらのフィラーを含有させることによって、熱膨脹係数の整合や耐熱性、耐薬品性の向上などを図りプリント配線板の性能を向上させることができる。
【００８７】
また、上記樹脂フィルムは、溶剤を含有していてもよい。上記溶剤としては、例えば、アセトン、メチルエチルケトン、シクロヘキサノン等のケトン類、酢酸エチル、酢酸ブチル、セロソルブアセテートやトルエン、キシレン等の芳香族炭化水素等が挙げられる。これらは単独で用いてもよいし、２種類以上併用してもよい。
【００８８】
次に、本発明の第２実施形態に係るプリント配線板１１０について、図１１を参照して説明する。上述した第１実施形態では、ＢＧＡ（ボールグリッドアレー）を配設した。この第２実施形態のプリント配線板の構成は、図１１に示すように導電性接続ピン９６を介して接続を取るＰＧＡ方式に構成されている。
【００８９】
また、上述した第１実施形態では、コア基板３０にザグリ加工によりチップコンデンサ２０を収容する凹部３４を設け、チップコンデンサ２０を収容した。第２実施形態では、通孔３０Ａを設けた第１樹脂基板３０ａおよび通孔を設けない第２、第３樹脂基板３０ｂ、３０ｃとをプリプレグ（接着板）３３ａ、３３ｂを介して貼り合わせることで、チップコンデンサ２０を収容する凹部３５を備えるコア基板３０を形成し、凹部３５内に複数個のチップコンデンサ２０を収容する。
【００９０】
本発明の第２実施形態に係るプリント配線板の製造工程について、図９及び図１０を参照して説明する。
【００９１】
（１）厚さ０．３ｍｍのガラスクロス等の心材にＢＴ（ビスマレイミドトリアジン）樹脂を含浸させ硬化させた樹脂基板３１ａの両面に銅箔３１ｂがラミネートされている銅張積層板３１Ｍを出発材料とする（図９（Ａ））。この銅貼積層板３１Ｍの銅箔３１ｂをパターン状にエッチングすることにより両面に導体回路３２を備える第２、第３樹脂基板３０ｂ、３０ｃを形成する。また、パターン状にエッチングすると共に、通孔３０Ａを形成することで導体回路３２を備える第１樹脂基板３０ａを形成する（図９（Ｂ））。そして、第３樹脂基板３０ｃと第２樹脂基板３０ｂとをガラスクロス等の心材にエポキシ樹脂を含浸させたプリプレグ（接着板）３３ｂを介して積層する。同様に、第２樹脂基板３０ｂと通孔３０Ａが形成された第１樹脂基板３０ａとを通孔３３Ａの形成されたプリプレグ（接着板）３３ａを介して積層する（図９（Ｃ））。
【００９２】
（２）そして、重ね合わせた基板を熱プレスを用いて加圧プレスすることにより、第１、第２、第３樹脂基板３０ａ、３０ｂ、３０ｃを多層状に一体化し、チップコンデンサ２０を収容する凹部３５を備えるコア基板３０を形成する（図９（Ｄ））。ここでは、先ず、加圧されることでプリプレグ３３ａ、３３ｂのエポキシ樹脂（絶縁性樹脂）を周囲に押し出し、エポキシ樹脂を第１、第２、第３樹脂基板３０ａ、３０ｂ、３０ｃに密着させる。更に、加圧と同時に加熱されることで、エポキシ樹脂が硬化し、プリプレグ３３ａ、３３ｂを接着板として介在させることで、第１樹脂基板３０ａと第２樹脂基板３０ｂと第３樹脂基板３０ｃとを強固に接着させる。
【００９３】
（３）その後、凹部３５の底面に、印刷機を用いて熱硬化系もしくはＵＶ硬化系の接着材料３６を塗布する（図９（Ｅ））。このとき、塗布以外にも、ポッティングなどをしてもよい。
【００９４】
（４）次に、複数個のチップコンデンサ２０を接着材料３６上に載置する（図１０参照）。コア基板に複数個のチップコンデンサ２０を収容することにより、コンデンサの高集積化が可能となる。
【００９５】
（５）その後、凹部３５内のチップコンデンサ２０間に、熱硬化性樹脂を充填し、加熱硬化して樹脂層３８を形成する（図１０（Ｂ参照）。このとき、熱硬化性樹脂としては、エポキシ、フェノール、ポリイミド、トリアジンが好ましい。これにより、凹部３５内のチップコンデンサ２０を固定し、チップコンデンサ２０と凹部３５の壁面との隙間を充填する。
【００９６】
（６）上記工程を経た基板３０に、熱硬化型エポキシ系樹脂シートを温度５０〜１５０℃まで昇温しながら圧力５ｋｇ／ｃｍ²で真空圧着ラミネートし、エポキシ系樹脂からなる層間樹脂絶縁層４０を設ける（図１０（Ｃ））。
【００９７】
（７）次いで、樹脂基板３０ａ側の層間樹脂絶縁層４０に、レーザにより、チップコンデンサ２０の第１端子２１，第２端子２２へ至るバイアホール用開口４２を形成する（図１０（Ｄ））。
【００９８】
（８）そして、コア基板３０にドリル又はレーザにより、スルーホール用貫通孔４４を形成する（図１０（Ｅ））。この後、酸素プラズマを用いてデスミア処理を行う。あるいは、過マンガン酸などの薬液によるデスミヤ処理を行ってもよい。
以降の工程は、上述した第１実施形態の（９）〜（２１）と同様であるため、説明を省略する。
【００９９】
引き続き、本発明の第２実施形態の改変例に係るプリント配線板について、図１２を参照して説明する。改変例のプリント配線板は、上述した第２実施形態とほぼ同様である。但し、第２実施形態では、コア基板３０に収容されるチップコンデンサ２０のみを備えていたが、改変例では、表面及び裏面に大容量のチップコンデンサ８６が実装されている。
【０１００】
ＩＣチップは、瞬時的に大電力を消費して複雑な演算処理を行う。ここで、ＩＣチップ側に大電力を供給するために、改変例では、プリント配線板に電源用のチップコンデンサ２０及びチップコンデンサ８６を備えてある。このチップコンデンサによる効果について、図１３を参照して説明する。
【０１０１】
図１３は、縦軸にＩＣチップへ供給される電圧を、横軸に時間を取ってある。
ここで、二点鎖線Ｃは、電源用コンデンサを備えないプリント配線板の電圧変動を示している。電源用コンデンサを備えない場合には、大きく電圧が減衰する。破線Ａは、表面にチップコンデンサを実装したプリント配線板の電圧変動を示している。上記二点鎖線Ｃと比較して電圧は大きく落ち込まないが、ループ長さが長くなるので、律速の電源供給が十分に行えていない。即ち、電力の供給開始時に電圧が降下している。また、二点鎖線Ｂは、図１１を参照して上述したチップコンデンサを内蔵するプリント配線板の電圧降下を示している。ループ長さは短縮できているが、コア基板３０に容量の大きなチップコンデンサを収容することができないため、電圧が変動している。ここで、実線Ｅは、図１２を参照して上述したコア基板内のチップコンデンサ２０を、また表面に大容量のチップコンデンサ８６を実装する改変例のプリント配線板の電圧変動を示している。ＩＣチップの近傍にチップコンデンサ２０を、また、大容量（及び相対的に大きなインダクタンス）のチップコンデンサ８６を備えることで、電圧変動を最小に押さえている。
【０１０２】
また、第２実施形態の改変例では、チップコンデンサ２０が、図１４（Ａ）に示すように第１、第２電極２１，２２の被覆層（図示せず）を完全に剥離した後、銅めっき膜２９により被覆してある。そして、銅めっき膜２９で被覆した第１、第２電極２１，２２に銅めっきよりなるバイアホール６０で電気的接続を取ってある。ここで、チップコンデンサの電極２１，２２は、メタライズからなり表面に凹凸がある。このため、金属層を剥き出した状態で用いると、接続層４０に非貫通孔４３を穿設する工程において、該凹凸に樹脂が残ることがある。この際には、当該樹脂残さにより第１、第２電極２１，２２とバイアホール６０との接続不良が発生することがある。これに対して、改変例では、銅めっき膜２９によって第１、第２電極２１，２２の表面が平滑になり、電極上に被覆された層間樹脂絶縁層４０に非貫通孔４２を穿設した際に、樹脂残さが残らず、バイアホール６０を形成した際の電極２１，２２との接続信頼性を高めることができる。
【０１０３】
更に、銅めっき膜２９の形成された電極２１、２２に、めっきによりバイアホール６０を形成するため、電極２１、２２とバイアホール６０との接続性が高く、ヒートサイクル試験を実施しても、電極２１、２２とバイアホール６０との間で断線が生じることがない。マイグレーションの発生もなく、コンデンサのバイアホールの接続部での不都合を引き起こさなかった。
【０１０４】
なお、上記銅めっき膜２９は、チップコンデンサの製造段階で金属層２６の表面に被覆されたニッケル／スズ層（被覆層）を、プリント配線板への搭載の段階で剥離してから設ける。この代わりに、チップコンデンサ２０の製造段階で、金属層２６の上に直接銅めっき膜２９を被覆することも可能である。即ち、改変例では、第１実施形態と同様に、レーザにて電極の銅めっき膜２９へ至る開口を設けた後、デスミヤ処理等を行い、バイアホールを銅めっきにより形成する。従って、銅めっき膜２９の表面に酸化膜が形成されていても、上記レーザ及びデスミヤ処理で酸化膜を除去できるため、適正に接続を取ることができる。
【０１０５】
また、図１４（Ｂ）に示すようにチップコンデンサ２０の第１電極２１、第２電極２２の被覆層２８から、上部を露出させてプリント配線板に収容し、被覆層２８から露出した第１電極２１、第２電極２２に電気的接続を取ることもできる。このとき、被覆層２８から露出した金属は、主成分がＣｕであることが望ましい。接続抵抗を低減することができるからである。
【０１０６】
更に、チップコンデンサ２０のセラミックから成る誘電体２３の表面には粗化層２３ａが設けられている。このため、セラミックから成るチップコンデンサ２０と樹脂からなる層間樹脂絶縁層４０との密着性が高く、ヒートサイクル試験を実施しても界面での層間樹脂絶縁層４０の剥離が発生することがない。この粗化層２３ａは、焼成後に、チップコンデンサ２０の表面を研磨することにより、また、焼成前に、粗化処理を施すこともできる。なお、改変例では、コンデンサの表面に粗化処理を施し、樹脂との密着性を高めたが、この代わりに、コンデンサの表面にシランカップリング処理を施すことも可能である。
【０１０７】
引き続き、本発明の第３実施形態に係るプリント配線板の構成について図１５を参照して説明する。
この第３実施形態のプリント配線板の構成は、上述した第１実施形態とほぼ同様である。但し、コア基板３０への収容されるチップコンデンサ２０が異なる。
図１５は、チップコンデンサの平面図を示している。図１５（Ａ）は、多数個取り用の裁断前のチップコンデンサを示し、図中で一点鎖線は、裁断線を示している。上述した第１実施形態のプリント配線板では、図１５（Ｂ）に平面図を示すようにチップコンデンサの側縁に第１電極２１及び第２電極２２を配設してある。図１５（Ｃ）は、第３実施形態の多数個取り用の裁断前のチップコンデンサを示し、図中で一点鎖線は、裁断線を示している。第３実施形態のプリント配線板では、図１５（Ｄ）に平面図を示すようにチップコンデンサの側縁の内側に第１電極２１及び第２電極２２を配設してある。
【０１０８】
この第３実施形態のプリント配線板では、外縁の内側に電極の形成されたチップコンデンサ２０を用いるため、容量の大きなチップコンデンサを用いることができる。
引き続き、第３実施形態の第１改変例に係るプリント配線板図１６を参照して説明する。
図１６は、第１改変例に係るプリント配線板のコア基板に収容されるチップコンデンサ２０の平面図を示している。上述した第１実施形態では、複数個の小容量のチップコンデンサをコア基板に収容したが、第１改変例では、大容量の大判のチップコンデンサ２０をコア基板に収容してある。ここで、チップコンデンサ２０は、第１電極２１と第２電極２２と、誘電体２３と、第１電極２１へ接続された第１導電膜２４と、第２電極２２側に接続された第２導電膜２５と、第１導電膜２４及び第２導電膜２５へ接続されていないチップコンデンサの上下面の接続用の電極２７とから成る。この電極２７を介してＩＣチップ側とドータボード側とが接続されている。
【０１０９】
この第１改変例のプリント配線板では、大判のチップコンデンサ２０を用いるため、容量の大きなチップコンデンサを用いることができる。また、大判のチップコンデンサ２０を用いるため、ヒートサイクルを繰り返してもプリント配線板に反りが発生することがない。
【０１１０】
図１７を参照して第２改変例に係るプリント配線板について説明する。図１７（Ａ）は、多数個取り用の裁断前のチップコンデンサを示し、図中で一点鎖線は、通常の裁断線を示し、図１７（Ｂ）は、チップコンデンサの平面図を示している。図１７（Ｂ）に示すように、この第２改変例では、多数個取り用のチップコンデンサを複数個（図中の例では３枚）連結させて大判で用いている。
【０１１１】
この第２改変例では、大判のチップコンデンサ２０を用いるため、容量の大きなチップコンデンサを用いることができる。また、大判のチップコンデンサ２０を用いるため、ヒートサイクルを繰り返してもプリント配線板に反りが発生することがない。
【０１１２】
上述した第３実施形態では、チップコンデンサをプリント配線板に内蔵させたが、チップコンデンサの代わりに、セラミック板に導電体膜を設けてなる板状のコンデンサを用いることも可能である。
【０１１３】
【発明の効果】
以上説明したように、本発明によれば、コア基板内にコンデンサを収容することが可能となり、ＩＣチップとコンデンサとの距離が短くなるため、プリント配線板のループインダクタンスを低減できる。また、導体回路が形成された樹脂基板を複数個積層してコア基板を形成しているため、コア基板内の配線密度が高まり、層間樹脂絶縁層の層数を減らすことが可能となる。
【０１１４】
また、コア基板とコンデンサの間に樹脂が充填されているので、コンデンサなどが起因する応力が発生しても緩和されるし、マイグレーションの発生がない。
そのために、コンデンサの電極とバイアホールの接続部への剥離や溶解などの影響がない。そのために、信頼性試験を実施しても所望の性能を保つことができるのである。
また、コンデンサを銅によって被覆されている場合にも、マイグレーションの発生を防止することができる。
【図面の簡単な説明】
【図１】（Ａ）、（Ｂ）、（Ｃ）、（Ｄ）、（Ｅ）は、本発明の第１実施形態に係るプリント配線板の製造工程図である。
【図２】（Ａ）、（Ｂ）、（Ｃ）、（Ｄ）、（Ｅ）は、本発明の第１実施形態に係るプリント配線板の製造工程図である。
【図３】（Ａ）、（Ｂ）、（Ｃ）、（Ｄ）は、本発明の第１実施形態に係るプリント配線板の製造工程図である。
【図４】（Ａ）、（Ｂ）、（Ｃ）、（Ｄ）は、本発明の第１実施形態に係るプリント配線板の製造工程図である。
【図５】（Ａ）、（Ｂ）は、本発明の第１実施形態に係るプリント配線板の製造工程図である。
【図６】（Ａ）、（Ｂ）は、本発明の第１実施形態に係るプリント配線板の製造工程図である。
【図７】本発明の第１実施形態に係るプリント配線板の断面図である。
【図８】図７に示すプリント配線板にＩＣチップを搭載し、ドータボードへ取り付けた状態を示す断面図である。
【図９】（Ａ）、（Ｂ）、（Ｃ）、（Ｄ）、（Ｅ）は、本発明の第２実施形態に係るプリント配線板の製造工程図である。
【図１０】（Ａ）、（Ｂ）、（Ｃ）、（Ｄ）、（Ｅ）は、本発明の第２実施形態に係るプリント配線板の製造工程図である。
【図１１】本発明の第２実施形態に係るプリント配線板にＩＣチップを搭載した状態を示す断面図である。
【図１２】本発明の第２実施形態の改変例に係るプリント配線板にＩＣチップを搭載した状態を示す断面図である。
【図１３】ＩＣチップへの供給電圧と時間との変化を示すグラフである。
【図１４】本発明の第２実施形態の改変例のチップコンデンサを示す断面図である。
【図１５】（Ａ）、（Ｂ）、（Ｃ）、（Ｄ）は、第３実施形態のプリント配線板のチップコンデンサの平面図である。
【図１６】第３実施形態に係るプリント配線板のチップコンデンサの平面図である。
【図１７】第３実施形態の改変例に係るプリント配線板のチップコンデンサの平面図である。
【符号の説明】
２０ チップコンデンサ
３０ コア基板
３０ａ 第１樹脂基板
３０ｂ 第２樹脂基板
３０ｃ 第３樹脂基板
３０Ａ 通孔
３２ 導体回路
３３ａ、３３ｂ 接着用樹脂層（接着板）
３３Ａ 開口部
３４ 凹部
３５ 凹部
３６ 接着材料
３８ 樹脂充填剤
４０ 層間樹脂絶縁層
５６ スルーホール
５８ 導体回路
６０ バイアホール
７０ ソルダーレジスト層
７１Ｕ、７１Ｄ 開口部
７２ ニッケルめっき層
７４ 金めっき層
７６Ｕ、７６Ｄ 半田バンプ
８０Ａ、８０Ｂ ビルドアップ配線層
９０ ＩＣチップ
９２Ｅ 接地用半田パッド
９２Ｓ 信号用半田パッド
９２Ｐ 電源用半田パッド
９４Ｅ 接地用半田パッド
９４Ｓ、信号用半田パッド
９４Ｐ 電源用半田パッド
９５ ドータボード
９６ 導電性接続ピン
１４０ 層間樹脂絶縁層
１５８ 導体回路
１６０ バイアホール[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a printed circuit board on which an electronic component such as an IC chip is placed, and more particularly to a printed wiring board having a built-in capacitor and a method for manufacturing the printed wiring board.
[0002]
[Prior art]
Currently, in a printed wiring board for a package substrate, a chip capacitor is sometimes surface-mounted for the purpose of facilitating power supply to an IC chip.
[0003]
Since the reactance of the wiring from the chip capacitor to the IC chip depends on the frequency, a sufficient effect cannot be obtained even if the chip capacitor is surface-mounted as the driving frequency of the IC chip increases. For this reason, the present applicant has proposed, in Japanese Patent Application No. 11-248311, a technique of forming a recess in the core substrate and accommodating a chip capacitor in the recess. As a technique for embedding a capacitor in a substrate, JP-A-6-326472, JP-A-7-263619, JP-A-10-256429, JP-A-11-45955, JP-A-11-126978, JP-A-11- No. 31868 etc.
[0004]
Japanese Patent Application Laid-Open No. 6-326472 discloses a technique of embedding a capacitor in a resin substrate made of glass epoxy. With this configuration, it is possible to reduce power supply noise, eliminate the need for a space for mounting a chip capacitor, and reduce the size of the insulating substrate. Japanese Patent Application Laid-Open No. 7-263619 discloses a technique for embedding a capacitor in a substrate such as ceramic or alumina. With this configuration, by connecting between the power supply layer and the ground layer, the wiring length is shortened and the wiring inductance is reduced.
[0005]
[Problems to be solved by the invention]
However, the above-mentioned Japanese Patent Laid-Open Nos. 6-326472 and 7-263619 cannot reduce the distance from the IC chip to the capacitor so much, and in the higher frequency region of the IC chip, the inductance is required as it is currently required. Could not be reduced. In particular, in multilayer build-up wiring boards made of resin, disconnection occurs between the chip capacitor terminals and vias due to the difference in thermal expansion coefficient between the ceramic capacitor and the resin core substrate and interlayer resin insulation layer. Peeling occurs between the capacitor and the interlayer resin insulation layer, and cracks occur in the interlayer resin insulation layer, and high reliability cannot be achieved over a long period of time.
[0006]
On the other hand, in the invention of Japanese Patent Application No. 11-248311, when there is a displacement in the position of the capacitor, the connection between the capacitor terminal and the via cannot be made accurately, and the power supply from the capacitor to the IC chip may not be possible. was there.
[0007]
Moreover, the multilayer buildup wiring board used as a package substrate builds up each interlayer resin insulating layer through the following steps. First, an interlayer insulating resin is applied, exposed and developed by a roll coater or printing to form a via hole opening for interlayer conduction, and an interlayer resin insulating layer is formed through UV curing and main curing. Further, a catalyst such as palladium is attached to the roughened surface obtained by roughening the interlayer insulating layer with an acid or an oxidizing agent. Then, a thin electroless plating film is formed, a pattern is formed on the plating film with a dry film, and after thickening by electrolytic plating, the dry film is peeled off with alkali and etched to create a conductor circuit. .
That is, it is necessary to repeat the above-described process every time one layer is formed. When the number of layers increases, the number of processes increases and the yield decreases.
[0008]
The present invention has been made to solve the above-described problems, and an object of the present invention is to provide a printed wiring board having a built-in capacitor and improved connection reliability, and a method for manufacturing the printed wiring board.
[0009]
Another object of the present invention is to provide a printed wiring board and a method for manufacturing the printed wiring board in which the loop inductance can be reduced and the number of interlayer resin insulation layers is reduced.
[0010]
[Means for Solving the Problems]
  In order to achieve the above object, the invention of claim 1 is a printed wiring board obtained by laminating a resin insulating layer and a conductor circuit on a core substrate,
  The core substrate is formed by bonding a plurality of resin substrates on which conductor circuits are formed,
  In the opening formed in the core substrateA metal film mainly composed of copper was formed on the electrode by plating.A capacitor is housed,
  A resin insulation layer is laminated on the core substrate, a conductor circuit on the resin insulation layer, and an electrode of the capacitorBetween,Provided in the resin insulation layerFormed by plating,By the via holeElectricalA technical feature is that the connection is established.
[0011]
  The invention according to claim 2 is a printed wiring board formed by laminating a resin insulating layer and a conductor circuit on a core substrate,
  The core substrate is formed by bonding a plurality of resin substrates on which conductor circuits are formed,
  In the opening formed in the core substrateA metal film mainly composed of copper was formed on the electrode by plating.A capacitor is housed,
  A resin insulation layer is laminated on the core substrate so as to cover the opening, and a conductor circuit on the resin insulation layer and an electrode of the capacitorBetween,Provided in the resin insulation layerFormed by plating,By the via holeElectricalA technical feature is that the connection is established.
[0012]
In the first and second aspects, the capacitor can be accommodated in the core substrate, and the distance between the IC chip and the capacitor is shortened, so that the loop inductance of the printed wiring board can be reduced. Further, since the core substrate is formed by laminating a plurality of resin substrates on which conductor circuits are formed, the wiring density in the core substrate is increased, and the number of interlayer resin insulating layers can be reduced.
[0013]
It means a circuit formed by a build-up method in which an interlayer resin insulation layer is provided on a core substrate, and via holes or through holes are provided in the interlayer resin insulation layer to form a conductor circuit as a conductive layer. For them, either a semi-additive method or a full additive method can be used.
[0014]
  It is desirable to fill the voids with resin. By eliminating the gap between the capacitor and the core substrate, the built-in capacitor is less likely to behave, and even if stress originating from the capacitor is generated, it can be relaxed by the filled resin. The resin also has an effect of reducing adhesion and migration between the capacitor and the core substrate.
  Further, according to the first and second aspects, electrical connection is established to the electrode of the chip capacitor formed with the metal film by a via hole formed by plating. Here, the electrode of the chip capacitor is made of metallization and has an uneven surface, but the surface is smoothed by the metal film, and a via hole is formed, so when a through hole is formed in the resin coated on the electrode The resin residue does not remain, and the connection reliability between the via hole and the electrode can be improved. Furthermore, since via holes are formed by plating on the plated electrodes, the connectivity between the electrodes and the via holes is high, and disconnection between the electrodes and the via holes may occur even when a heat cycle test is performed. Absent.
  The metal film of the capacitor electrode is preferably provided with any one of copper, nickel, and a noble metal. This is because a layer of tin, zinc or the like in the built-in capacitor tends to induce migration at the connection portion with the via hole. Therefore, the occurrence of migration can also be prevented.
[0015]
According to the third aspect, since the plurality of resin substrates are bonded together with the adhesive plate interposed therebetween, they can be firmly bonded.
[0016]
According to the fourth aspect, since the adhesive plate is made by impregnating the core material with the thermosetting resin, the core substrate can have high strength.
[0017]
According to the fifth aspect of the present invention, since the resin substrate is made by impregnating the core material with resin, the core substrate can have high strength.
[0018]
According to the sixth aspect, since a plurality of capacitors are accommodated in the core substrate, the capacitors can be highly integrated.
[0019]
According to the seventh aspect, in addition to the capacitor accommodated in the substrate, a capacitor is provided on the surface. Since the capacitor is accommodated in the printed wiring board, the distance between the IC chip and the capacitor is shortened, the loop inductance can be reduced, and the power can be supplied instantaneously. Since the capacitor is disposed, a large-capacity capacitor can be attached, and a large amount of power can be easily supplied to the IC chip.
[0020]
According to the eighth aspect, since the capacitance of the capacitor on the surface is equal to or larger than the capacitance of the capacitor on the inner layer, there is no shortage of power supply in the high frequency region, and a desired operation of the IC chip is ensured.
[0021]
According to the ninth aspect of the present invention, since the inductance of the capacitor on the surface is equal to or higher than the inductance of the capacitor on the inner layer, there is no shortage of power supply in the high frequency region, and the desired operation of the IC chip is secured.
[0024]
Further, the surface of the chip capacitor may be roughened. Thereby, the adhesiveness between the ceramic chip capacitor and the resin interlayer resin insulation layer is high, and even when the heat cycle test is performed, the interlayer resin insulation layer does not peel off at the interface.
[0025]
  Claim10Then, the thermal expansion coefficient of the insulating adhesive is set to be smaller than that of the core substrate, that is, close to a capacitor made of ceramic. For this reason, in the heat cycle test, even if an internal stress is generated between the core substrate and the capacitor due to a difference in thermal expansion coefficient, cracks, peeling, and the like hardly occur on the core substrate, and high reliability can be achieved.
[0026]
  Claim11In this case, at least a portion of the chip capacitor electrode coating layer is exposed and accommodated in the printed wiring board, and electrical connection is made to the electrode exposed from the coating layer. At this time, it is desirable that the metal exposed from the coating layer is mainly composed of Cu. This is because the connection resistance can be reduced.
[0027]
  Claim12Then, since a chip capacitor having an electrode formed inside the outer edge is used, even if conduction is made through a via hole, the external electrode can be made large, and the allowable range of alignment is widened.
[0028]
  Claim13Then, since a capacitor having electrodes formed in a matrix is used, a large chip capacitor can be easily accommodated in the core substrate. As a result, the capacitance can be increased, and the electrical problem can be solved. Further, even after various thermal histories, the printed wiring board is hardly warped.
[0029]
  Claim14Then, a plurality of chip capacitors may be connected to the capacitor. Thereby, the capacitance can be adjusted as appropriate, and the IC chip can be operated appropriately.
[0030]
  Claim16The method for producing a printed wiring board of the present invention has at least the following steps (a) to (i) as technical features:
(A) forming a conductor circuit on a plurality of resin substrates;
(B) a step of laminating a plurality of the resin substrates via an adhesive plate;
(C) A step of bonding the resin substrates to each other via the bonding plate to form a core substrate;
(D) forming a recess in the core substrate;
(E) In the recessA metal film mainly composed of copper was formed on the electrode by plating.Housing the capacitor;
(F) forming a resin insulating layer on the core substrate;
(G) forming an opening extending through the resin insulating layer to the electrode of the capacitor;
(H) forming a conductor circuit on the resin insulation layer andBy platingForm a via holeAnd making an electrical connection between the conductor circuit and the electrode of the capacitor.Process;
(I) A step of alternately laminating interlayer resin insulation layers and conductor circuits on the resin insulation layer.
[0031]
  Claim17The method for producing a printed wiring board of the present invention has at least the following steps (a) to (i) as technical features:
(A) a step of forming a resin substrate having a through hole and having a conductor circuit disposed on the surface;
(B) forming a resin substrate having no through hole and having a conductor circuit disposed on its surface;
(C) a step of laminating a resin substrate having the through hole and a resin substrate not having the through hole through an adhesive plate;
(D) a step of bonding the resin substrates to each other via the bonding plate to form a core substrate;
(E) In the through holeA metal film mainly composed of copper was formed on the electrode by plating.Housing the capacitor;
(F) forming a resin insulating layer on the core substrate;
(G) forming an opening extending through the resin insulating layer to the electrode of the capacitor;
(H) forming a conductor circuit on the resin insulation layer andBy platingForm a via holeAnd making an electrical connection between the conductor circuit and the electrode of the capacitor.Process;
(I) A step of alternately laminating interlayer resin insulation layers and conductor circuits on the resin insulation layer.
[0032]
  Claim16And claims17Then, the capacitor can be accommodated in the core substrate, and the distance between the IC chip and the capacitor is shortened, so that the loop inductance of the printed wiring board can be reduced. Further, since the core substrate is formed by laminating a plurality of resin substrates on which conductor circuits are formed, the wiring density in the core substrate is increased, and the number of interlayer resin insulating layers can be reduced.
[0033]
DETAILED DESCRIPTION OF THE INVENTION
Embodiments of the present invention will be described below with reference to the drawings.
First, the configuration of the printed wiring board according to the first embodiment of the present invention will be described with reference to FIGS. FIG. 7 shows a cross section of the printed wiring board 10, and FIG. 8 shows a state where the IC chip 90 is mounted on the printed wiring board 10 shown in FIG.
[0034]
As shown in FIG. 7, the printed wiring board 10 includes a core substrate 30 that houses the chip capacitor 20 and build-up wiring layers 80A and 80B. The build-up wiring layer 80A and the build-up wiring layer 80B are connected through the through hole 56. Build-up wiring layers 80A and 80B are made of interlayer resin insulation layers 40 and 140. In the interlayer resin insulation layer 40 on the upper buildup wiring layer 80A side, a via hole 60 connected to the conductor circuit 58 and the first electrode 21 and the second electrode 22 of the chip capacitor 20 is formed, and the interlayer resin insulation layer 140 is formed. A conductor circuit 158 and a via hole 160 are formed. On the other hand, a conductor circuit 58 is formed in the interlayer resin insulation layer 40 on the lower buildup wiring layer 80B side, and a conductor circuit 158 and a via hole 160 are formed in the interlayer resin insulation layer 140. A solder resist layer 70 is formed on the interlayer resin insulation layer 140 of the buildup wiring layers 80A and 80B.
[0035]
As shown in FIG. 7, the chip capacitor 20 includes a first electrode 21, a second electrode 22, and a dielectric 23 sandwiched between the first and second electrodes. The dielectric 23 has a first electrode 21 side. A plurality of first conductive films 24 connected to each other and a second conductive film 25 connected to the second electrode 22 side are arranged to face each other.
[0036]
As shown in FIG. 8, solder bumps 76U for connection to pads 92E, 92P, and 92S of the IC chip 90 are provided on the upper buildup wiring layer 80A. On the other hand, solder bumps 76D for connection to pads 94E, 94P, 94S of the daughter board 95 are disposed on the lower buildup wiring layer 80B.
[0037]
The signal pad 92S of the IC chip 90 shown in FIG. 8 is connected to the signal pad 94S of the daughter board 95 via the bump 76U-conductor circuit 158-via hole 160-through hole 56-via hole 160-bump 76D. It is connected.
[0038]
The grounding pad 92E of the IC chip 90 is connected to the first electrode 21 of the chip capacitor 20 through the bump 76U-via hole 160-conductor circuit 58-via hole 60. On the other hand, the grounding pad 94E of the daughter board 95 is connected to the first electrode 21 of the chip capacitor 20 via the bump 76D-via hole 160-through hole 56-via hole 60.
[0039]
The power supply pad 92P of the IC chip 90 is connected to the second electrode 22 of the chip capacitor 20 via the bump 76U-via hole 160-conductor circuit 58-via hole 60. On the other hand, the power supply pad 94P of the daughter board 95 is connected to the second electrode 22 of the chip capacitor 20 via the bump 76D-via hole 160-through hole 56-via hole 60.
[0040]
As shown in FIG. 7, the core substrate 30 of the present embodiment includes a first resin substrate 30a and a second resin substrate 30b connected to the first resin substrate 30a via an adhesive resin layer (adhesive plate) 33a. The third resin substrate 30c is connected to the second resin substrate 30b via an adhesive resin layer (adhesive plate) 33b. Conductor circuits 32 are formed on both surfaces of the first resin substrate 30a, the second resin substrate 30b, and the third resin substrate 30c. In addition, the core substrate 30 is formed with a recess 34 that can receive the chip capacitor 20 by counterboring, and the recess 34 stores the chip capacitor 20.
[0041]
Thereby, since the chip capacitor 20 can be accommodated in the core substrate 30, the distance between the IC chip 90 and the chip capacitor 20 is shortened, and the loop inductance of the printed wiring board 10 can be reduced. In addition, since the core substrate 30 is formed by laminating the first, second, and third resin substrates 30a, 30b, and 30c having the conductor circuits 32 disposed on both sides, the wiring density in the core substrate 30 is reduced. As a result, the number of interlayer resin insulation layers can be reduced.
[0042]
Furthermore, in the first embodiment, as shown in FIG. 2A, an adhesive 36 is interposed between the lower surface of the through hole 34 of the core substrate 30 and the chip capacitor 20, and the side surface of the through hole 37 and the chip capacitor 20 are interposed. A resin filler 38 is filled in between. Here, the thermal expansion coefficients of the adhesive 36 and the resin filler 38 are set to be smaller than that of the core substrate 30, that is, close to the chip capacitor 20 made of ceramic. For this reason, in the heat cycle test, even if an internal stress is generated due to a difference in thermal expansion coefficient between the core substrate 30 and the chip capacitor 20, cracks, peeling, and the like hardly occur in the core substrate 30, and high reliability can be achieved. . In addition, migration can be prevented.
[0043]
Next, a method for manufacturing the printed wiring board described above with reference to FIG. 7 will be described with reference to FIGS.
[0044]
(1) Starting material is a copper-clad laminate 31M in which a copper foil 31b is laminated on both surfaces of a resin substrate 31a obtained by impregnating a BT (bismaleimide triazine) resin into a core material such as a glass cloth having a thickness of 0.3 mm. (FIG. 1A). By etching the copper foil 31b of the copper-clad laminate 31M into a pattern, first, second, and third resin substrates 30a, 30b, and 30c having conductor circuits 32 on both surfaces are formed (FIG. 1B )). Then, the third resin substrate 30c and the second resin substrate 30b are laminated via a prepreg 33b in which a core material such as a glass cloth is impregnated with an epoxy resin. Similarly, the second resin substrate 30b and the first resin substrate 30a are stacked via the prepreg 33a (FIG. 1C).
[0045]
It should be noted that a substrate made of ceramic or AIN could not be used as the core substrate. This is because the substrate has poor external formability and cannot accommodate a capacitor, and even if it is filled with resin, voids are generated.
[0046]
(2) Then, the first, second, and third resin substrates 30a, 30b, and 30c are integrated into a multi-layer shape by press-pressing the superposed substrates using a hot press to form the core substrate 30. (FIG. 1 (D)). Here, first, the epoxy resin (insulating resin) of the prepregs 33a and 33b is pushed out by being pressurized, and the epoxy resin is brought into close contact with the first, second, and third resin substrates 30a, 30b, and 30c. Furthermore, the epoxy resin is cured by being heated simultaneously with the pressurization, and the first resin substrate 30a, the second resin substrate 30b, and the third resin substrate 30c are bonded by interposing the prepregs 33a and 33b as adhesive plates. Adhere firmly.
[0047]
(3) Next, a recess 34 for accommodating the chip capacitor 20 is formed in the core substrate 30 by counterboring (FIG. 1E). Here, the concave portion for accommodating the capacitor is provided by counterboring, but a core substrate including the accommodating portion may be formed by bonding an insulating resin substrate having an opening and a resin insulating substrate not having an opening. Is possible.
[0048]
(4) Thereafter, a thermosetting or UV curable adhesive material 36 is applied to the bottom surface of the recess 34 by using a printing machine (FIG. 2A). At this time, potting or the like may be performed in addition to the application.
Next, the chip capacitor 20 is placed on the adhesive material 36 (FIG. 2B).
Although one or a plurality of chip capacitors 20 may be used, the use of a plurality of chip capacitors 20 enables high integration of the capacitors.
[0049]
(5) After that, a thermosetting resin is filled in the recess 34, and the resin layer 38 is formed by heating and curing (FIG. 2C). At this time, epoxy, phenol, polyimide, and triazine are preferable as the thermosetting resin. As a result, the chip capacitor 20 in the recess 34 is fixed, and the gap between the chip capacitor 20 and the wall surface of the recess 34 is filled.
[0050]
(6) A pressure of 5 kg / cm while raising the temperature of a thermosetting epoxy resin sheet to be described later to a temperature of 50 to 150 ° C.²Then, an interlayer resin insulation layer 40 is provided by vacuum pressure bonding (FIG. 2D). The degree of vacuum at the time of vacuum bonding is 10 mmHg.
[0051]
(7) Next, via hole openings 42 reaching the first terminal 21 and the second terminal 22 of the chip capacitor 20 are formed in the interlayer resin insulating layer 40 on the resin substrate 30a side by a laser (FIG. 2E). .
[0052]
(8) Then, the through hole 44 for the through hole is formed in the core substrate 30 by a drill or a laser (FIG. 3A). Thereafter, desmear treatment is performed using oxygen plasma.
[0053]
(9) Next, plasma processing is performed using SV-4540 manufactured by Nippon Vacuum Technology Co., Ltd., and a roughened surface 46 is formed on the entire surface of the core substrate 30 (FIG. 3B). At this time, argon gas is used as the inert gas, and plasma treatment is performed for 2 minutes under the conditions of power 200 W, gas pressure 0.6 Pa, and temperature 70 ° C.
[0054]
(10) Thereafter, sputtering using Ni and Cu as targets is performed, and a Ni / Cu metal layer 48 is formed on the surface of the interlayer resin insulating layer 40 (FIG. 3C). Although sputtering is used here, a metal layer such as copper or nickel may be formed by electroless plating. In some cases, the electroless plating film may be formed after the sputtering. You may roughen by an acid or an oxidizing agent.
The roughened layer is preferably 0.1 to 5 μm.
[0055]
(11) Next, a photosensitive dry film is affixed to the surface of the Ni / Cu metal layer 48, a mask is placed thereon, exposure and development are performed, and a resist 50 having a predetermined pattern is formed. Then, the core substrate 30 is immersed in the electrolytic plating solution, a current is passed through the Ni / Cu metal layer 48, and electrolytic plating is performed on the resist 50 non-formation portion under the following conditions to form the electrolytic plating film 52 (FIG. 3 (D)).
[0056]

[0057]
(12) After stripping and removing the resist 50 with 5% NaOH, the Ni—Cu alloy layer 48 under the resist 50 is dissolved and removed by etching using a mixed solution of nitric acid, sulfuric acid and hydrogen peroxide, and the Ni—Cu alloy is removed. A through hole 56 having a thickness of 16 μm and a conductor circuit 58 (including a via hole 60) made of the layer 48 and the electrolytic plating film 52 are formed. After the substrate is washed with water and dried, the surface of the through hole 56 and the conductor circuit 58 (including the via hole 60) is etched by spraying an etching solution on both sides of the substrate to spray the through hole 56 and A roughened surface 62 is formed on the entire surface of the conductor circuit 58 (including the via hole 60) (FIG. 4A). As an etching solution, a mixture of 10 parts by weight of imidazole copper (II) complex, 7 parts by weight of glycolic acid, 5 parts by weight of potassium chloride and 78 parts by weight of ion-exchanged water is used.
[0058]
(13) A resin filler 64 containing an epoxy resin as a main component is filled in the through hole 56 and dried by heating. (FIG. 4B).
[0059]
(14) Thereafter, the temperature of the thermosetting epoxy resin sheet used in the step (6) is increased to 50 to 150 ° C., and the pressure is 5 kg / cm.²Then, an interlayer resin insulation layer 140 is provided by vacuum compression lamination (FIG. 4C). The degree of vacuum at the time of vacuum bonding is 10 mmHg. Although an epoxy resin is used here, a cycloolefin resin film can also be used.
[0060]
(15) Next, via hole openings 142 are formed in interlayer resin insulating layer 140 by laser (FIG. 4D).
[0061]
(16) Plasma treatment is performed using SV-4540 manufactured by Nippon Vacuum Technology Co., Ltd. in the same manner as in step (9) to form roughened surface 146 on the entire surface of interlayer resin insulating layer 140 (FIG. 5A). )). You may roughen by an acid or an oxidizing agent. The roughened layer is preferably 0.1 to 5 μm.
[0062]
(17) Thereafter, by repeating the steps (10) to (12), a conductor circuit 158 (via hole) having a thickness of 16 μm made of the Ni—Cu alloy layer 148 and the electrolytic plating film 152 is formed on the interlayer resin insulation layer 140. 160) and a roughened surface 162 are formed (FIG. 5B).
[0063]
(18) Next, the photosensitizing property obtained by acrylating 50% of an epoxy group of a cresol novolac type epoxy resin (manufactured by Nippon Kayaku Co., Ltd.) dissolved in diethylene glycol dimethyl ether (DMDG) to a concentration of 60% by weight. 46.67 parts by weight of oligomer (molecular weight 4000), 80 parts by weight of bisphenol A type epoxy resin dissolved in methyl ethyl ketone (manufactured by Yuka Shell, trade name: Epicoat 1001), 15 parts by weight of imidazole curing agent (manufactured by Shikoku Kasei Co., Ltd.) , Trade name: 2E4MZ-CN) 1.6 parts by weight, polyfunctional acrylic monomer (manufactured by Kyoei Chemical Co., Ltd., trade name: R604) which is a photosensitive monomer, polyvalent acrylic monomer (manufactured by Kyoei Chemical Co., Ltd., product) Name: DPE6A) 1.5 parts by weight, dispersion antifoaming agent (manufactured by San Nopco, trade name: S-65) 0.7 A weight part is put into a container, and a mixed composition is prepared by stirring and mixing. 2.0 parts by weight of benzophenone (manufactured by Kanto Chemical Co., Inc.) as a photoweight initiator and Michler's ketone as a photosensitizer for the mixed composition. (Kanto Chemical Co., Ltd.) 0.2 part by weight is added to obtain a solder resist composition (organic resin insulating material) having a viscosity adjusted to 2.0 Pa · s at 25 ° C.
Viscosity was measured using a B-type viscometer (manufactured by Tokyo Keiki Co., Ltd., DVL-B type) at 60 rpm for rotor No. 4 and at 6 rpm for rotor No. 3.
[0064]
(19) Next, the solder resist composition is applied to both surfaces of the substrate 30 to a thickness of 20 μm, and after drying at 70 ° C. for 20 minutes and 70 ° C. for 30 minutes, the opening of the solder resist is performed. A photomask having a thickness of 5 mm on which the pattern of the portion is drawn is brought into close contact with the solder resist layer 70 to 1000 mJ / cm²Are exposed to UV light and developed with a DMTG solution to form openings 71U and 71D (FIG. 6A).
[0065]
(20) Next, the substrate on which the solder resist layer (organic resin insulating layer) 70 is formed is made of nickel chloride (2.3 × 10^-1mol / l), sodium hypophosphate (2.8 × 10 6)^-1mol / l), sodium citrate (1.6 × 10^-1The nickel plating layer 72 having a thickness of 5 μm is formed in the openings 71U and 71D by immersing in an electroless nickel plating solution having a pH of 4.5 containing 1 mol / l). Further, the substrate was made of potassium gold cyanide (7.6 × 10 6^-3mol / l), ammonium chloride (1.9 × 10^-1mol / l), sodium citrate (1.2 × 10^-1mol / l), sodium hypophosphite (1.7 × 10^-1mol / l) is immersed in an electroless plating solution at 80 ° C. for 7.5 minutes to form a 0.03 μm thick gold plating layer 74 on the nickel plating layer 72 (FIG. 6B). .
[0066]
(21) Then, solder bumps (solder bodies) 76U and 76D are formed by printing solder paste on the openings 71U and 71D of the solder resist layer 70 and reflowing at 200 ° C. Thereby, the printed wiring board 10 having the solder bumps 76U and 76D can be obtained (see FIG. 7).
[0067]
Next, placement of the IC chip 90 on the printed wiring board 10 completed in the above-described process and attachment to the daughter board 95 will be described with reference to FIG. The IC chip 90 is mounted so that the solder pads 92E, 92P, and 92S of the IC chip 90 correspond to the solder bumps 76U of the completed printed wiring board 10, and the IC chip 90 is attached by performing reflow. Similarly, the printed wiring board 10 is attached to the daughter board 95 by reflowing so that the pads 94E, 94P, 94S of the daughter board 95 correspond to the solder bumps 76D of the printed wiring board 10.
[0068]
The resin film forming the interlayer resin insulation layers 40 and 140 described above contains a hardly soluble resin, soluble particles, a curing agent, and other components. Each will be described below.
[0069]
The resin film used in the production method of the present invention is a resin film in which particles soluble in an acid or an oxidizing agent (hereinafter referred to as soluble particles) are dispersed in a resin that is hardly soluble in an acid or oxidizing agent (hereinafter referred to as a poorly soluble resin). It is.
As used herein, the terms “poorly soluble” and “soluble” refer to those having a relatively fast dissolution rate as “soluble” for convenience when immersed in a solution of the same acid or oxidizing agent for the same time. A relatively slow dissolution rate is referred to as “slightly soluble” for convenience.
[0070]
Examples of the soluble particles include resin particles soluble in an acid or an oxidizing agent (hereinafter, soluble resin particles), inorganic particles soluble in an acid or an oxidizing agent (hereinafter, soluble inorganic particles), and a metal soluble in an acid or an oxidizing agent. Examples thereof include particles (hereinafter, soluble metal particles). These soluble particles may be used alone or in combination of two or more.
[0071]
The shape of the soluble particles is not particularly limited, and examples thereof include spherical shapes and crushed shapes. Moreover, it is desirable that the soluble particles have a uniform shape. This is because a roughened surface having unevenness with uniform roughness can be formed.
[0072]
The average particle size of the soluble particles is preferably 0.1 to 10 μm. If it is the range of this particle size, you may contain the thing of a 2 or more types of different particle size. That is, it contains soluble particles having an average particle diameter of 0.1 to 0.5 μm and soluble particles having an average particle diameter of 1 to 3 μm. Thereby, a more complicated roughened surface can be formed and it is excellent also in adhesiveness with a conductor circuit. In the present invention, the particle size of the soluble particles is the length of the longest part of the soluble particles.
[0073]
Examples of the soluble resin particles include those made of a thermosetting resin, a thermoplastic resin, and the like, as long as the dissolution rate is higher than that of the hardly soluble resin when immersed in a solution made of an acid or an oxidizing agent. There is no particular limitation.
Specific examples of the soluble resin particles include, for example, an epoxy resin, a phenol resin, a polyimide resin, a polyphenylene resin, a polyolefin resin, a fluorine resin, and the like, and may be composed of one of these resins. And it may consist of a mixture of two or more resins.
[0074]
Moreover, as the soluble resin particles, resin particles made of rubber can be used. Examples of the rubber include polybutadiene rubber, epoxy-modified, urethane-modified, various modified polybutadiene rubbers such as (meth) acrylonitrile modification, (meth) acrylonitrile-butadiene rubber containing a carboxyl group, and the like. By using these rubbers, the soluble resin particles are easily dissolved in an acid or an oxidizing agent. That is, when soluble resin particles are dissolved using an acid, acids other than strong acids can be dissolved. When soluble resin particles are dissolved using an oxidizing agent, permanganese having a relatively low oxidizing power is used. Even acid salts can be dissolved. Even when chromic acid is used, it can be dissolved at a low concentration. Therefore, no acid or oxidant remains on the resin surface, and as described later, when a catalyst such as palladium chloride is applied after the roughened surface is formed, the catalyst is not applied or the catalyst is oxidized. There is nothing to do.
[0075]
Examples of the soluble inorganic particles include particles composed of at least one selected from the group consisting of aluminum compounds, calcium compounds, potassium compounds, magnesium compounds, and silicon compounds.
[0076]
Examples of the aluminum compound include alumina and aluminum hydroxide. Examples of the calcium compound include calcium carbonate and calcium hydroxide. Examples of the potassium compound include potassium carbonate and the like. Examples of the magnesium compound include magnesia, dolomite, basic magnesium carbonate and the like, and examples of the silicon compound include silica and zeolite. These may be used alone or in combination of two or more.
[0077]
Examples of the soluble metal particles include particles composed of at least one selected from the group consisting of copper, nickel, iron, zinc, lead, gold, silver, aluminum, magnesium, calcium, and silicon. Further, the surface layer of these soluble metal particles may be coated with a resin or the like in order to ensure insulation.
[0078]
When two or more kinds of the soluble particles are used in combination, the combination of the two kinds of soluble particles to be mixed is preferably a combination of resin particles and inorganic particles. Both of them have low electrical conductivity, so that the insulation of the resin film can be ensured, and the thermal expansion can be easily adjusted between the poorly soluble resin, and no crack occurs in the interlayer resin insulation layer made of the resin film. This is because no peeling occurs between the interlayer resin insulation layer and the conductor circuit.
[0079]
The poorly soluble resin is not particularly limited as long as it can maintain the shape of the roughened surface when the roughened surface is formed using an acid or an oxidizing agent in the interlayer resin insulation layer. For example, thermosetting Examples thereof include resins, thermoplastic resins, and composites thereof. Moreover, the photosensitive resin which provided photosensitivity to these resin may be sufficient. By using a photosensitive resin, a via opening can be formed in the interlayer resin insulation layer using exposure and development processes.
Among these, those containing a thermosetting resin are desirable. This is because the shape of the roughened surface can be maintained by the plating solution or various heat treatments.
[0080]
Specific examples of the hardly soluble resin include an epoxy resin, a phenol resin, a phenoxy resin, a polyimide resin, a polyphenylene resin, a polyolefin resin, and a fluorine resin. These resins may be used alone or in combination of two or more.
Furthermore, an epoxy resin having two or more epoxy groups in one molecule is more desirable. Not only can the aforementioned roughened surface be formed, but also has excellent heat resistance, etc., so that stress concentration does not occur in the metal layer even under heat cycle conditions, and peeling of the metal layer is unlikely to occur. Because.
[0081]
Examples of the epoxy resin include cresol novolac type epoxy resin, bisphenol A type epoxy resin, bisphenol F type epoxy resin, phenol novolac type epoxy resin, alkylphenol novolac type epoxy resin, biphenol F type epoxy resin, naphthalene type epoxy resin, Examples thereof include cyclopentadiene type epoxy resins, epoxidized products of condensates of phenols and aromatic aldehydes having a phenolic hydroxyl group, triglycidyl isocyanurate, and alicyclic epoxy resins. These may be used alone or in combination of two or more. Thereby, it will be excellent in heat resistance.
[0082]
In the resin film used in the present invention, it is desirable that the soluble particles are dispersed almost uniformly in the hardly soluble resin. A roughened surface having unevenness with a uniform roughness can be formed, and even when a via or a through hole is formed in a resin film, adhesion of a metal layer of a conductor circuit formed thereon can be secured. Because. Moreover, you may use the resin film containing a soluble particle only in the surface layer part which forms a roughening surface. As a result, since the portion other than the surface layer portion of the resin film is not exposed to the acid or the oxidizing agent, the insulation between the conductor circuits via the interlayer resin insulation layer is reliably maintained.
[0083]
In the resin film, the blending amount of the soluble particles dispersed in the hardly soluble resin is preferably 3 to 40% by weight with respect to the resin film. When the blending amount of the soluble particles is less than 3% by weight, a roughened surface having desired irregularities may not be formed. When the blending amount exceeds 40% by weight, the soluble particles are dissolved using an acid or an oxidizing agent In addition, the resin film is melted to the deep part of the resin film, and the insulation between the conductor circuits through the interlayer resin insulating layer made of the resin film cannot be maintained, which may cause a short circuit.
[0084]
The resin film preferably contains a curing agent, other components and the like in addition to the soluble particles and the hardly soluble resin.
Examples of the curing agent include imidazole curing agents, amine curing agents, guanidine curing agents, epoxy adducts of these curing agents, microcapsules of these curing agents, triphenylphosphine, and tetraphenylphosphorus. And organic phosphine compounds such as nium tetraphenylborate.
[0085]
The content of the curing agent is desirably 0.05 to 10% by weight with respect to the resin film. If it is less than 0.05% by weight, since the resin film is not sufficiently cured, the degree of penetration of the acid and the oxidant into the resin film increases, and the insulating properties of the resin film may be impaired. On the other hand, if it exceeds 10% by weight, an excessive curing agent component may denature the composition of the resin, which may lead to a decrease in reliability.
[0086]
Examples of the other components include fillers such as inorganic compounds or resins that do not affect the formation of the roughened surface. Examples of the inorganic compound include silica, alumina, and dolomite. Examples of the resin include polyimide resin, polyacrylic resin, polyamideimide resin, polyphenylene resin, melanin resin, and olefin resin. By containing these fillers, it is possible to improve the performance of the printed wiring board by matching the thermal expansion coefficient, improving heat resistance, and chemical resistance.
[0087]
Moreover, the said resin film may contain the solvent. Examples of the solvent include ketones such as acetone, methyl ethyl ketone, and cyclohexanone, and aromatic hydrocarbons such as ethyl acetate, butyl acetate, cellosolve acetate, toluene, and xylene. These may be used alone or in combination of two or more.
[0088]
Next, a printed wiring board 110 according to a second embodiment of the present invention will be described with reference to FIG. In the first embodiment described above, a BGA (ball grid array) is provided. The configuration of the printed wiring board according to the second embodiment is configured in a PGA system in which connection is established via conductive connection pins 96 as shown in FIG.
[0089]
Further, in the first embodiment described above, the core substrate 30 is provided with the concave portion 34 for accommodating the chip capacitor 20 by counterboring, and the chip capacitor 20 is accommodated. In the second embodiment, the first resin substrate 30a provided with the through hole 30A and the second and third resin substrates 30b and 30c not provided with the through hole are bonded to each other through the prepregs (adhesive plates) 33a and 33b. Then, the core substrate 30 including the concave portion 35 for accommodating the chip capacitor 20 is formed, and the plurality of chip capacitors 20 are accommodated in the concave portion 35.
[0090]
A manufacturing process of the printed wiring board according to the second embodiment of the present invention will be described with reference to FIGS.
[0091]
(1) Starting material is a copper-clad laminate 31M in which a copper foil 31b is laminated on both surfaces of a resin substrate 31a obtained by impregnating a BT (bismaleimide triazine) resin into a core material such as a glass cloth having a thickness of 0.3 mm. (FIG. 9A). By etching the copper foil 31b of the copper-clad laminate 31M into a pattern, second and third resin substrates 30b and 30c having conductor circuits 32 on both surfaces are formed. Further, the first resin substrate 30a provided with the conductor circuit 32 is formed by etching in a pattern and forming the through holes 30A (FIG. 9B). Then, the third resin substrate 30c and the second resin substrate 30b are laminated via a prepreg (adhesive plate) 33b in which a core material such as glass cloth is impregnated with an epoxy resin. Similarly, the second resin substrate 30b and the first resin substrate 30a in which the through holes 30A are formed are stacked via a prepreg (adhesive plate) 33a in which the through holes 33A are formed (FIG. 9C).
[0092]
(2) Then, the first, second, and third resin substrates 30a, 30b, and 30c are integrated into a multilayer shape by press-pressing the stacked substrates using a hot press, and the chip capacitor 20 is accommodated. A core substrate 30 including the recesses 35 is formed (FIG. 9D). Here, first, the epoxy resin (insulating resin) of the prepregs 33a and 33b is pushed out by being pressurized, and the epoxy resin is brought into close contact with the first, second, and third resin substrates 30a, 30b, and 30c. Furthermore, the epoxy resin is cured by being heated simultaneously with the pressurization, and the first resin substrate 30a, the second resin substrate 30b, and the third resin substrate 30c are bonded by interposing the prepregs 33a and 33b as adhesive plates. Adhere firmly.
[0093]
(3) Thereafter, a thermosetting or UV curable adhesive material 36 is applied to the bottom surface of the recess 35 using a printing machine (FIG. 9E). At this time, potting or the like may be performed in addition to the application.
[0094]
(4) Next, a plurality of chip capacitors 20 are placed on the adhesive material 36 (see FIG. 10). By accommodating a plurality of chip capacitors 20 on the core substrate, the capacitors can be highly integrated.
[0095]
(5) After that, a thermosetting resin is filled between the chip capacitors 20 in the recesses 35 and is heated and cured to form a resin layer 38 (see FIG. 10B). Epoxy, phenol, polyimide, and triazine are preferable, thereby fixing the chip capacitor 20 in the recess 35 and filling the gap between the chip capacitor 20 and the wall surface of the recess 35.
[0096]
(6) A pressure of 5 kg / cm while heating the thermosetting epoxy resin sheet to a temperature of 50 to 150 ° C. on the substrate 30 that has undergone the above steps.²And an interlayer resin insulation layer 40 made of an epoxy resin is provided (FIG. 10C).
[0097]
(7) Next, via hole openings 42 reaching the first terminal 21 and the second terminal 22 of the chip capacitor 20 are formed in the interlayer resin insulating layer 40 on the resin substrate 30a side by a laser (FIG. 10D). .
[0098]
(8) Then, the through hole 44 for the through hole is formed in the core substrate 30 by a drill or a laser (FIG. 10E). Thereafter, desmear treatment is performed using oxygen plasma. Or you may perform the desmear process by chemical | medical solutions, such as permanganic acid.
Since the subsequent steps are the same as (9) to (21) of the first embodiment described above, description thereof will be omitted.
[0099]
Next, a printed wiring board according to a modification of the second embodiment of the present invention will be described with reference to FIG. The modified printed wiring board is substantially the same as that of the second embodiment described above. However, in the second embodiment, only the chip capacitor 20 accommodated in the core substrate 30 is provided, but in the modified example, large-capacity chip capacitors 86 are mounted on the front surface and the back surface.
[0100]
An IC chip consumes a large amount of power instantaneously and performs complicated arithmetic processing. Here, in order to supply large power to the IC chip side, in the modified example, a chip capacitor 20 for power supply and a chip capacitor 86 are provided on the printed wiring board. The effect of this chip capacitor will be described with reference to FIG.
[0101]
In FIG. 13, the vertical axis indicates the voltage supplied to the IC chip, and the horizontal axis indicates time.
Here, an alternate long and two short dashes line C indicates a voltage fluctuation of a printed wiring board that does not include a power supply capacitor. When the power supply capacitor is not provided, the voltage is greatly attenuated. A broken line A indicates voltage fluctuation of a printed wiring board having a chip capacitor mounted on the surface. The voltage does not drop much as compared with the two-dot chain line C, but the loop length becomes long, so the rate-determining power supply cannot be sufficiently performed. That is, the voltage drops at the start of power supply. A two-dot chain line B indicates a voltage drop of the printed wiring board incorporating the chip capacitor described above with reference to FIG. Although the loop length can be shortened, the voltage fluctuates because a large-capacity chip capacitor cannot be accommodated in the core substrate 30. Here, the solid line E indicates the voltage fluctuation of the printed wiring board of the modified example in which the chip capacitor 20 in the core substrate described above with reference to FIG. 12 and the large-capacity chip capacitor 86 are mounted on the surface. By providing the chip capacitor 20 in the vicinity of the IC chip and the chip capacitor 86 having a large capacity (and relatively large inductance), voltage fluctuation is minimized.
[0102]
In the modified example of the second embodiment, the chip capacitor 20 completely peels off the coating layers (not shown) of the first and second electrodes 21 and 22 as shown in FIG. It is covered with a plating film 29. The first and second electrodes 21 and 22 covered with the copper plating film 29 are electrically connected by via holes 60 made of copper plating. Here, the electrodes 21 and 22 of the chip capacitor are made of metallization and have irregularities on the surface. For this reason, if it is used in a state where the metal layer is exposed, the resin may remain on the unevenness in the step of forming the non-through hole 43 in the connection layer 40. At this time, the resin residue may cause a connection failure between the first and second electrodes 21 and 22 and the via hole 60. On the other hand, in the modified example, the surfaces of the first and second electrodes 21 and 22 are smoothed by the copper plating film 29, and the non-through holes 42 are formed in the interlayer resin insulating layer 40 covered on the electrodes. In this case, no resin residue remains, and the connection reliability with the electrodes 21 and 22 when the via hole 60 is formed can be improved.
[0103]
Furthermore, since the via hole 60 is formed by plating on the electrodes 21 and 22 on which the copper plating film 29 is formed, the connectivity between the electrodes 21 and 22 and the via hole 60 is high, and even if a heat cycle test is performed, No disconnection occurs between the electrodes 21 and 22 and the via hole 60. There was no migration and no inconvenience at the capacitor via-hole connection.
[0104]
The copper plating film 29 is provided after the nickel / tin layer (coating layer) coated on the surface of the metal layer 26 at the manufacturing stage of the chip capacitor is peeled off at the stage of mounting on the printed wiring board. Alternatively, the copper plating film 29 can be directly coated on the metal layer 26 at the manufacturing stage of the chip capacitor 20. That is, in the modified example, as in the first embodiment, an opening reaching the copper plating film 29 of the electrode is provided by a laser, and then desmear processing or the like is performed to form a via hole by copper plating. Therefore, even if an oxide film is formed on the surface of the copper plating film 29, the oxide film can be removed by the laser and desmear treatment, so that a proper connection can be established.
[0105]
Further, as shown in FIG. 14B, the first electrode 21 and the second electrode 22 of the chip capacitor 20 are exposed from the coating layer 28 of the first electrode 21 and accommodated in the printed wiring board and exposed from the coating layer 28. Electrical connection can also be made to the electrode 21 and the second electrode 22. At this time, it is desirable that the metal exposed from the coating layer 28 is mainly composed of Cu. This is because the connection resistance can be reduced.
[0106]
Further, a roughened layer 23 a is provided on the surface of the dielectric 23 made of ceramic of the chip capacitor 20. For this reason, the adhesion between the ceramic chip capacitor 20 and the resin interlayer resin insulation layer 40 is high, and the interlayer resin insulation layer 40 does not peel off at the interface even when the heat cycle test is performed. The roughened layer 23a can be subjected to a roughening treatment by polishing the surface of the chip capacitor 20 after firing or before firing. In the modified example, the surface of the capacitor is roughened to improve the adhesion with the resin. Alternatively, the surface of the capacitor can be subjected to a silane coupling treatment.
[0107]
The configuration of the printed wiring board according to the third embodiment of the present invention will be described with reference to FIG.
The configuration of the printed wiring board of the third embodiment is substantially the same as that of the first embodiment described above. However, the chip capacitor 20 accommodated in the core substrate 30 is different.
FIG. 15 shows a plan view of the chip capacitor. FIG. 15A shows a chip capacitor before cutting for multi-piece cutting, and a one-dot chain line in the drawing indicates a cutting line. In the printed wiring board of the first embodiment described above, the first electrode 21 and the second electrode 22 are arranged on the side edge of the chip capacitor as shown in the plan view of FIG. FIG. 15C shows the chip capacitor before cutting for multi-piece fabrication according to the third embodiment, and the alternate long and short dash line in the drawing indicates the cutting line. In the printed wiring board of the third embodiment, the first electrode 21 and the second electrode 22 are disposed inside the side edge of the chip capacitor as shown in the plan view of FIG.
[0108]
In the printed wiring board of the third embodiment, since the chip capacitor 20 having electrodes formed inside the outer edge is used, a chip capacitor having a large capacity can be used.
Next, a printed wiring board according to a first modification of the third embodiment will be described with reference to FIG.
FIG. 16 is a plan view of the chip capacitor 20 accommodated in the core substrate of the printed wiring board according to the first modification. In the first embodiment described above, a plurality of small-capacity chip capacitors are accommodated in the core substrate. However, in the first modification, a large-capacity large-sized chip capacitor 20 is accommodated in the core substrate. Here, the chip capacitor 20 includes a first electrode 21, a second electrode 22, a dielectric 23, a first conductive film 24 connected to the first electrode 21, and a second electrode connected to the second electrode 22 side. The conductive film 25 and the connection electrodes 27 on the upper and lower surfaces of the chip capacitor not connected to the first conductive film 24 and the second conductive film 25 are formed. The IC chip side and the daughter board side are connected via this electrode 27.
[0109]
Since the large-sized chip capacitor 20 is used in the printed wiring board of the first modified example, a chip capacitor having a large capacity can be used. Further, since the large chip capacitor 20 is used, the printed wiring board is not warped even when the heat cycle is repeated.
[0110]
A printed wiring board according to a second modification will be described with reference to FIG. FIG. 17A shows a chip capacitor before cutting for multi-piece cutting, in which a one-dot chain line shows a normal cutting line, and FIG. 17B shows a plan view of the chip capacitor. . As shown in FIG. 17B, in the second modified example, a plurality of chip capacitors (three in the example in the figure) are connected and used in a large format.
[0111]
In the second modified example, since a large chip capacitor 20 is used, a chip capacitor having a large capacity can be used. Further, since the large chip capacitor 20 is used, the printed wiring board is not warped even when the heat cycle is repeated.
[0112]
In the third embodiment described above, the chip capacitor is built in the printed wiring board. However, instead of the chip capacitor, it is also possible to use a plate-like capacitor in which a conductive film is provided on a ceramic plate.
[0113]
【The invention's effect】
As described above, according to the present invention, the capacitor can be accommodated in the core substrate, and the distance between the IC chip and the capacitor is shortened, so that the loop inductance of the printed wiring board can be reduced. Further, since the core substrate is formed by laminating a plurality of resin substrates on which conductor circuits are formed, the wiring density in the core substrate is increased, and the number of interlayer resin insulation layers can be reduced.
[0114]
In addition, since the resin is filled between the core substrate and the capacitor, even if a stress caused by the capacitor or the like is generated, the stress is alleviated and no migration occurs.
Therefore, there is no influence of peeling or dissolution on the connection portion between the capacitor electrode and the via hole. Therefore, the desired performance can be maintained even if the reliability test is performed.
Also, migration can be prevented when the capacitor is covered with copper.
[Brief description of the drawings]
FIGS. 1A, 1B, 1C, 1D and 1E are manufacturing process diagrams of a printed wiring board according to a first embodiment of the present invention.
FIGS. 2A, 2B, 2C, 2D, and 2E are manufacturing process diagrams of the printed wiring board according to the first embodiment of the present invention. FIGS.
FIGS. 3A, 3B, 3C and 3D are manufacturing process diagrams of the printed wiring board according to the first embodiment of the present invention. FIGS.
4A, 4B, 4C, and 4D are manufacturing process diagrams of the printed wiring board according to the first embodiment of the present invention.
FIGS. 5A and 5B are manufacturing process diagrams of the printed wiring board according to the first embodiment of the present invention. FIGS.
6A and 6B are manufacturing process diagrams of the printed wiring board according to the first embodiment of the present invention.
FIG. 7 is a cross-sectional view of the printed wiring board according to the first embodiment of the present invention.
8 is a cross-sectional view showing a state in which an IC chip is mounted on the printed wiring board shown in FIG. 7 and attached to the daughter board.
FIGS. 9A, 9B, 9C, 9D, 9E, and 9E are manufacturing process diagrams of the printed wiring board according to the second embodiment of the present invention.
10 (A), (B), (C), (D), and (E) are manufacturing process diagrams of a printed wiring board according to a second embodiment of the present invention.
FIG. 11 is a cross-sectional view showing a state where an IC chip is mounted on a printed wiring board according to a second embodiment of the present invention.
FIG. 12 is a cross-sectional view showing a state where an IC chip is mounted on a printed wiring board according to a modification of the second embodiment of the present invention.
FIG. 13 is a graph showing changes in supply voltage to IC chip and time.
FIG. 14 is a cross-sectional view showing a chip capacitor according to a modification of the second embodiment of the present invention.
15A, 15B, 15C, and 15D are plan views of chip capacitors of a printed wiring board according to a third embodiment.
FIG. 16 is a plan view of a chip capacitor of the printed wiring board according to the third embodiment.
FIG. 17 is a plan view of a chip capacitor of a printed wiring board according to a modification of the third embodiment.
[Explanation of symbols]
20 chip capacitors
30 core substrate
30a First resin substrate
30b Second resin substrate
30c Third resin substrate
30A through hole
32 conductor circuit
33a, 33b Adhesive resin layer (adhesive plate)
33A opening
34 recess
35 recess
36 Adhesive materials
38 Resin filler
40 Interlayer resin insulation layer
56 Through hole
58 Conductor circuit
60 Bahia Hall
70 Solder resist layer
71U, 71D opening
72 Nickel plating layer
74 Gold plating layer
76U, 76D Solder bump
80A, 80B Build-up wiring layer
90 IC chip
92E Grounding solder pad
92S Signal Solder Pad
92P Power supply solder pads
94E Grounding solder pad
94S, signal solder pad
94P Power supply solder pads
95 Daughter board
96 Conductive connection pins
140 Interlayer resin insulation layer
158 Conductor circuit
160 Viahole

Claims (17)

A printed wiring board formed by laminating a resin insulating layer and a conductor circuit on a core substrate,
The core substrate is formed by bonding a plurality of resin substrates on which conductor circuits are formed,
In the opening formed in the core substrate, a capacitor in which a metal film mainly composed of copper is formed on an electrode by plating is accommodated,
A resin insulation layer is laminated on the core substrate, and electrical connection is established by a via hole formed in the resin insulation layer between the conductor circuit on the resin insulation layer and the capacitor electrode and formed by plating. A printed wiring board characterized by being made. A printed wiring board formed by laminating a resin insulating layer and a conductor circuit on a core substrate,
The core substrate is formed by bonding a plurality of resin substrates on which conductor circuits are formed,
In the opening formed in the core substrate, a capacitor in which a metal film mainly composed of copper is formed on an electrode by plating is accommodated,
A resin insulating layer is laminated on the core substrate so as to cover the opening , and is provided on the resin insulating layer between the conductor circuit on the resin insulating layer and the electrode of the capacitor , and is formed by plating . A printed wiring board characterized by being electrically connected by a via hole.   The printed wiring board according to claim 1 or 2, wherein the plurality of resin substrates are bonded together with an adhesive plate interposed therebetween.   The printed wiring board according to claim 3, wherein the adhesive plate is formed by impregnating a core material with a thermosetting resin.   The printed circuit board according to any one of claims 1 to 4, wherein the resin substrate is formed by impregnating a core material with a resin.   The printed wiring board according to claim 1, wherein the capacitor includes a plurality of capacitors.   The printed wiring board according to claim 1, wherein a capacitor is mounted on a surface of the printed wiring board.   8. The printed wiring board according to claim 7, wherein a capacitance of the chip capacitor on the surface is equal to or greater than a capacitance of the chip capacitor on the inner layer.   8. The printed wiring board according to claim 7, wherein the inductance of the chip capacitor on the surface is equal to or greater than the inductance of the chip capacitor on the inner layer.   3. The printed wiring board according to claim 1, wherein a capacitor is joined to the core substrate with an insulating adhesive, and the insulating adhesive has a smaller coefficient of thermal expansion than the core substrate.   10. The device according to claim 1, wherein at least a part of the covering layer of the electrode of the capacitor is exposed, and the electrode exposed from the covering layer is electrically connected by plating. 11. Printed wiring board. As the capacitor, printed wiring board according to one of claims 1 to 11, characterized in that using a chip capacitor having electrodes formed inside of the outer edge. As the capacitor, printed wiring board according to one of claims 1 to 12, characterized in that using a chip capacitor formed of the electrode in a matrix. Printed circuit board according to one of claims 1 to 13, characterized in that as the capacitor, it is used by plural connecting chip capacitors for multi-piece.   The printed wiring board according to claim 1, wherein the core substrate is covered with a resin insulating layer, and a through hole is formed so as to pass through the core substrate and the resin insulating layer. . A method for producing a printed wiring board comprising at least the following steps (a) to (i):
(A) forming a conductor circuit on a plurality of resin substrates;
(B) a step of laminating a plurality of the resin substrates via an adhesive plate;
(C) A step of bonding the resin substrates to each other via the bonding plate to form a core substrate;
(D) forming a recess in the core substrate;
(E) A step of accommodating a capacitor in which a metal film mainly composed of copper is formed on the electrode by plating in the recess;
(F) forming a resin insulating layer on the core substrate;
(G) forming an opening extending through the resin insulating layer to the electrode of the capacitor;
(H) forming a conductor circuit on the resin insulating layer, forming a via hole in the opening by plating, and establishing an electrical connection between the conductor circuit and the capacitor electrode ;
(I) A step of alternately laminating interlayer resin insulation layers and conductor circuits on the resin insulation layer. A method for producing a printed wiring board comprising at least the following steps (a) to (i):
(A) A step of forming a resin substrate having through holes and having a conductor circuit disposed on the surface;
(B) forming a resin substrate having no through hole and having a conductor circuit disposed on its surface;
(C) a step of laminating a resin substrate having the through hole and a resin substrate not having the through hole through an adhesive plate;
(D) a step of bonding the resin substrates to each other via the bonding plate to form a core substrate;
(E) A step of accommodating a capacitor in which a metal film mainly composed of copper is formed on the electrode by plating in the through hole;
(F) forming a resin insulating layer on the core substrate;
(G) forming an opening extending through the resin insulating layer to the electrode of the capacitor;
(H) forming a conductor circuit on the resin insulating layer, forming a via hole in the opening by plating, and establishing an electrical connection between the conductor circuit and the capacitor electrode ;
(I) A step of alternately laminating interlayer resin insulation layers and conductor circuits on the resin insulation layer.

Images