JP2002118366A - Printed wiring board and manufacturing method thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a printed wiring board and manufacturing method thereof where the loop inductance is reduced while the number of inter-layer resin insulating layers is decreased. SOLUTION: First, second, and third resin substrates 30a, 30b, 30c where a conductor circuit 32 is formed on both surfaces are laminated through bonding resin layers 33a and 33b to form a core substrate 30, in which a chip capacitor 20 is provided. Thus, the loop inductance is reduced while the number of inter- layer resin insulating layers is decreased.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a printed circuit board on which electronic components such as IC chips are mounted, and more particularly to a printed circuit board having a built-in capacitor and a method of manufacturing the printed circuit board.

[0002]

2. Description of the Related Art At present, in a printed wiring board for a package substrate, a chip capacitor is sometimes mounted on a surface for the purpose of, for example, smoothly supplying power to an IC chip.

Since the reactance of the wiring from the chip capacitor to the IC chip depends on the frequency, a sufficient effect cannot be obtained even if the chip capacitor is surface-mounted with the increase in the driving frequency of the IC chip. For this reason, the present applicant has proposed a technique in Japanese Patent Application No. 11-248311 in which a recess is formed in a core substrate and a chip capacitor is accommodated in the recess. Japanese Patent Application Laid-Open No. 6-326472 discloses a technique for embedding a capacitor in a substrate.
JP-A-7-263519, JP-A-10-256429
JP-A-11-45555, JP-A-11-1269
No. 78 and JP-A-11-31868.

Japanese Patent Application Laid-Open No. 6-326472 discloses a technique for embedding a capacitor in a resin substrate made of glass epoxy. With this configuration, power supply noise is reduced, and a space for mounting a chip capacitor is not required, and the size of the insulating substrate can be reduced. In addition, Japanese Patent Application Laid-Open
No. 263619 discloses a technique for embedding a capacitor in a substrate made of ceramic, alumina, or the like. With this configuration, by connecting between the power supply layer and the ground layer, the wiring length is shortened and the wiring inductance is reduced.

[0005]

However, the above-mentioned Japanese Patent Application Laid-Open No. 6-326472 and Japanese Patent Application Laid-open No.
Cannot reduce the distance between the IC chip and the capacitor too much, and could not reduce the inductance as required at present in the higher frequency range of the IC chip. In particular, in the case of a resin-made multilayer build-up wiring board, disconnection between a terminal of a chip capacitor and a via due to a difference in the coefficient of thermal expansion between a capacitor made of ceramic and a core substrate made of resin and an interlayer resin insulating layer. Peeling occurred between the capacitor and the interlayer resin insulation layer, cracks occurred in the interlayer resin insulation layer, and high reliability could not be achieved for a long period of time.

On the other hand, in the invention of Japanese Patent Application No. 11-248311, when there is a displacement in the arrangement of the capacitor, the connection between the terminal of the capacitor and the via cannot be made accurately, and the power supply from the capacitor to the IC chip is not possible. There was a fear that it would not be possible.

In a multilayer build-up wiring board used as a package substrate, each interlayer resin insulation layer is built up through the following steps. First, apply, expose and develop interlayer insulating resin by roll coater or printing,
By forming a via hole opening for interlayer conduction,
After V curing and main curing, an interlayer resin insulating layer is formed. Further, a catalyst such as palladium is applied to the roughened surface obtained by subjecting the interlayer insulating layer to a roughening treatment with an acid, an oxidizing agent, or the like. Then, form a thin electroless plating film, form a pattern on the plating film with a dry film, and after thickening by electrolytic plating, peel off and remove the dry film with alkali,
Etching to create conductor circuits. That is, it is necessary to repeat the above-described steps each time one layer is formed,
As the number of layers increases, the number of steps increases and the yield decreases.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-described problems, and an object of the present invention is to provide a printed wiring board having a built-in capacitor and improved connection reliability, and a method of manufacturing the printed wiring board. It is in.

Another object of the present invention is to provide a printed wiring board and a method for manufacturing the printed wiring board, wherein the loop inductance can be reduced and the number of interlayer resin insulating layers is reduced.

[0010]

According to the first aspect of the present invention, there is provided a printed wiring board comprising a resin insulating layer and a conductive circuit laminated on a core substrate.
The technical feature of the core substrate is that a plurality of resin substrates on which conductive circuits are formed are bonded together, and a capacitor is housed in the core substrate.

According to a second aspect of the present invention, there is provided a printed wiring board comprising a resin insulating layer and a conductive circuit laminated on a core substrate, wherein the core substrate comprises a plurality of resin substrates on which a conductive circuit is formed. It is a technical feature that the capacitor is housed in a recess formed in the core substrate.

According to the first and second aspects, the capacitor can be accommodated in the core substrate, and the distance between the IC chip and the capacitor is shortened, so that the loop inductance of the printed wiring board can be reduced. Further, since the core substrate is formed by laminating a plurality of resin substrates on which conductive circuits are formed, the wiring density in the core substrate is increased, and the number of interlayer resin insulating layers can be reduced.

A circuit formed by a build-up method in which an interlayer resin insulation layer is provided on a core substrate, a via hole or a through hole is provided in the interlayer resin insulation layer, and a conductor circuit as a conductive layer is formed. I have. They include
Either a semi-additive method or a full-additive method can be used.

It is desirable to fill the void with a resin. By eliminating the gap between the capacitor and the core substrate, the built-in capacitor is less likely to behave, and even if a stress originating from the capacitor is generated, the stress can be reduced by the filled resin. The resin also has the effect of reducing adhesion and migration between the capacitor and the core substrate.

According to the third aspect, since a plurality of resin substrates are bonded together with an adhesive plate interposed therebetween, they can be firmly bonded.

According to the fourth aspect, since the adhesive plate is formed by impregnating the core material with a thermosetting resin, the core substrate can have high strength.

In the fifth aspect, the resin substrate is obtained by impregnating the core material with the resin, so that the core substrate can have high strength.

According to the sixth aspect, since a plurality of capacitors are accommodated in the core substrate, high integration of the capacitors becomes possible.

According to the present invention, a capacitor is provided on the surface in addition to the capacitor housed in the substrate. Since the capacitor is housed in the printed wiring board, the distance between the IC chip and the capacitor is shortened, the loop inductance is reduced, and power can be supplied instantaneously. Because a capacitor is provided, a large-capacity capacitor can be attached.
Large power can be easily supplied to the IC chip.

According to the present invention, since the capacitance of the capacitor on the front surface is equal to or larger than the capacitance of the capacitor in the inner layer, there is no shortage of power supply in a high frequency region, and a desired operation of the IC chip is ensured.

According to the ninth aspect, since the inductance of the capacitor on the surface is equal to or larger than the inductance of the capacitor in the inner layer, there is no shortage of power supply in a high frequency region.
The desired operation of the IC chip is ensured.

According to the tenth and eleventh aspects, the electrodes of the chip capacitor on which the metal film is formed are electrically connected to the electrodes by plating via holes. Here, the electrode of the chip capacitor is made of metallized and has irregularities on the surface,
The metal film smoothes the surface and forms a via hole, so that when a through hole is formed in the resin coated on the electrode, no resin residue remains and the connection reliability between the via hole and the electrode is improved. Can be. Furthermore, since the via hole is formed by plating on the plated electrode, the connectivity between the electrode and the via hole is high, and even if a heat cycle test is performed, disconnection between the electrode and the via hole may occur. Absent.

It is desirable that the metal film of the electrode of the capacitor is provided with any one of copper, nickel and noble metal. This is because a layer of tin or zinc in the built-in capacitor easily induces migration at a connection portion with the via hole. Therefore, the occurrence of migration can be prevented.

The surface of the chip capacitor may be roughened. Accordingly, the adhesion between the ceramic chip capacitor and the interlayer resin insulating layer made of resin is high, and the interlayer resin insulating layer does not peel off at the interface even when the heat cycle test is performed.

In the twelfth aspect, the coefficient of thermal expansion of the insulating adhesive is set to be smaller than that of the core substrate, that is, closer to that of a capacitor made of ceramic. For this reason, in the heat cycle test, even if internal stress is generated due to a difference in the coefficient of thermal expansion between the core substrate and the capacitor, cracks, peeling, and the like hardly occur on the core substrate, and high reliability can be achieved.

According to a thirteenth aspect, at least a portion of the electrode of the chip capacitor is exposed and accommodated in the printed wiring board, and the electrode exposed from the coating layer is electrically connected. At this time, the main component of the metal exposed from the coating layer is desirably Cu. This is because the connection resistance can be reduced.

According to the fourteenth aspect, since a chip capacitor having an electrode formed inside the outer edge is used, a large external electrode can be obtained even when conduction is established via the via hole, and the allowable range of alignment is widened. Disappears.

In the fifteenth aspect, since a capacitor having electrodes formed in a matrix is used, it is easy to accommodate a large chip capacitor in the core substrate. Therefore, the capacitance can be increased, so that an electrical problem can be solved. Further, even after various thermal histories, the printed wiring board is less likely to warp.

In the sixteenth aspect, a plurality of chip capacitors for multi-cavity may be connected to the capacitor. As a result, the capacitance can be adjusted appropriately, and I
The C chip can be operated.

According to a seventeenth aspect of the present invention, there is provided a method for manufacturing a printed wiring board, which comprises at least the following steps (a) to (e): (a) forming a conductive circuit on a plurality of resin substrates; (B) laminating a plurality of the resin substrates via an adhesive plate; (c) bonding the resin substrates to each other via the adhesive plate to form a core substrate; (d) the core Forming a recess in the substrate; (e) housing a capacitor in the recess.

The technical feature of the method for manufacturing a printed wiring board according to the eighteenth aspect is to provide at least the following steps (a) to (e): (a) A through hole is provided, and a conductor circuit is provided on the surface. Forming a resin substrate provided; (b) forming a resin substrate provided with a conductive circuit on a surface without a through hole; (c) a resin substrate having the through hole and not including the through hole. (D) bonding the resin substrates to each other via the adhesive plate to form a core substrate; and (e) housing a capacitor in the through hole.

In the seventeenth and eighteenth aspects, the capacitor can be accommodated in the core substrate, and the distance between the IC chip and the capacitor is shortened, so that the loop inductance of the printed wiring board can be reduced. Further, since the core substrate is formed by laminating a plurality of resin substrates on which conductive circuits are formed, the wiring density in the core substrate is increased, and the number of interlayer resin insulating layers can be reduced.

[0033]

Embodiments of the present invention will be described below with reference to the drawings. First, the configuration of the printed wiring board according to the first embodiment of the present invention will be described with reference to FIGS. FIG. 7 shows a cross section of the printed wiring board 10, and FIG. 8 shows a state where the IC chip 90 is mounted on the printed wiring board 10 shown in FIG.

As shown in FIG. 7, the printed wiring board 10
Is a core substrate 30 that houses the chip capacitor 20,
It consists of build-up wiring layers 80A and 80B. The build-up wiring layer 80A and the build-up wiring layer 80B
They are connected via through holes 56. The build-up wiring layers 80A, 80B are formed of the interlayer resin insulation layers 40, 14
Consists of zero. In the interlayer resin insulation layer 40 on the side of the upper build-up wiring layer 80A, via holes 60 connected to the conductor circuit 58 and the first electrode 21 and the second electrode 22 of the chip capacitor 20 are formed. In
Conductive circuits 158 and via holes 160 are formed. On the other hand, the conductor circuit 58 is formed in the interlayer resin insulation layer 40 on the lower buildup wiring layer 80B side, and the conductor circuit 158 and the via hole 1 are formed in the interlayer resin insulation layer 140.
60 are formed. Build-up wiring layers 80A, 8
The solder resist layer 70 is formed on the interlayer resin insulating layer 140 of the layer 0B.

As shown in FIG. 7, the chip capacitor 20 includes a first electrode 21, a second electrode 22, and a dielectric 23 sandwiched between the first and second electrodes. A first conductive film 24 connected to the electrode 21 side;
A plurality of second conductive films 25 connected to the side are arranged to face each other.

As shown in FIG. 8, pads 92E and 92 of IC chip 90 are provided on upper build-up wiring layer 80A.
A solder bump 76U for connection to P, 92S is provided. On the other hand, pads 94E, 94P, 94S of daughter board 95 are provided on lower build-up wiring layer 80B.
A solder bump 76D is provided for connection to the substrate.

The signal pads 92S of the IC chip 90 shown in FIG. 8 include bumps 76U, conductor circuits 158, via holes 160, through holes 56, and via holes 160.
-Connected to the signal pads 94S of the daughter board 95 via the bumps 76D.

The grounding pad 92E of the IC chip 90 is
It is connected to the first electrode 21 of the chip capacitor 20 via the bump 76U, the via hole 160, the conductor circuit 58, and the via hole 60. On the other hand, the ground pad 94E of the daughter board 95 is connected to the bump 76D-via hole 16D.
It is connected to the first electrode 21 of the chip capacitor 20 via the 0-through hole 56-the via hole 60.

The power supply pad 92P of the IC chip 90 is
It is connected to the second electrode 22 of the chip capacitor 20 via the bump 76U, the via hole 160, the conductor circuit 58, and the via hole 60. On the other hand, the power supply pad 94P of the daughter board 95 is connected to the bump 76D-via hole 16D.
It is connected to the second electrode 22 of the chip capacitor 20 via the 0-through hole 56-the via hole 60.

As shown in FIG. 7, the core substrate 30 of the present embodiment includes a first resin substrate 30a and a second resin substrate 30a connected to the first resin substrate 30a via an adhesive resin layer (adhesion plate) 33a.
The resin substrate 30b and the third resin substrate 30 connected to the second resin substrate 30b via an adhesive resin layer (adhesive plate) 33b.
c. First resin substrate 30a, second resin substrate 30
b, Conductive circuits 32 are formed on both surfaces of the third resin substrate 30c. Further, a concave portion 34 capable of accommodating the chip capacitor 20 is formed in the core substrate 30 by counterboring, and the concave portion 34 accommodates the chip capacitor 20.

As a result, the chip capacitor 20 can be accommodated in the core substrate 30, so that the IC chip 9
The distance between 0 and the chip capacitor 20 is reduced, and the loop inductance of the printed wiring board 10 is reduced.
Further, since the core substrate 30 is formed by laminating the first, second, and third resin substrates 30a, 30b, and 30c having the conductor circuits 32 disposed on both surfaces, the wiring density in the core substrate 30 is reduced. As a result, the number of interlayer resin insulating layers can be reduced.

Further, in the first embodiment, an adhesive 36 is interposed between the lower surface of the through hole 34 of the core substrate 30 and the chip capacitor 20 as shown in FIG. A resin filler 38 is filled between the chip capacitor 20 and the chip capacitor 20. Here, the thermal expansion coefficients of the adhesive 36 and the resin filler 38 are set to be smaller than the core substrate 30, that is, close to the chip capacitor 20 made of ceramic. For this reason, in the heat cycle test, even if internal stress is generated due to the difference in the coefficient of thermal expansion between the core substrate 30 and the chip capacitor 20, cracks, peeling, and the like hardly occur in the core substrate 30, and high reliability can be achieved. . Further, occurrence of migration can be prevented.

Next, a method of manufacturing the printed wiring board described above with reference to FIG. 7 will be described with reference to FIGS.

(1) A copper-clad laminate 31M in which copper foil 31b is laminated on both surfaces of a resin substrate 31a in which a core material such as a glass cloth having a thickness of 0.3 mm is impregnated with a BT (bismaleimide triazine) resin and cured. As a starting material (FIG. 1 (A)). The copper foil 31b of the copper-clad laminate 31M
Is etched in a pattern to form first, second, and third resin substrates 30a having conductor circuits 32 on both surfaces.
30b and 30c are formed (FIG. 1B). The prepreg 33 is obtained by impregnating the third resin substrate 30c and the second resin substrate 30b with a core material such as glass cloth and epoxy resin.
b. Similarly, the second resin substrate 30b and the first resin substrate 30a are laminated via the prepreg 33a (FIG. 1C).

The core substrate is made of ceramic or AI.
A substrate such as N could not be used. This is because the substrate has poor external formability, and may not be able to accommodate a capacitor, and may cause voids even when filled with resin.

(2) Then, the first, second, and third resin substrates 30a, 30b, and 30c are integrated into a multilayer by pressing the superposed substrates by using a hot press. Is formed (FIG. 1D). Here, first, the epoxy resin (insulating resin) of the prepregs 33a, 33b is extruded to the periphery by being pressed, and the epoxy resin is applied to the first, second, and third resin substrates 30a, 30b, 30.
c. Furthermore, the epoxy resin is cured by being heated simultaneously with the pressurization, and the prepregs 33a, 33b
As an adhesive plate, the first resin substrate 30a
And the second resin substrate 30b and the third resin substrate 30c are firmly bonded.

(3) Next, a recess 34 for accommodating the chip capacitor 20 is formed in the core substrate 30 by counterboring (FIG. 1E). Here, the concave portion for accommodating the capacitor is provided by counterboring, but a core substrate having an accommodating portion may be formed by laminating an insulating resin substrate having an opening and a resin insulating substrate having no opening. It is possible.

(4) Thereafter, a thermosetting or UV-curable adhesive material 36 is applied to the bottom surface of the concave portion 34 using a printing machine (FIG. 2A). At this time, potting may be performed in addition to the application. Next, the chip capacitor 20 is placed on the adhesive material 36 (FIG. 2B). One or a plurality of chip capacitors 20 may be used, but using a plurality of chip capacitors 20 enables high integration of the capacitors.

(5) Thereafter, the recess 34 is filled with a thermosetting resin, and is cured by heating to form a resin layer 38 (FIG. 2).
(C)). At this time, as the thermosetting resin, epoxy, phenol, polyimide, and triazine are preferable.
Thus, the chip capacitor 20 in the concave portion 34 is fixed, and the gap between the chip capacitor 20 and the wall surface of the concave portion 34 is filled.

(6) A thermosetting epoxy resin sheet described later is applied to the substrate 30 having undergone the above steps at a temperature of 50 to 150 ° C.
Vacuum compression lamination is performed at a pressure of 5 kg / cm ² while the temperature is increased to provide an interlayer resin insulating layer 40 (FIG. 2D).
The degree of vacuum during vacuum compression is 10 mmHg.

(7) Next, the chip capacitor 20 is formed on the interlayer resin insulation layer 40 on the resin substrate 30a side by laser.
A via hole opening 42 reaching the first terminal 21 and the second terminal 22 is formed (FIG. 2E).

(8) Then, through holes 44 for through holes are formed in the core substrate 30 by a drill or a laser (FIG. 3A). Thereafter, desmear treatment is performed using oxygen plasma.

(9) Next, S manufactured by Japan Vacuum Engineering Co., Ltd.
Plasma processing is performed using V-4540, and core substrate 3
Then, a roughened surface 46 is formed on the entire surface of No. 0 (FIG. 3B). At this time, an argon gas was used as an inert gas, and a power of 200 W, a gas pressure of 0.6 Pa and a temperature of 70 ° C. were used.
Perform plasma treatment for minutes.

(10) Thereafter, sputtering using Ni and Cu as targets is performed, and the Ni / Cu metal layer 48 is formed.
Is formed on the surface of the interlayer resin insulation layer 40 (FIG. 3).
(C)). Here, sputtering is used, but a metal layer such as copper or nickel may be formed by electroless plating. In some cases, the electroless plating film may be formed after the formation by sputtering. Roughening treatment may be performed with an acid or an oxidizing agent. Further, the roughened layer has a thickness of 0.1 mm.
1-5 μm is desirable.

(11) Next, a photosensitive dry film is adhered to the surface of the Ni / Cu metal layer 48, a mask is placed, and exposure and development are performed to form a resist 50 having a predetermined pattern. Then, the core substrate 30 is immersed in an electrolytic plating solution, an electric current is passed through the Ni / Cu metal layer 48, and an electrolytic plating is performed on the non-formed portion of the resist 50 under the following conditions to form an electrolytic plated film 52 (FIG. 3 (D)).

[Aqueous electrolytic plating solution] Sulfuric acid 2.24 mol / l Copper sulfate 0.26 mol / l Additive (captoside HL, manufactured by Atotech Japan) 19.5 ml / l [Electroplating conditions] Current density 1 A / dm ² Time 120 minutes Temperature 22 ± 2 ℃

(12) After removing and removing the resist 50 with 5% NaOH, the Ni-Cu alloy layer 48 under the resist 50 is dissolved and removed by etching using a mixed solution of nitric acid, sulfuric acid and hydrogen peroxide. 16-μm-thick through-hole 56 formed of a Cu alloy layer 48 and an electrolytic plating film 52
And a conductor circuit 58 (including the via hole 60). Then, after the substrate is washed with water and dried, an etching solution is sprayed on both surfaces of the substrate by spraying to etch the surfaces of the through-hole 56 and the conductor circuit 58 (including the via-hole 60). A roughened surface 62 is formed on the entire surface of the conductor circuit 58 (including the via hole 60) (FIG. 4A). As an etching solution, a mixture of 10 parts by weight of an imidazole copper (II) complex, 7 parts by weight of glycolic acid, 5 parts by weight of potassium chloride, and 78 parts by weight of ion-exchanged water is used.

(13) A resin filler 64 containing an epoxy resin as a main component is filled in the through hole 56, and is heated and dried. (FIG. 4 (B)).

(14) Thereafter, the thermosetting epoxy resin sheet used in the step (6) is vacuum-compressed and laminated at a pressure of 5 kg / cm ² while the temperature is raised to a temperature of 50 to 150 ° C. Is provided (FIG. 4C). The degree of vacuum during vacuum compression is 10 mmHg. here,
Although an epoxy resin is used, a cycloolefin resin film can also be used.

(15) Next, a via hole opening 142 is formed in the interlayer resin insulating layer 140 by laser (FIG. 4D).

(16) In the same manner as in the step (9), plasma processing is performed using SV-4540 manufactured by Japan Vacuum Engineering Co., Ltd. to form a roughened surface 146 on the entire surface of the interlayer resin insulating layer 140 (FIG. 5 (A)). Roughening treatment may be performed with an acid or an oxidizing agent. The roughened layer has a thickness of 0.1 to 5 μm.
m is desirable.

(17) Thereafter, the steps (10) to (12) are repeated, whereby the interlayer resin insulating layer 140 is
A 16 μm-thick conductive circuit 158 (including the via hole 160) and a roughened surface 162 formed of the Ni—Cu alloy layer 148 and the electrolytic plating film 152 are formed (FIG. 5B).

(18) Next, a cresol novolak type epoxy resin (manufactured by Nippon Kayaku Co., Ltd.) dissolved in diethylene glycol dimethyl ether (DMDG) so as to have a concentration of 60% by weight was used. Oligomer for imparting properties (molecular weight 4000) 46.67
15 parts by weight, 80 parts by weight of bisphenol A type epoxy resin dissolved in methyl ethyl ketone (trade name: Epicoat 1001 manufactured by Yuka Shell Co., Ltd.), imidazole curing agent (trade name: 2E4MZ-CN manufactured by Shikoku Chemicals Co., Ltd.)
1.6 parts by weight, 3 parts by weight of a polyfunctional acrylic monomer (manufactured by Kyoei Chemical Co., trade name: R604) as a photosensitive monomer,
Also polyvalent acrylic monomer (Kyoei Chemical Co., Ltd., trade name:
1.5 parts by weight of DPE6A) and 0.71 part by weight of a dispersant antifoaming agent (manufactured by San Nopco, trade name: S-65) are placed in a container, stirred and mixed to prepare a mixed composition. Of benzophenone (manufactured by Kanto Kagaku) and 0.2 parts by weight of Michler's ketone (manufactured by Kanto Kagaku) as a photosensitizer were added to give a viscosity of 25.
A solder resist composition (organic resin insulating material) adjusted to 2.0 Pa · s at ° C is obtained. The viscosity was measured using a B-type viscometer (DVL-B type, manufactured by Tokyo Keiki Co., Ltd.) at 60 rpm with rotor No. 4, and at 6 rpm with rotor N.
According to o.3.

(19) Next, the solder resist composition is applied to both sides of the substrate 30 to a thickness of 20 μm,
After performing a drying process under the conditions of 20 ° C. for 20 minutes and 70 ° C. for 30 minutes, a 5 mm-thick photomask on which a pattern of the solder resist opening is drawn is applied to the solder resist layer 70.
And exposed to ultraviolet light of 1000 mJ / cm ² ,
Openings 71U and 71D are formed by developing with a DMTG solution (FIG. 6A).

(20) Next, the substrate on which the solder resist layer (organic resin insulating layer) 70 has been formed is coated with nickel chloride (2.3 × 10 ^-1 mol / l) and sodium hypophosphite (2.8 × 10 ^-1 mol / l). 10 ^-1 mol / l) and an electroless nickel plating solution having a pH of 4.5 containing sodium citrate (1.6 × 10 ^-1 mol / l) for 20 minutes.
A nickel plating layer 72 having a thickness of 5 μm is formed on U and 71D. Further, the substrate was coated with potassium potassium cyanide (7.
6 × 10 ⁻³ mol / l), ammonium chloride (1.9 × 10 ⁻³ mol / l)
10 ^-1 mol / l), sodium citrate (1.2 × 1
0 ^-1 mol / l), sodium hypophosphite (1.7 × 1
(0 ^-1 mol / l) for 7.5 minutes at 80 ° C. to form a 0.03 μm thick gold plating layer 74 on the nickel plating layer 72 (FIG. 6).
(B)).

(21) Thereafter, the solder resist layer 70
The solder bumps (solder bodies) 76U and 76D are formed by printing a solder paste in the openings 71U and 71D of the above and performing reflow at 200 ° C. Thereby, the printed wiring board 10 having the solder bumps 76U and 76D can be obtained (see FIG. 7).

Next, mounting of the IC chip 90 on the printed wiring board 10 completed in the above-described steps and mounting on the daughter board 95 will be described with reference to FIG. The IC chip 90 is placed so that the solder pads 92E, 92P, 92S of the IC chip 90 correspond to the solder bumps 76U of the completed printed wiring board 10, and the IC chip 90 is mounted by performing reflow. Similarly,
The printed wiring board 10 is attached to the daughter board 95 by reflowing so that the pads 94E, 94P, 94S of the daughter board 95 correspond to the solder bumps 76D of the printed wiring board 10.

The resin film forming the above-mentioned interlayer resin insulation layers 40 and 140 contains a hardly soluble resin, soluble particles, a curing agent and other components. Each is described below.

The resin film used in the production method of the present invention is obtained by mixing particles soluble in an acid or an oxidizing agent (hereinafter, referred to as soluble particles) in a resin which is hardly soluble in an acid or an oxidizing agent (hereinafter, referred to as a hardly soluble resin). It is dispersed. The terms “sparingly soluble” and “soluble” as used in the present invention, when immersed in a solution containing the same acid or oxidizing agent for the same time, have a relatively high dissolution rate and are called “soluble” for convenience. Those having a relatively low dissolution rate are referred to as "poorly soluble" for convenience.

Examples of the soluble particles include resin particles soluble in an acid or an oxidizing agent (hereinafter referred to as “soluble resin particles”), inorganic particles soluble in an acid or an oxidizing agent (hereinafter referred to as “soluble inorganic particles”), and an acid or an oxidizing agent. Soluble metal particles (hereinafter referred to as “soluble metal particles”) and the like. These soluble particles may be used alone or in combination of two or more.

The shape of the soluble particles is not particularly limited.
Spherical, crushed and the like. The shape of the soluble particles is desirably a uniform shape. This is because a roughened surface having unevenness with a uniform roughness can be formed.

The average particle size of the above-mentioned soluble particles is 0.1.
1 to 10 μm is desirable. Within this particle size range, 2
More than one kind of particles having different particle sizes may be contained. That is, it contains soluble particles having an average particle size of 0.1 to 0.5 μm and soluble particles having an average particle size of 1 to 3 μm.
Thereby, a more complicated roughened surface can be formed,
Excellent adhesion to conductor circuits. In the present invention, the particle size of the soluble particles is the length of the longest portion of the soluble particles.

Examples of the soluble resin particles include those made of a thermosetting resin, a thermoplastic resin, and the like. When immersed in a solution containing an acid or an oxidizing agent, the soluble resin particles have a higher dissolution rate than the hardly soluble resin. If it is, there is no particular limitation. Specific examples of the soluble resin particles include, for example, those made of epoxy resin, phenol resin, polyimide resin, polyphenylene resin, polyolefin resin, fluororesin, and the like, and may be made of one of these resins. Alternatively, it may be composed of a mixture of two or more resins.

As the soluble resin particles, resin particles made of rubber can be used. Examples of the rubber include polybutadiene rubber, various modified polybutadiene rubbers such as epoxy-modified, urethane-modified, (meth) acrylonitrile-modified, and (meth) acrylonitrile-butadiene rubber containing a carboxyl group. By using these rubbers, the soluble resin particles are easily dissolved in an acid or an oxidizing agent. In other words, when dissolving the soluble resin particles using an acid, an acid other than a strong acid can be dissolved, and when dissolving the soluble resin particles using an oxidizing agent, permanganese having a relatively weak oxidizing power is used. Acid salts can also be dissolved. Even when chromic acid is used, it can be dissolved at a low concentration. Therefore, the acid or the oxidizing agent does not remain on the resin surface, and as described later, when a catalyst such as palladium chloride is applied after forming the roughened surface, the catalyst is not applied or the catalyst is oxidized. Or not.

Examples of the soluble inorganic particles include particles made of at least one selected from the group consisting of aluminum compounds, calcium compounds, potassium compounds, magnesium compounds and silicon compounds.

Examples of the aluminum compound include alumina and aluminum hydroxide. Examples of the calcium compound include calcium carbonate and
Examples of the potassium compound include potassium carbonate.Examples of the magnesium compound include magnesia, dolomite, and basic magnesium carbonate.Examples of the silicon compound include silica and zeolite. Is mentioned. These may be used alone or in combination of two or more.

The soluble metal particles include, for example,
Copper, nickel, iron, zinc, lead, gold, silver, aluminum,
Examples include particles made of at least one selected from the group consisting of magnesium, calcium, and silicon. These soluble metal particles may have a surface layer coated with a resin or the like in order to ensure insulation.

When two or more of the above-mentioned soluble particles are used in combination, the combination of the two types of soluble particles to be mixed is preferably a combination of resin particles and inorganic particles. Both have low conductivity, so that the insulation of the resin film can be ensured, and thermal expansion can be easily adjusted with the poorly soluble resin, and no crack occurs in the interlayer resin insulation layer made of the resin film. This is because peeling does not occur between the interlayer resin insulating layer and the conductor circuit.

The hardly soluble resin is not particularly limited as long as it can maintain the shape of the roughened surface when the roughened surface is formed by using an acid or an oxidizing agent in the interlayer resin insulating layer. Examples thereof include thermosetting resins, thermoplastic resins, and composites thereof. Further, a photosensitive resin obtained by imparting photosensitivity to these resins may be used. By using a photosensitive resin, a via opening can be formed in the interlayer resin insulating layer by using exposure and development processes. Among these, those containing a thermosetting resin are desirable. Thereby, the shape of the roughened surface can be maintained even by the plating solution or various heat treatments.

Specific examples of the hardly soluble resin include, for example, epoxy resin, phenol resin, phenoxy resin,
Examples thereof include a polyimide resin, a polyphenylene resin, a polyolefin resin, and a fluorine resin. These resins may be used alone or in combination of two or more. Further, an epoxy resin having two or more epoxy groups in one molecule is more desirable. Not only can the above-described roughened surface be formed, but also excellent in heat resistance, etc., even under heat cycle conditions, stress concentration does not occur in the metal layer, and peeling of the metal layer does not easily occur. Because.

Examples of the epoxy resin include cresol novolak type epoxy resin, bisphenol A type epoxy resin, bisphenol F type epoxy resin, phenol novolak type epoxy resin, alkylphenol novolak type epoxy resin, biphenol F type epoxy resin, and naphthalene type epoxy resin. Resin, dicyclopentadiene type epoxy resin, epoxidized product of condensate of phenols and aromatic aldehyde having phenolic hydroxyl group,
Triglycidyl isocyanurate, alicyclic epoxy resin and the like. These may be used alone or in combination of two or more. Thereby, it becomes excellent in heat resistance and the like.

In the resin film used in the present invention, the soluble particles are desirably substantially uniformly dispersed in the hardly-soluble resin. A roughened surface having unevenness with a uniform roughness can be formed, and even when a via or a through hole is formed in a resin film, the adhesion of a metal layer of a conductive circuit formed thereon can be secured. Because. Alternatively, a resin film containing soluble particles only in the surface layer forming the roughened surface may be used. Thereby, since the portions other than the surface layer of the resin film are not exposed to the acid or the oxidizing agent, the insulation between the conductor circuits via the interlayer resin insulating layer is reliably maintained.

In the above resin film, the amount of the soluble particles dispersed in the poorly soluble resin is preferably 3 to 40% by weight based on the resin film. If the amount of the soluble particles is less than 3% by weight, it may not be possible to form a roughened surface having desired irregularities. If the amount exceeds 40% by weight, the soluble particles may be dissolved using an acid or an oxidizing agent. In addition, there is a case where the resin film is melted to a deep portion of the resin film and the insulation between the conductor circuits via the interlayer resin insulating layer made of the resin film cannot be maintained, which may cause a short circuit.

The resin film desirably contains a curing agent and other components in addition to the soluble particles and the hardly-soluble resin. As the curing agent, for example,
Imidazole-based curing agents, amine-based curing agents, guanidine-based curing agents, epoxy adducts of these curing agents and microcapsules of these curing agents, and organic materials such as triphenylphosphine, tetraphenylphosphonium, and tetraphenylborate. Phosphine compounds and the like can be mentioned.

The content of the curing agent is desirably 0.05 to 10% by weight based on the resin film. 0.
If the amount is less than 05% by weight, the resin film is insufficiently cured, so that the degree of penetration of the acid or the oxidizing agent into the resin film is increased, and the insulating property of the resin film may be impaired. On the other hand, when the content exceeds 10% by weight, an excessive curing agent component may modify the composition of the resin, which may cause a decrease in reliability.

Examples of the other components include fillers such as inorganic compounds or resins which do not affect the formation of the roughened surface. As the inorganic compound, for example,
Examples of the resin include silica, alumina, and dolomite. Examples of the resin include a polyimide resin, a polyacryl resin, a polyamideimide resin, a polyphenylene resin, a melanin resin, and an olefin resin. By incorporating these fillers, the performance of the printed wiring board can be improved by matching the thermal expansion coefficient, improving heat resistance and chemical resistance, and the like.

Further, the above resin film may contain a solvent. As the solvent, for example, acetone,
Ketones such as methyl ethyl ketone and cyclohexanone,
Ethyl acetate, butyl acetate, cellosolve acetate, and aromatic hydrocarbons such as toluene and xylene. These may be used alone or in combination of two or more.

Next, a printed wiring board 110 according to a second embodiment of the present invention will be described with reference to FIG.
In the first embodiment described above, a BGA (ball grid array) is provided. The configuration of the printed wiring board according to the second embodiment is a PGA system in which connection is established via conductive connection pins 96 as shown in FIG.

In the first embodiment described above, the recesses 34 for accommodating the chip capacitors 20 are provided in the core substrate 30 by counterboring to accommodate the chip capacitors 20. In the second embodiment, the first resin substrate 30a having the through hole 30A and the second and third resin substrates 30 not having the through hole are provided.
b and 30c are bonded together via prepregs (adhesive plates) 33a and 33b to form a core substrate 30 having a recess 35 for housing the chip capacitor 20.
A plurality of chip capacitors 20 are housed in the housing 5.

The manufacturing process of the printed wiring board according to the second embodiment of the present invention will be described with reference to FIGS.

(1) A copper-clad laminate 31M in which copper foil 31b is laminated on both surfaces of a resin substrate 31a in which a core material such as a glass cloth having a thickness of 0.3 mm is impregnated with a BT (bismaleimide triazine) resin and cured. Is used as a starting material (FIG. 9A). By etching the copper foil 31b of the copper-clad laminate 31M into a pattern, the second and third resin substrates 30b and 30c having the conductor circuits 32 on both surfaces are formed. In addition, the first resin substrate 30a including the conductor circuit 32 is formed by forming a through hole 30A while etching in a pattern (FIG. 9B). Then, the third resin substrate 30c and the second resin substrate 30b are laminated via a prepreg (adhesive plate) 33b in which a core material such as glass cloth is impregnated with an epoxy resin. Similarly, the second resin substrate 3
Ob and the first resin substrate 30a in which the through-hole 30A is formed are laminated via a prepreg (adhesive plate) 33a in which the through-hole 33A is formed (FIG. 9C).

(2) Then, the first, second, and third resin substrates 30a, 30b, and 30c are integrated in a multilayer shape by pressing the superimposed substrates by using a hot press. The core substrate 30 having the concave portion 35 for accommodating is formed (FIG. 9D). Here, first, the epoxy resin (insulating resin) of the prepregs 33a, 33b is extruded to the surroundings by being pressed, and the epoxy resin is applied to the first, second, and third resin substrates 30a, 30b, 30c.
In close contact. Furthermore, by being heated at the same time as pressurization,
The epoxy resin is cured, and the first resin substrate 30a, the second resin substrate 30b, and the third resin substrate 30c are firmly adhered by interposing the prepregs 33a and 33b as an adhesive plate.

(3) Thereafter, a thermosetting or UV-curable adhesive material 36 is applied to the bottom surface of the recess 35 using a printing machine (FIG. 9E). At this time, potting may be performed in addition to the application.

(4) Next, a plurality of chip capacitors 2
0 is placed on the adhesive material 36 (see FIG. 10). By accommodating a plurality of chip capacitors 20 in the core substrate, high integration of the capacitors becomes possible.

(5) After that, a thermosetting resin is filled between the chip capacitors 20 in the concave portions 35 and heat-cured to form a resin layer 38 (see FIG. 10B). As the resin, epoxy, phenol, polyimide, and triazine are preferable, whereby the chip capacitor 20 in the recess 35 is fixed.
And the gap between the recess 35 and the wall surface of the recess 35 is filled.

(6) The thermosetting epoxy resin sheet is vacuum-press-laminated on the substrate 30 having undergone the above steps at a pressure of 5 kg / cm ² while the temperature is raised to a temperature of 50 to 150 ° C.
An interlayer resin insulating layer 40 made of an epoxy resin is provided (FIG. 10C).

(7) Next, the chip capacitor 20 is formed on the interlayer resin insulation layer 40 on the resin substrate 30a side by laser.
A via hole opening 42 reaching the first terminal 21 and the second terminal 22 is formed (FIG. 10D).

(8) Then, through holes 44 for through holes are formed in the core substrate 30 by using a drill or a laser (FIG. 10E). Thereafter, desmear treatment is performed using oxygen plasma. Alternatively, desmear treatment with a chemical such as permanganate may be performed. Subsequent steps are the same as (9) to (21) of the above-described first embodiment, and a description thereof will not be repeated.

Next, a printed wiring board according to a modification of the second embodiment of the present invention will be described with reference to FIG. The printed wiring board of the modified example is almost the same as the above-described second embodiment. However, in the second embodiment, only the chip capacitors 20 accommodated in the core substrate 30 are provided, but in a modified example, large-capacity chip capacitors 86 are mounted on the front and back surfaces.

The IC chip instantaneously consumes a large amount of power and performs complicated arithmetic processing. Here, in order to supply a large electric power to the IC chip side, in a modified example, a chip capacitor 20 and a chip capacitor 86 for power supply are provided on the printed wiring board. The effect of this chip capacitor will be described with reference to FIG.

FIG. 13 shows the voltage supplied to the IC chip on the vertical axis and the time on the horizontal axis. Here, the two-dot chain line C
Indicates voltage fluctuation of a printed wiring board without a power supply capacitor. When the power supply capacitor is not provided, the voltage greatly decreases. A broken line A indicates a voltage fluctuation of a printed wiring board having a chip capacitor mounted on the surface. Although the voltage does not drop much as compared with the two-dot chain line C, the rate-limiting power supply cannot be performed sufficiently because the loop length is long. That is, the voltage drops at the start of power supply. The two-dot chain line B indicates the voltage drop of the printed wiring board incorporating the chip capacitor described above with reference to FIG. Although the loop length can be shortened, the voltage fluctuates because a large-capacity chip capacitor cannot be accommodated in the core substrate 30. Here, the solid line E shows the voltage fluctuation of the printed wiring board of the modification in which the chip capacitor 20 in the core substrate described above with reference to FIG. 12 and the large-capacity chip capacitor 86 are mounted on the surface. By providing the chip capacitor 20 near the IC chip and the chip capacitor 86 having a large capacity (and a relatively large inductance), the voltage fluctuation is suppressed to the minimum.

In a modification of the second embodiment, the chip capacitor 20 completely peels off the coating layers (not shown) of the first and second electrodes 21 and 22 as shown in FIG. Thereafter, it is covered with a copper plating film 29. The first and second electrodes 21 and 22 covered with the copper plating film 29 are electrically connected to each other through via holes 60 made of copper plating. Here, the electrodes 21 and 22 of the chip capacitor are
It is made of metallized and has irregularities on the surface. Therefore, when the metal layer is used in a state where the metal layer is exposed, the resin may remain on the unevenness in the step of forming the non-through hole 43 in the connection layer 40. In this case, a connection failure between the first and second electrodes 21 and 22 and the via hole 60 may occur due to the resin residue. On the other hand, in the modified example, the surfaces of the first and second electrodes 21 and 22 are smoothed by the copper plating film 29, and the non-through holes 42 are formed in the interlayer resin insulating layer 40 coated on the electrodes. At this time, no resin residue remains, and the connection reliability with the electrodes 21 and 22 when the via hole 60 is formed can be improved.

Further, the electrode 2 on which the copper plating film 29 is formed
Since the via holes 60 are formed by plating on the first and second electrodes 22, the connectivity between the electrodes 21 and 22 and the via holes 60 is high.
No disconnection occurs between the via hole 60 and the via hole 60. No migration occurred, and no inconvenience occurred at the connection of the via hole of the capacitor.

The copper plating film 29 is obtained by peeling off the nickel / tin layer (coating layer) coated on the surface of the metal layer 26 at the stage of manufacturing the chip capacitor at the stage of mounting on the printed wiring board. Provide. Alternatively, it is also possible to cover the metal layer 26 with the copper plating film 29 directly at the stage of manufacturing the chip capacitor 20. That is, in the modified example, similarly to the first embodiment, after providing an opening to the copper plating film 29 of the electrode with a laser, a desmear process or the like is performed.
Via holes are formed by copper plating. Therefore, even if an oxide film is formed on the surface of the copper plating film 29, the oxide film can be removed by the laser and desmear treatments, so that proper connection can be established.

Further, as shown in FIG. 14B, the coating layer 2 of the first electrode 21 and the second electrode 22 of the chip capacitor 20 is formed.
From 8, the upper part can be exposed and housed in a printed wiring board, and can be electrically connected to the first electrode 21 and the second electrode 22 exposed from the covering layer 28. At this time, the main component of the metal exposed from the coating layer 28 is desirably Cu. This is because the connection resistance can be reduced.

Further, a roughened layer 23a is provided on the surface of the dielectric 23 made of ceramic of the chip capacitor 20. Therefore, the adhesion between the chip capacitor 20 made of ceramic and the interlayer resin insulation layer 40 made of resin is high, and the interlayer resin insulation layer 40 does not peel off at the interface even when the heat cycle test is performed. This roughened layer 23a can be subjected to a roughening treatment by polishing the surface of the chip capacitor 20 after firing, or before firing. In the modified example, the surface of the capacitor is subjected to a roughening treatment to improve the adhesion to the resin, but instead, the surface of the capacitor may be subjected to a silane coupling treatment.

Next, the configuration of the printed wiring board according to the third embodiment of the present invention will be described with reference to FIG. The configuration of the printed wiring board of the third embodiment is substantially the same as that of the above-described first embodiment. However, the core substrate 3
The chip capacitors 20 housed to 0 are different. FIG.
5 shows a plan view of the chip capacitor. FIG.
(A) shows a chip capacitor for multi-piece cutting before cutting, and a dashed line in the drawing shows a cutting line. In the printed wiring board of the first embodiment described above, the first electrode 21 and the second electrode 22 are arranged on the side edges of the chip capacitor as shown in the plan view of FIG. FIG. 15 (C)
Represents a chip capacitor for multi-piece cutting according to the third embodiment before cutting, and a dashed line in the drawing indicates a cutting line. In the printed wiring board according to the third embodiment, FIG.
As shown in the plan view, a first electrode 21 and a second electrode 22 are provided inside the side edge of the chip capacitor.

In the printed wiring board according to the third embodiment,
Since the chip capacitor 20 having the electrode formed inside the outer edge is used, a large-capacity chip capacitor can be used. Subsequently, a printed wiring board according to a first modification of the third embodiment will be described with reference to FIG. FIG.
Shows a plan view of the chip capacitor 20 housed in the core substrate of the printed wiring board according to the first modification. In the above-described first embodiment, a plurality of small-capacity chip capacitors are housed in the core substrate. In the first modification, a large-capacity large-format chip capacitor 20 is housed in the core substrate. Here, the chip capacitor 20 is connected to the first electrode 21.
, The second electrode 22, the dielectric 23, the first conductive film 24 connected to the first electrode 21, the second conductive film 25 connected to the second electrode 22, the first conductive film 24 and the first conductive film 24. 2 conductive film 25
And the connection electrodes 27 on the upper and lower surfaces of the chip capacitor not connected to the chip capacitor. The IC chip side and the daughter board side are connected via the electrodes 27.

In the printed wiring board of the first modification, a large-sized chip capacitor 20 is used, so that a large-capacity chip capacitor can be used. Further, since the large chip capacitor 20 is used, the printed wiring board does not warp even if the heat cycle is repeated.

A printed wiring board according to a second modification will be described with reference to FIG. FIG. 17A shows a chip capacitor before cutting for multi-cavity, in which a dashed line indicates a normal cutting line, and FIG. 17B is a plan view of the chip capacitor. . As shown in FIG. 17B, in the second modification, a plurality of (three in the example in the figure) multi-chip chip capacitors are connected and used in a large format.

In the second modification, a large-sized chip capacitor 20 is used, so that a large-capacity chip capacitor can be used. Further, since the large chip capacitor 20 is used, the printed wiring board does not warp even if the heat cycle is repeated.

In the above-described third embodiment, the chip capacitor is built in the printed wiring board. However, instead of the chip capacitor, it is also possible to use a plate-like capacitor in which a conductor film is provided on a ceramic plate. .

[0113]

As described above, according to the present invention,
Capacitors can be accommodated in the core board,
Since the distance between the IC chip and the capacitor is reduced, the loop inductance of the printed wiring board can be reduced. Further, since the core substrate is formed by laminating a plurality of resin substrates on which conductive circuits are formed, the wiring density in the core substrate is increased, and the number of interlayer resin insulating layers can be reduced.

Further, since the resin is filled between the core substrate and the capacitor, even if a stress caused by the capacitor or the like is generated, the stress is reduced and no migration occurs. Therefore, there is no influence such as peeling or melting of the connection portion between the electrode of the capacitor and the via hole. Therefore, desired performance can be maintained even if a reliability test is performed. Also, even when the capacitor is covered with copper, the occurrence of migration can be prevented.

[Brief description of the drawings]

FIG. 1 (A), (B), (C), (D), (E)
It is a manufacturing process figure of the printed wiring board concerning a 1st embodiment of the present invention.

FIG. 2 (A), (B), (C), (D), (E)
It is a manufacturing process figure of the printed wiring board concerning a 1st embodiment of the present invention.

FIGS. 3A, 3B, 3C, and 3D are manufacturing process diagrams of the printed wiring board according to the first embodiment of the present invention.

FIGS. 4A, 4B, 4C, and 4D are manufacturing process diagrams of the printed wiring board according to the first embodiment of the present invention.

FIGS. 5A and 5B are manufacturing process diagrams of the printed wiring board according to the first embodiment of the present invention.

FIGS. 6A and 6B are manufacturing process diagrams of the printed wiring board according to the first embodiment of the present invention.

FIG. 7 is a sectional view of the printed wiring board according to the first embodiment of the present invention.

8 is a cross-sectional view showing a state where an IC chip is mounted on the printed wiring board shown in FIG. 7 and attached to a daughter board.

FIG. 9 (A), (B), (C), (D), (E)
It is a manufacturing process figure of the printed wiring board concerning a 2nd embodiment of the present invention.

FIG. 10 (A), (B), (C), (D), (E)
FIG. 7 is a manufacturing process diagram of the printed wiring board according to the second embodiment of the present invention.

FIG. 11 is a sectional view showing a state in which an IC chip is mounted on a printed wiring board according to a second embodiment of the present invention.

FIG. 12 is a cross-sectional view showing a state in which an IC chip is mounted on a printed wiring board according to a modification of the second embodiment of the present invention.

FIG. 13 is a graph showing changes in supply voltage to an IC chip and time.

FIG. 14 is a cross-sectional view illustrating a chip capacitor according to a modification of the second embodiment of the present invention.

FIGS. 15A, 15B, 15C, and 15D are plan views of a chip capacitor of a printed wiring board according to a third embodiment.

FIG. 16 is a plan view of a chip capacitor of a printed wiring board according to a third embodiment.

FIG. 17 is a plan view of a chip capacitor of a printed wiring board according to a modification of the third embodiment.

[Explanation of symbols]

 Reference Signs List 20 chip capacitor 30 core substrate 30a first resin substrate 30b second resin substrate 30c third resin substrate 30A through hole 32 conductive circuit 33a, 33b bonding resin layer (bonding plate) 33A opening 34 recess 35 recess 36 adhesive material 38 resin Filler 40 Interlayer resin insulating layer 56 Through hole 58 Conductor circuit 60 Via hole 70 Solder resist layer 71U, 71D Opening 72 Nickel plating layer 74 Gold plating layer 76U, 76D Solder bump 80A, 80B Build-up wiring layer 90 IC chip 92E Ground Solder pad 92S Signal solder pad 92P Power solder pad 94E Ground solder pad 94S, signal solder pad 94P Power solder pad 95 Daughter board 96 Conductive connection pin 140 Interlayer resin insulation layer 158 Conductor circuit 160 Via Lumpur

 ──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Wang East Winter 1-1 Ibigawa-cho, Ibi-gun, Gifu Prefecture Inside the Ogaki-Kita Plant (72) Inventor Eiro Yabashi 1-1, Ibigawa-cho, Ibi-gun, Gifu Prefecture (72) Inventor Seiji Shirai 1-1 North of Ibigawa-cho, Ibi-gun, Gifu Prefecture F-term (reference) 5E317 AA21 AA24 CC25 CC31 CC51 CD27 GG11 GG17 5E346 AA38 AA60 CC04 CC08 CC09 CC32 CC37 DD22 DD47 EE06 EE08 FF03 FF15 FF17 GG15 HH06 HH33

Claims (18)

[Claims] 1. A printed wiring board comprising a resin insulating layer and a conductive circuit laminated on a core substrate, wherein the core substrate is formed by bonding a plurality of resin substrates on which a conductive circuit is formed, A printed wiring board, wherein a capacitor is housed in the core substrate. 2. A printed wiring board comprising a resin insulating layer and a conductive circuit laminated on a core substrate, wherein the core substrate is formed by bonding a plurality of resin substrates each having a conductive circuit formed thereon, A printed wiring board, wherein a capacitor is housed in a recess formed in the core substrate. 3. The printed wiring board according to claim 1, wherein the plurality of resin substrates are bonded together with an adhesive plate interposed therebetween. 4. The printed wiring board according to claim 3, wherein the adhesive plate is formed by impregnating a core material with a thermosetting resin. 5. The printed wiring board according to claim 1, wherein the resin substrate is formed by impregnating a resin into a core material. 6. The printed wiring board according to claim 1, wherein a plurality of the capacitors are provided. 7. The printed wiring board according to claim 1, wherein a capacitor is mounted on a surface of the printed wiring board. 8. The printed wiring board according to claim 7, wherein the capacitance of the chip capacitor on the front surface is equal to or larger than the capacitance of the chip capacitor in the inner layer. 9. The printed wiring board according to claim 7, wherein the inductance of the chip capacitor on the front surface is equal to or larger than the inductance of the chip capacitor in the inner layer. 10. The printed wiring according to claim 1, wherein a metal film is formed on the electrode of the capacitor, and the electrode on which the metal film is formed is electrically connected to the electrode by plating. Board. 11. The printed wiring board according to claim 10, wherein the metal film formed on the electrode of the capacitor is a plating film mainly composed of copper. 12. The capacitor according to claim 1, wherein a capacitor is bonded to the core substrate with an insulating adhesive, and the insulating adhesive has a smaller coefficient of thermal expansion than the core substrate. Printed wiring board. 13. The capacitor according to claim 1, wherein at least a part of the coating layer of the electrode of the capacitor is exposed, and the electrode exposed from the coating layer is electrically connected to the electrode by plating. 2. The printed wiring board according to item 1. 14. The printed wiring board according to claim 1, wherein a chip capacitor having an electrode formed inside an outer edge is used as the capacitor. 15. The printed wiring board according to claim 1, wherein a chip capacitor having electrodes formed in a matrix is used as said capacitor. 16. The printed wiring board according to claim 1, wherein a plurality of chip capacitors for multi-cavity are connected and used as said capacitor. 17. A method for manufacturing a printed wiring board, comprising at least the following steps (a) to (e): (a) a step of forming a conductor circuit on a plurality of resin substrates; (b) A step of laminating a plurality of the resin substrates via an adhesive plate; (c) a step of bonding the resin substrates to each other via the adhesive plate to form a core substrate; and (d) forming a recess in the core substrate. (E) accommodating a capacitor in the recess. 18. A method for manufacturing a printed wiring board, comprising at least the following steps (a) to (e): (a) forming a resin substrate provided with through holes and provided with a conductive circuit on the surface; (B) forming a resin substrate having no through-hole and having a conductor circuit disposed on the surface thereof; (c) bonding the resin substrate having the through-hole to the resin substrate not having the through-hole. (D) bonding the resin substrates to each other via the bonding plate to form a core substrate; (e) storing a capacitor in the through hole.