JP2013021269A - Wiring substrate with built-in component - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a wiring substrate with a built-in component capable of suppressing electrical interference among a plurality of components built in a cavity of a core substrate.SOLUTION: This invention relates to a wiring substrate with a built-in component provided with a core substrate and a wiring lamination part. A cavity 50 formed in the core substrate has a shape including more than five corners in planar view, a plurality of components C are disposed in the cavity 50, and a resin filler 20 is filled in a gap part between an inner wall surface of the core substrate in which the cavity 50 is formed and the plurality of components C. Concerning an X direction and a Y direction substantially orthogonal to each other in planar view, a component C (1) having an electric path along the Y direction, a component C (2) having an electric path along the X direction are respectively disposed, and electrical interference between both components can be suppressed.

Description

  The present invention relates to a component built-in wiring board in which a plurality of components are arranged in a cavity formed in a core substrate.

  Conventionally, a package is known in which a conductor substrate and an insulating layer are alternately laminated on both sides of a core substrate to constitute a wiring substrate, and an IC chip or the like is mounted on the wiring substrate. In recent years, due to the increase in the speed of IC chips and the increase in the number of terminals, when power is supplied to an IC chip from an external board via a wiring board, the malfunction of the IC chip due to the unstable power supply voltage or the influence of noise is a problem. Become. Therefore, it is effective to arrange a decoupling capacitor capable of removing noise along the electrical path for power supply on the wiring board. As a decoupling capacitor arranged in a wiring board, a structure in which a chip capacitor is arranged in a cavity provided in a core board has been proposed from the viewpoint of shortening a wiring distance to an IC chip (for example, a patent Reference 1). In the wiring board having such a structure, for example, by connecting a chip capacitor between the power supply wiring and the ground potential, noise propagating to the power supply wiring can be suppressed.

  In the conventional wiring board, a configuration for supplying a plurality of power supply voltages to the IC chip is generally employed. In this case, the wiring board needs to be provided with a decoupling capacitor individually for each of the plurality of power supply wirings connected to the IC chip. For example, FIG. 1 of Patent Document 1 discloses a structure in which two chip capacitors are arranged in a predetermined direction in a concave portion that is a hollow portion provided in a wiring board. Such a structure can also be applied to a wiring board in which a plurality of components other than chip capacitors are arranged in the cavity. In a wiring board having such a structure, it is desirable to efficiently arrange a plurality of components in a cavity having a predetermined size.

Japanese Patent No. 3522571

  In general, when a plurality of power supply voltages are supplied to an IC chip via a wiring board, a problem occurs in the operation of the IC chip due to noise being propagated by electrical interference between the power supply wirings. There is a fear. However, if the above-described conventional wiring board structure is adopted, it is inevitable that the influence of noise propagating between a plurality of components arranged in the cavity is increased. In other words, a plurality of components are arranged close to each other in the cavity of the wiring board, and the electrical paths are in parallel with each other, so that electrical interference is likely to occur. There is a problem that it is easy to propagate through a general route. In addition, if the distance between a plurality of components is increased, it is possible to reduce mutual electrical interference. However, in this case, it is necessary to provide a large cavity in the wiring board, which hinders the miniaturization of the wiring board. Come.

  Therefore, the present invention has been made to solve these problems, and even when a plurality of components are incorporated in the cavity of the core substrate, the electrical interference between the components is suppressed, and the device is small and reliable. An object of the present invention is to provide a wiring board with a built-in component.

  In order to solve the above problems, a component-embedded wiring board according to the present invention includes a core substrate in which a cavity is formed, a plurality of components arranged in the cavity, and one or both main surfaces of the core substrate. A component comprising: a wiring laminate portion in which insulating layers and conductor layers are alternately laminated; and a resin filler filled in a gap portion between the inner wall surface of the core substrate defining the cavity and the plurality of components In the built-in wiring board, the cavity is formed in a shape having five or more corners in a plan view, and the plurality of components are related to a first direction and a second direction substantially orthogonal to each other in a plan view, A first part having an electrical path along the first direction and a second part having an electrical path along the second direction are included.

  In order to solve the above problems, the component-embedded wiring board of the present invention is the component-embedded wiring board including the core substrate, the plurality of components, the wiring laminated portion, and the resin-filled layer. A first shape having an electrical path along the first direction is formed in an asymmetric shape with respect to at least one of a first direction and a second direction substantially orthogonal to each other in plan view. And a second part having an electrical path along the second direction.

  According to the component built-in wiring board of the present invention, the cavity is formed in the core substrate of the component built-in wiring board, and the electrical paths of the first and second components among the plurality of components are substantially orthogonal to each other. Thus, the gap between the inner wall surface of the core substrate and each component that defines the cavity is filled with a resin filler. Therefore, for example, even when two components arranged close to each other are connected to different power supply wirings, by making the electrical paths orthogonal to each other, the electrical paths can be compared with each other compared to when the electrical paths are parallel. Interference can be made sufficiently small, and propagation of noise between a plurality of components can be prevented to increase electrical reliability. In this case, the hollow portion is not a simple rectangle in plan view, but has a complicated planar shape having five or more corners, or an asymmetric shape with respect to the first direction or the second direction. Even if the longitudinal directions of the first and second parts whose orthogonal paths are orthogonal to each other are different, efficient arrangement is possible by adapting the planar shape of the cavity to the shape.

  The first and second parts are preferably formed using a material having higher rigidity than the core substrate and the resin filler. In this case, if a plurality of parts having the same shape are arranged in parallel, the rigidity decreases along a specific direction. However, according to the structure of the present invention, the planar shape of the cavity has various directions and a plurality of parts are arranged. Since these components have different directions, the overall strength of the component built-in wiring board can be increased without causing a decrease in rigidity along a specific direction.

  The outer shape of the hollow portion in plan view is not particularly limited, and can be constituted by, for example, a straight line group in the first direction and a straight line group in the second direction. Thereby, it is easy to adapt to the arrangement of components having a shape such as a rectangle in a plan view, and the processing for forming the cavity in the core substrate can be simplified.

  As the first and second components, components having a pair of terminal electrodes formed at both ends can be used. In this case, the direction in which the pair of terminal electrodes face each other matches the direction of the electrical path. At this time, the electrical connection of the first and second components is not particularly limited. For example, each terminal electrode is connected to a wiring having a different power supply voltage, and the other terminal electrode is placed close to each other. They can be placed and connected to a common potential. In such a connection form, terminal electrodes connected to a common potential do not cause a problem due to an electrical short, and may be arranged close to each other.

  In addition, as the first and second components, for example, chip components formed in a rectangular shape in plan view can be used. Since the pair of terminal electrodes at this time are formed on the two short sides of the rectangle, the electrical path coincides with the longitudinal direction along the two long sides of the rectangle. Examples of the first and second components include a capacitor, and a decoupling chip capacitor connected to a power supply voltage is a typical example.

  In addition, it is preferable that the width of the gap portion filled with the resin filler in the hollow portion is set to be shorter than the length of each short side of the first and second parts in a plan view. If the width of the gap is too wide, the region with low rigidity in the cavity will expand, reducing the strength of the wiring board. Conversely, if the width of the gap is too narrow, the coefficient of thermal expansion between the component and the core board will be reduced. It interferes with absorbing deformation caused by the difference.

  According to the present invention, when a plurality of components are built in the cavity formed in the core substrate of the component built-in wiring board, the electrical paths of the components are arranged so as to be substantially orthogonal, and the cavity is adapted to the arrangement. Since the planar shape of the part is formed, it is possible to suppress electrical interference between the adjacent parts in the cavity. As a result, it is possible to effectively prevent noise propagation and potential instability through the electrical path of each component, and to increase the electrical reliability of the wiring board. In addition, the planar shape of the hollow portion is a shape having five or more corners or an asymmetric shape with respect to either of two directions substantially orthogonal to each other. When the space between the parts is filled with a resin filler, high rigidity can be easily maintained, and the strength of the entire wiring board can be increased.

1 is a schematic cross-sectional structure diagram of a component built-in wiring board according to an embodiment. It is a figure which shows the example of the typical top view which looked at the inside of the cavity part formed in the core board | substrate of the wiring board of FIG. 1 by planar view. It is a figure which shows an example of the equivalent circuit containing the part of the electrical connection of the semiconductor chip of FIG. 1, and two chip capacitors. It is a figure which shows the planar structure when two chip capacitors are arrange | positioned in parallel in a cavity part as a comparative example for contrast with this embodiment. It is a figure which shows the planar structure when two chip capacitors are arrange | positioned similarly to FIG. 2 in a cavity part. It is a figure which shows the modification from which a connection form differs from this embodiment. It is a figure which shows the modification from which this embodiment differs in the planar shape of a cavity part. It is a figure which shows the modification which has arrange | positioned three chip capacitors in a cavity part. It is a figure which shows an example of the equivalent circuit corresponding to FIG. 3 in the case of arrange | positioning two chip inductors in a cavity part.

  Preferred embodiments of the present invention will be described below with reference to the drawings. However, the embodiment described below is an example of a form to which the technical idea of the present invention is applied, and the present invention is not limited by the content of the present embodiment.

  First, the structure of a component built-in wiring board embodying the present invention will be described. FIG. 1 shows a schematic cross-sectional structure diagram of a component built-in wiring board 10 (hereinafter simply referred to as a wiring board 10) of the present embodiment. As shown in FIG. 1, the wiring board 10 of the present embodiment includes a core substrate 11 made of, for example, an epoxy resin containing glass fiber, a buildup layer 12 (wiring laminated portion) on the upper surface side of the core substrate 11, It has a structure including a buildup layer 13 (wiring laminated portion) on the lower surface side of the substrate 11. In the core substrate 11, a cavity portion (cavity) 50 penetrating the central region is formed, and two chip capacitors C are embedded in the cavity portion 50. The core substrate 11 is formed with a plurality of through-hole conductors 21 penetrating the outer peripheral region in the stacking direction, and the inside of the through-hole conductor 21 is filled with a closing body 22 made of, for example, glass epoxy. A semiconductor chip 100 that is a semiconductor element is placed on the wiring substrate 10.

  Here, FIG. 2 shows an example of a schematic plan view in which the inside of the cavity 50 formed in the core substrate 11 of the wiring board 10 of FIG. 1 is viewed in plan view. In the lower part of FIG. 2, for convenience, coordinate axes in the X direction (first direction) and the Y direction (second direction) orthogonal to each other are shown. The X direction corresponds to the horizontal direction in FIG. 1, and the Y direction corresponds to the vertical direction in FIG. Inside the cavity 50, a chip capacitor C (1) that is a first component and a chip capacitor C (2) that is a second component are arranged. In the example of FIG. 2, the two chip capacitors C have the same shape, and are formed in a rectangle having a length L and a width W (L> W) in plan view. The two chip capacitors C have a pair of terminal electrodes T at both ends in the longitudinal direction (length L). Each terminal electrode T is formed from the side surface on one end side of the chip capacitor C to each part of the front surface and the back surface. One chip capacitor C (1) has a longitudinal direction arranged along the Y direction, and the other chip capacitor C (2) has a longitudinal direction arranged along the X direction. In the following description, an electrical path of each chip capacitor C is defined as a longitudinal direction in which a pair of terminal electrodes T are opposed to each other. Therefore, in the example of FIG. 2, one chip capacitor C (1) has an electrical path in the Y direction, and the other chip capacitor C (2) has an electrical path in the X direction. The paths are in a positional relationship orthogonal to each other. The arrangement of the chip capacitor C is related to electrical characteristics, and details will be described later.

  On the other hand, in the example of FIG. 2, the cavity 50 has a planar shape including six corners surrounded by six straight lines in plan view. Specifically, three straight lines having lengths X1, X2, and X3 in the X direction, three straight lines having lengths Y1, Y2, and Y3 in the Y direction, and each of the X and Y directions. There are six corners where the straight lines meet at 90 degrees. Here, it can be seen that there is a relationship of X1 = X2 + X3 and Y1 = Y2 + Y3. As can be seen from FIG. 2, the planar shape of the cavity 50 is asymmetric with respect to each of the X direction and the Y direction. The planar shape of the cavity 50 matches the planar shape of the inner wall surface 11a (FIG. 1) of the core substrate 11. As shown in FIG. 1, the height of the cavity 50 is substantially equal to the height of the two chip capacitors C in the stacking direction of the wiring substrate 10. Inside the hollow portion 50, the gap portion having the width G between the inner wall surface 11 a and the two chip capacitors C and the gap portion having the width G sandwiched between the two chip capacitors C are filled with the resin filler 20. It has been.

  The dimensions in the example of FIG. 2 are not particularly limited, but specific examples include, for example, X1 = 2.1 mm, X2 = 0.9 mm, X3 = 1.2 mm, Y1 = 1.4 mm, Y2 = 0.5 mm. Y3 = 0.9 mm, L = 1.0 mm, W = 0.5 mm, and G = 0.2 mm.

  The resin filler 20 is made of, for example, a polymer material made of a thermosetting resin such as an epoxy resin, and has a role of fixing each chip capacitor C in the cavity 50 formed in the core substrate 11. Specifically, the elastic deformation of the resin filler 20 acts to absorb deformation caused by the difference in thermal expansion coefficient between the core substrate 11 and each chip capacitor C. Each chip capacitor C has higher rigidity than the resin filler 20 and the core substrate 11, and the resin filler 20 has lower rigidity than the core substrate 11. Here, the rigidity of each of the chip capacitor C, the resin filler 20, and the core substrate 11 can be compared by evaluating the Young's modulus. As a method for measuring the Young's modulus, for example, a nanoindentation method can be used. As a measuring device, for example, “Nanoindenter II” manufactured by Nano Instruments Inc. can be used. In the example of FIG. 2, the gap portion filled with the resin filler 20 in the hollow portion 50 has a common width G. That is, the four sides of one chip capacitor C (1) and the four sides of the other chip capacitor C (2) are all surrounded by a gap having a width G. In the present embodiment, the gap portion in the hollow portion 50 is not limited to the uniform width G, but the width G of the gap portion is too large in consideration of the action of absorbing the above-described deformation by the resin filler 20. Even if it is too small, it is not preferable. In that case, assuming that the planar shape of the cavity 50 is a rectangle, the width G of the gap must be non-uniform when the longitudinal directions of the two chip capacitors C are arranged orthogonally. However, if the planar shape of FIG. 2 is adopted, the width G of the gap can be easily made uniform.

  Returning to FIG. 1, one build-up layer 12 includes a resin insulating layer 14 above the core substrate 11, a resin insulating layer 15 above the resin insulating layer 14, and a solder resist layer 16 above the resin insulating layer 15. Are laminated. A conductor layer 31 is formed on the upper surface of the resin insulating layer 14, and a plurality of terminal pads 33 are formed on the upper surface of the resin insulating layer 15. A plurality of via conductors 30 are provided at predetermined positions of the resin insulating layer 14 to connect the upper end electrode of the through-hole conductor 21 and the surface portion of the terminal electrode T of the chip capacitor C to the conductor layer 31 in the stacking direction. In addition, a plurality of via conductors 32 that connect and conduct the conductor layer 31 and the plurality of terminal pads 33 in the stacking direction are provided at predetermined positions of the resin insulating layer 15. The solder resist layer 16 is opened at a plurality of locations to expose a plurality of terminal pads 33, and a plurality of solder bumps 34 are formed there. Each solder bump 34 is connected to each pad 101 of the semiconductor chip 100 placed on the wiring substrate 10.

  The other buildup layer 13 is formed by laminating a resin insulation layer 17 below the core substrate 11, a resin insulation layer 18 below the resin insulation layer 17, and a solder resist layer 19 below the resin insulation layer 18. Being done. A conductor layer 41 is formed on the lower surface of the resin insulating layer 17, and a plurality of BGA pads 43 are formed on the lower surface of the resin insulating layer 18. A plurality of via conductors 40 are provided at predetermined positions of the resin insulating layer 17 to connect and connect the lower end electrode of the through-hole conductor 21 and the back surface portion of the terminal electrode T of the chip capacitor C to the conductor layer 41 in the stacking direction. A plurality of via conductors 42 are provided at predetermined positions of the resin insulating layer 18 to connect and connect the conductor layer 41 and the plurality of BGA pads 43 in the stacking direction. The solder resist layer 19 is opened at a plurality of locations to expose a plurality of BGA pads 43 to which a plurality of solder balls 44 are connected. The plurality of solder balls 44 have a structure that can be electrically connected to an external substrate (not shown).

  FIG. 3 shows an example of an equivalent circuit including a part of electrical connection between the semiconductor chip 100 of FIG. 1 and two chip capacitors C. As shown in FIG. 3, the power supply voltage V <b> 1, the power supply voltage V <b> 2, and the ground potential GN are supplied to the semiconductor chip 100 via the wiring substrate 10 from the external base material. Among these, the power supply voltages V1 and V2 of the two systems may have different voltage values, or may be equal to each other. One chip capacitor C (1) is used as a decoupling capacitor for the power supply voltage V1, and the other chip capacitor C (2) is used as a decoupling capacitor for the power supply voltage V2.

  Specifically, the pair of terminal electrodes T of the chip capacitor C (1) is connected to the power supply voltage V1 and the ground potential GN, and the pair of terminal electrodes T of the chip capacitor C (2) is connected to the power supply voltage V2 and the ground potential. Connected to GN. Each of the power supply voltages V 1 and V 2 and the ground potential GN is electrically connected to the pad 101 and the solder ball 44 of the semiconductor chip 100. In FIG. 1, the electrical connections in this case are as follows: pad 101, solder bump 34, terminal pad 33, via conductor 32, conductor layer 31, via conductor 30, terminal electrode T of chip capacitor C, via conductor 40, conductor layer 41. , Via conductors 42, BGA pads 43, and solder balls 44 in this order. Here, since the two power supply voltages V1 and V2 are supplied to different circuit portions in the semiconductor chip 100, if noise propagation or signal leakage occurs due to mutual electrical interference, circuit operation There is a risk of inconvenience. In order to deal with such a problem, in the present embodiment, as described below, the influence of the electrical interference is suppressed by an effect based on the arrangement of the chip capacitor C in the cavity 50.

  Hereinafter, specific effects based on the arrangement of the chip capacitor C of the present embodiment will be described with reference to FIGS. 4 and 5. 4 shows, as a comparative example, a planar structure when two chip capacitors C are arranged in parallel in the cavity 50 for comparison with the present embodiment, and FIG. 3 shows a planar structure when the chip capacitor C is arranged in the same manner as in FIG. 4 and 5 show the coordinate axes in the X direction and the Y direction, as in FIG. Here, it is assumed that the cavity 50 has a planar shape including a plurality of straight lines along the X direction and a plurality of straight lines along the Y direction.

  First, in FIG. 4, the planar shape of the cavity 50 is a rectangle composed of two sides in the X direction and two sides in the Y direction, which is a typical planar shape that has been conventionally employed. The two chip capacitors C (3) and C (4) arranged in the cavity 50 are both arranged in the longitudinal direction along the X direction. Then, a pair of terminal electrodes T of one chip capacitor C (3) are connected to the power supply voltage V1 and the ground potential GN, respectively, and a pair of terminal electrodes T of the other chip capacitor C (4) are connected to the power supply voltage V2. Each is connected to the ground potential GN. That is, an electrical path P (3) that connects a pair of terminal electrodes T of one chip capacitor C (3) and an electrical path P (that connects a pair of terminal electrodes T of the other chip capacitor C (4). 4) are all along the X direction. In addition, the direction of the arrow of each electric path | route P (3) and P (4) shall show the direction through which an electric current flows.

  According to the planar structure of FIG. 4, since the electrical paths P (3) and P (4) are arranged in the same direction in a close state, the chip capacitors C (3) and C (4) The electrical interference between them increases. In other words, the mutual inductance increases between the two electrical paths P (3) and P (4) arranged in the same direction, and the effect becomes more noticeable as the frequency increases. Therefore, when the chip capacitors C (3) and C (4) are used as decoupling capacitors for different power supply voltages V1 and V2, respectively, due to electrical interference (mutual inductance) in the cavity 50, the power supplies V1 and V2 There is a risk of noise propagation between the wirings and instability of the power supply voltage.

  On the other hand, in FIG. 5, the planar shape of the cavity 50 is composed of three sides in the X direction and three sides in the Y direction, which is the planar shape shown in FIG. The two chip capacitors C (1) and C (2) arranged in the cavity 50 are arranged so that their longitudinal directions are orthogonal to each other as in FIG. The pair of terminal electrodes T of one chip capacitor C (1) is connected between the power supply voltage V1 and the ground potential GN, and the pair of terminal electrodes T of the other chip capacitor C (2) is connected to the power supply voltage V2. And the ground potential GN. That is, the electrical path P (1) connecting the pair of terminal electrodes T of one chip capacitor C (1) is along the Y direction, and the electric path connecting the pair of terminal electrodes T of the other chip capacitor C (2). The target path P (2) is along the X direction.

  Therefore, according to the planar structure of FIG. 5, the electrical paths P (1) and P (2) are close to each other, but are arranged orthogonal to each other, and therefore, compared to FIG. 4, the chip capacitor C (1 ), And the electrical interference between C (2) becomes relatively small. In other words, the mutual inductance between the electrical paths P (1) and P (2) that are orthogonal to each other is sufficiently small even when the frequency is high. Therefore, when the chip capacitors C (1) and C (2) are used as decoupling capacitors of different power supply voltages V1 and V2, respectively, unlike FIG. 4, electrical interference (mutual inductance) in the cavity 50 is suppressed. Therefore, it is possible to effectively prevent the propagation of noise between the wirings of the power supply voltages V1 and V2 and the instability of the power supply voltage.

  Further, according to the planar structure of FIG. 5, it is possible to suppress a decrease in rigidity due to the portion of the resin filler 20 filled in the gap portion in the cavity 50 as compared with the planar structure of FIG. 4. That is, in FIGS. 4 and 5, the rigidity of the resin filler 20 buried in the gap between the cavity 50 and the two chip capacitors C is lowered, but the cavity 50 in FIG. 4 is rectangular. On the other hand, since the cavity 50 in FIG. 5 has a complicated planar shape having a relatively large number of straight lines and corners, the structure is advantageous for maintaining high rigidity particularly when stress is applied in the stacking direction. Can be realized. Thereby, the effect which prevents the crack in the vicinity of the cavity part 50 of the wiring board 10 and a crack is acquired. The difference in the planar shape of the cavity 50 in FIGS. 4 and 5 is derived from the fact that the longitudinal directions of the two chip capacitors C are arranged not in the same direction but perpendicularly as described above.

  The characteristic structure of the wiring board 10 to which the present invention is applied has been described above, but the planar structure shown in the present embodiment is an example, and the present invention is applied to various modifications described below. Can do. FIG. 6 shows a modification in which the connection form is different from the present embodiment. In FIG. 6, the planar shapes of the cavity 50 and the two chip capacitors C are the same as those in FIG. 5, but the electrical connection to each chip capacitor C is changed. Specifically, the terminal electrode Ta of one chip capacitor C and the terminal electrode Tb of the other chip capacitor C are connected to the ground potential GN. That is, the side of the two chip capacitors C that is connected to the common ground potential GN is the terminal electrodes Ta and Tb that are close to each other. The electrical paths P (1) and P (2) are in the opposite direction from the case of FIG. Wirings connected to the terminal electrodes Ta and Tb are electrically connected at predetermined positions in the wiring board 10. With the planar structure of FIG. 6, even if the terminal electrodes Ta and Tb on the side connected to the common potential are short-circuited, there is no problem in operation, so that the interval between two chip capacitors C can be shortened.

  FIG. 7 shows a modification in which the planar shape of the cavity 50 is different from that of the present embodiment. That is, the cavity 50 in FIG. 5 has a planar shape having six straight lines and six corners, whereas the cavity 50 in FIG. 7 has a planar shape having eight straight lines and eight corners. It has become. In this case, with respect to one chip capacitor C (1), the other chip capacitor C (2) is arranged so that the longitudinal direction thereof is along the substantially central portion of the chip capacitor C (1). According to the modified example of FIG. 7, it is possible to realize a structure that is advantageous for maintaining high rigidity by the amount of the straight line and the corners of the planar shape of the cavity 50 increased.

  Note that the cavity 50 of the present embodiment is not formed in a simple planar shape such as a rectangle, but has five or more corners or a planar shape asymmetric with respect to either the X direction or the Y direction. It is a condition to form. Therefore, the present invention is not limited to the planar shape shown in FIGS. 5 and 7 and can be formed in various planar shapes. As long as this condition is satisfied, the planar shape constituting the cavity 50 may include a straight line in a direction other than the X direction / Y direction, or may partially include a curve. Further, chamfering (R chamfering, C chamfering) may be performed on each of the planar corners forming the cavity 50.

  FIG. 8 shows a modification in which three chip capacitors C are arranged in the cavity 50. That is, the chip capacitor C (3) is added to the two chip capacitors C (1) and C (2) in FIG. In the modified example of FIG. 8, chip capacitors C (2) and C (3) are symmetrically arranged on both sides of the chip capacitor C (1), and the electrical paths P (2) and P (3) are respectively arranged. Are in the same direction. However, since the chip capacitors C (2) and C (3) on both sides are not adjacent to each other and are separated from each other, the electrical interference between them is reduced. In this case, the two adjacent chip capacitors C (1) and C (2) or the two adjacent chip capacitors C (1) and C (3) are as described in this embodiment. Since the electrical paths P are orthogonal to each other, the effect of suppressing electrical interference can be enjoyed. Note that the present invention is not limited to the modification of FIG. 8, and even when the chip capacitors C are further increased, the present invention can be applied as long as the electrical paths P of adjacent chip capacitors C are orthogonal.

  Furthermore, the component disposed in the cavity 50 is not limited to the chip capacitor C, and for example, a chip inductor may be used. FIG. 9 shows an example of an equivalent circuit corresponding to FIG. 3 when two chip inductors L are arranged in the cavity 50. FIG. 9 shows a case where two chip inductors L are used as choke coils for two power supply voltages V1 and V2. That is, one chip inductor L (1) is inserted in series with the wiring of the power supply voltage V1, and the other chip inductor L (2) is inserted in series with the wiring of the power supply voltage V2. In the plan view of the cavity 50 in this case, the two chip capacitors C in FIG. Even when the present invention is applied to the equivalent circuit of FIG. 9, the effect of suppressing the electrical interference between the chip inductors L in the cavity 50 is the same.

  Even when the chip capacitor C and the chip inductor L are mixed in the cavity 50, the present invention can be applied according to the same arrangement. Further, the components disposed in the cavity 50 are not limited to the chip capacitor C and the chip inductor L, and various components can be used.

  The wiring board 10 of the present embodiment having the above structure can be manufactured using a known method except for the structure of the cavity 50. In addition, regarding formation of the cavity part 50, it can process using a router like the case where a planar shape is a rectangle. In this case, the cavity 50 having a complicated planar shape can be formed by controlling the movement of the router in the X direction and the Y direction so as to conform to the planar shape of the cavity 50.

  The contents of the present invention have been specifically described above based on the present embodiment, but the present invention is not limited to the above-described embodiment, and various modifications can be made without departing from the scope of the present invention. For example, in the present embodiment, the case where the present invention is applied to the wiring substrate 10 on which the semiconductor chip 100 is mounted has been described. However, as long as a plurality of components are built in the cavity 50, other than the semiconductor chip 100. The present invention can be applied to the wiring board 10 on which components are placed. In the present embodiment, the case where an epoxy resin containing glass fiber is used for the core substrate has been described. However, when a metal plate or photosensitive glass is used for the core substrate, the through-hole conductor 21 is formed. It is also possible to simultaneously form the hole and the cavity 50 containing a plurality of components by etching. The contents of the present invention are not limited by the above-described embodiment in other respects, and can be appropriately changed without being limited to the contents disclosed in the above-described embodiment as long as the effects of the present invention can be obtained. is there.

DESCRIPTION OF SYMBOLS 10 ... Component built-in wiring board 11 ... Core board | substrates 12, 13 ... Build-up layers 14, 15, 17, 18 ... Resin insulation layers 16, 19 ... Solder resist layer 20 ... Resin filler 21 ... Through-hole conductor 22 ... Closure body 30 , 32, 40, 42 ... via conductors 31, 41 ... conductor layer 33 ... terminal pad 34 ... solder bump 43 ... BGA pad 44 ... solder ball 50 ... cavity 100 ... semiconductor chip C ... chip capacitor L ... chip inductor

Claims (9)

A core substrate in which a cavity is formed;
A plurality of components disposed in the cavity;
A wiring laminated portion in which insulating layers and conductor layers are alternately laminated on one or both main surface sides of the core substrate;
A resin filler filled in a gap portion between the inner wall surface of the core substrate and the plurality of components defining the hollow portion;
In the component built-in wiring board with
The cavity is formed in a shape having five or more corners in plan view,
The plurality of parts are related to a first direction and a second direction that are substantially orthogonal to each other in plan view, and a first part having an electrical path along the first direction, and the second direction. A second component having an electrical path
A wiring board with a built-in component. A core substrate in which a cavity is formed;
A plurality of components disposed in the cavity;
A wiring laminated portion in which insulating layers and conductor layers are alternately laminated on one or both main surface sides of the core substrate;
A resin filler filled in a gap portion between the inner wall surface of the core substrate and the plurality of components defining the hollow portion;
In the component built-in wiring board with
The hollow portion is formed in an asymmetric shape with respect to at least one of the first direction and the second direction substantially orthogonal to each other in plan view,
The plurality of parts includes a first part having an electrical path along the first direction and a second part having an electrical path along the second direction.
A wiring board with a built-in component.   The component built-in wiring board according to claim 1, wherein the first and second components are formed using a material having higher rigidity than the core substrate and the resin filler.   4. The cavity according to claim 1, wherein an outer shape of the hollow portion is configured by a straight line group in the first direction and a straight line group in the second direction. 5. Component built-in wiring board. The first component has a pair of terminal electrodes formed at both ends in the first direction,
The second component has a pair of terminal electrodes formed at both ends in the second direction.
The component built-in wiring board according to any one of claims 1 to 4, wherein the wiring board has a built-in component.   One electrode of the pair of terminal electrodes of the first component and one electrode adjacent to the first component of the pair of terminal electrodes of the second component are common. The component built-in wiring board according to claim 5, wherein the component built-in wiring board is connected to a potential. The first component is formed in a rectangular shape whose outer shape in plan view has two long sides in the first direction and two short sides in the second direction,
The second component is formed in a rectangular shape in which a plan view has two short sides in the first direction and two long sides in the second direction.
The component built-in wiring board according to claim 6.   8. The component built-in wiring board according to claim 7, wherein, in the hollow portion, the width of the gap is smaller than the length of each short side of the first and second components in a plan view. The component built-in wiring board according to claim 1, wherein the first and second components are capacitors.