JP6425632B2 - Printed board - Google Patents

Description

  The present invention relates to a printed circuit board having a noise filter.

  A noise filter is mounted on the printed circuit board in order to remove electromagnetic noise in a high frequency band leaking from a circuit element such as an LSI (Large Scale Integrated circuit) or an IC (Integrated Circuit). FIG. 7 is a view showing an example of a conventional noise filter mounted on the printed circuit board 100. As shown in FIG. On the printed circuit board 100, a circuit element 101, a connector circuit 102, a bypass capacitor 104, a power supply wiring pattern 111, and a ground wiring pattern 112 are mounted.

  As shown in FIG. 7, one end of the power supply wiring pattern 111 is connected to the circuit element 101, and the other end of the power supply wiring pattern 111 is connected to the external power supply 103 via the connector circuit 102. One end of the bypass capacitor 104 is connected to the power supply wiring pattern 111 via the lead wiring 113, and the other end of the bypass capacitor 104 is connected to the ground wiring pattern 112 via the lead wiring 114. If the high frequency electromagnetic noise generated in the circuit element 101 propagates to the external power supply 103, for example, the power supply voltage fluctuates to cause malfunction of the circuit element 101 or another circuit element receiving power supply from the external power supply 103 (not shown) The problem of causing the malfunction of) may occur. The bypass capacitor 104 functions as a noise filter for high frequency electromagnetic noise, and can bypass high frequency electromagnetic noise propagating through the power supply wiring pattern 111 to the ground wiring pattern 112. This makes it possible to improve the power supply quality.

  However, parasitic inductance exists in the bypass capacitor 104. Since the bypass performance of the bypass capacitor 104 is degraded by this parasitic inductance, there is a problem that high frequency electromagnetic noise leaking to the external power supply 103 side can not be sufficiently reduced. For this problem, for example, the prior art disclosed in Patent Document 1 (Japanese Patent Application Laid-Open No. 2005-303193) is known. Since the chip type capacitor array disclosed in Patent Document 1 includes a plurality of capacitors connected in parallel with the common external electrode, the parasitic inductance of the chip type capacitor array itself can be reduced.

JP 2005-303193 A (for example, FIGS. 1 to 4 and paragraphs 0020 to 0030)

  However, the prior art of Patent Document 1 can not suppress the deterioration of the bypass performance due to the parasitic inductance of the wiring used for mounting the bypass capacitor.

  In view of the above, it is an object of the present invention to provide a printed circuit board capable of suppressing the performance deterioration of a bypass circuit including a capacitor.

  A printed circuit board according to an aspect of the present invention is a printed circuit board having a structure in which a first wiring layer and a second wiring layer are stacked via an insulating layer, and as a part of the first wiring layer The formed first wiring line and second wiring line, and the first wiring layer are arranged, and have a pair of electrode terminals, and one of the pair of electrode terminals is the one described above. A bypass capacitor electrically connected to one end of the first wiring line, a third wiring line formed as a part of the second wiring layer, and the insulating layer; A first interlayer connection hole for electrically connecting the one end of the first wiring line to one end of the third wiring line, and a hole formed through the insulating layer, and one end of the second wiring line And a second interlayer for electrically connecting the second wiring to the other end of the third wiring line The first wiring line and the second wiring line extend in parallel to each other so as to form mutual inductance by magnetic coupling, and the first wiring The one end of the line is opposite to the other end of the second wiring line, and the one end of the second wiring line is opposite to the other end of the first wiring line. I assume.

  A printed circuit board according to another aspect of the present invention is a printed circuit board having a structure in which a first wiring layer and a second wiring layer are stacked via an insulating layer, and is a part of the first wiring layer. Disposed in the second wiring layer, and a first wiring line and a second wiring line formed as a second wiring line, a third wiring line formed as a part of the second wiring layer, and A bypass capacitor having one of the pair of electrode terminals electrically connected to one end of the third wiring line, and the insulating layer formed through the bypass capacitor. A first interlayer connection hole for electrically connecting one end of the first wiring line to the one end of the third wiring line, and a hole formed through the insulating layer, and one end of the second wiring line Layer electrically connecting the second portion to the other end of the third wiring line And a connection hole, wherein the first wiring line and the second wiring line extend in parallel to each other so as to form mutual inductance by magnetic coupling, and the first wiring The one end of the line is opposite to the other end of the second wiring line, and the one end of the second wiring line is opposite to the other end of the first wiring line. I assume.

  According to the present invention, the first wiring line and the second wiring line are connected in series via the third wiring line, and are mutually opposed and parallel to each other so as to form mutual inductance by magnetic coupling. Extends to The negative inductance that appears equivalently to this mutual inductance can cancel the parasitic inductance of the bypass circuit including the bypass capacitor. Therefore, the performance deterioration of the bypass circuit can be suppressed without adding a new electronic component.

It is a figure which shows roughly an example of the cross-section of the multilayer printed circuit board of Embodiment 1 which concerns on this invention. (A), (B), (C) is a top view of the wiring layer which comprises the multilayer printed circuit board of Embodiment 1. FIG. (A) is a figure which shows the mutual induction circuit containing a pair of parasitic inductors, (B) is a figure which shows T-type equivalent circuit of this mutual induction circuit. FIG. 2 is a view schematically showing the main part of the equivalent circuit of the multilayer printed circuit board of the first embodiment. (A), (B), (C) is a top view of the wiring layer which comprises the multilayer printed circuit board of Embodiment 2 which concerns on this invention. It is a figure which shows an example of the arrangement | positioning range of the magnetic body 23 of Embodiment 3 which concerns on this invention. It is a figure which shows an example of the conventional noise filter mounted in the printed circuit board.

  Hereinafter, various embodiments according to the present invention will be described in detail with reference to the drawings. In addition, the component which attached | subjected the same code | symbol in drawing shall have the same function and the same structure.

Embodiment 1
FIG. 1 is a view schematically showing an example of the cross-sectional structure of a multilayer printed circuit board 1 according to a first embodiment of the present invention, and FIGS. 2 (A), (B) and (C) show the multilayer printed circuit board. FIG. 2 is a plan view of a wiring layer constituting 1; FIGS. 2A, 2B, and 2C show planar configurations of the upper wiring layer WL1, the intermediate wiring layer WL2, and the lower wiring layer WL3 when viewed from the same direction.

  A multilayer printed circuit board 1 shown in FIG. 1 is formed between an upper wiring layer WL1 which is a first wiring layer, a lower wiring layer WL3 which is a second wiring layer, and the upper wiring layer WL1 and the lower wiring layer WL3. And an intermediate wiring layer WL2 arranged. A first insulating layer I1 intervenes between the upper wiring layer WL1 and the intermediate wiring layer WL2, and a second insulating layer I2 intervenes between the intermediate wiring layer WL2 and the lower wiring layer WL3. The multilayer printed board 1 has a structure in which an upper wiring layer WL1, a first insulating layer I1, an intermediate wiring layer WL2, a second insulating layer I2, and a lower wiring layer WL3 are stacked in the thickness direction (vertical direction in the drawing). There is. The first insulating layer I1 and the second insulating layer I2 are made of an electrically insulating material (for example, a resin material). The first insulating layer I1 and the second insulating layer I2 can constitute the insulating layer of the present invention.

  As shown in FIGS. 2A to 2C, in the multilayer printed circuit board 1, vias Ha, Hb, Hc, which are interlayer connection holes penetrating both the first insulating layer I1 and the second insulating layer I2. Hd, He are formed. For example, a conductive paste is filled in the vias Ha, Hb, Hc, Hd, and He, or a metal layer such as copper is formed by electroless plating, so that the vias Ha, Hb, Hc, Hd, He has conductivity.

  The vias Ha and Hb formed in the vicinity of the central portion of the multilayer printed circuit board 1 conduct to both the upper wiring layer WL1 and the lower wiring layer WL3, but do not conduct to the intermediate wiring layer WL2. Therefore, the vias Ha and Hb electrically connect the upper wiring layer WL1 and the lower wiring layer WL3, but between the upper wiring layer WL1 and the intermediate wiring layer WL2 and the intermediate wiring layer WL2. There is no electrical connection between the lower wiring layer WL3. The other vias Hc, Hd, He are electrically connected to both the upper wiring layer WL1 and the intermediate wiring layer WL2, but are not electrically connected to the lower wiring layer WL3. Therefore, vias Hc, Hd, He electrically connect between upper interconnection layer WL1 and intermediate interconnection layer WL2, but do not electrically connect intermediate interconnection layer WL2 and lower interconnection layer WL3. .

  The upper wiring layer WL1 is formed on the outer surface, ie, the upper surface, of both surfaces in the thickness direction of the first insulating layer I1. As shown in FIG. 2A, the upper wiring layer WL1 is electrically connected to the circuit element 10, which is an electronic component such as an LSI or IC, and the external power supply 12 such as a DC-DC converter or an on-vehicle battery. The connector circuit 11 and the bypass capacitor 13 for removing electromagnetic noise are provided.

  Further, as a wiring pattern constituting upper wiring layer WL1, power supply wiring pattern W1 connected to the power supply terminal of circuit element 10, and power supply wiring pattern W2 electrically connected to external power supply 12 through connector circuit 11 A lead wire W3 electrically connecting one electrode terminal of the bypass capacitor 13 to the power supply wiring pattern W1, a wire W4 electrically connecting the other electrode terminal of the bypass capacitor 13 to the via Hc, and the circuit element 10 A ground wiring W5 electrically connecting the ground terminal to the via Hd and a ground wiring W6 electrically connecting the ground terminal of the connector circuit 11 to the via He are formed. The power supply wiring patterns W1 and W2, the lead wiring W3, the wiring W4 and the ground wirings W5 and W6 may be made of a conductor such as copper foil.

  The intermediate wiring layer WL2 is formed between the first insulating layer I1 and the second insulating layer I2 as shown in FIG. As shown in FIG. 2B, the intermediate wiring layer WL2 has a ground conductor surface 22 substantially on the entire surface excluding the regions of the vias Ha, Hb, Hc, Hd, and He. It is electrically grounded. The ground conductor surface 22 may be made of a conductor such as copper foil. The negative terminal of the external power supply 12 is connected to the ground conductor surface 22 through the connector circuit 11, the ground wiring W6 and the via He.

  Lower interconnection layer WL3 is formed on the outer surface, that is, the lower surface of second insulating layer I2, as shown in FIG. As a wiring pattern constituting the lower wiring layer WL3, as shown in FIG. 2C, a wiring line W9 for electrically connecting the vias Ha and Hb is formed. The wiring line W9 may be made of a conductor such as copper foil.

  Although the wiring line W9 has a bent portion which is bent at a right angle as shown in FIG. 2C, the present invention is not limited to this. Instead of such a wiring line W9, a linear wiring line or a circular or oval wiring line may be employed.

  Referring to FIG. 2A, in the upper wiring layer WL1, one power supply wiring pattern W1 includes a first wiring line W1a formed at a position facing and in proximity to the other power supply wiring pattern W2. The other power supply wiring pattern W2 includes a second wiring line W2a formed at a position facing and in proximity to one power supply wiring pattern W1. The first and second wiring lines W1a and W2a (hereinafter referred to as "proximity wiring lines W1a and W2a") are formed to face each other and to extend in parallel to each other. The wiring line W9 of the lower wiring layer WL3 is a third wiring line for connecting the adjacent wiring lines W1a and W2a in series.

  As shown in FIG. 2A, the left end of the adjacent wiring line W1a is electrically connected to the via Ha. As a result, as shown in FIG. 2C, the proximity wiring line W1a is electrically connected to the left end portion of the wiring line W9 of the lower wiring layer WL3 through the via Ha. The right end portion of the other adjacent wiring line W2a is electrically connected to the via Hb as shown in FIG. 2 (A). As a result, the adjacent wiring line W2a is electrically connected to the other end on the right side of the wiring line W9 of the lower wiring layer WL3 through the via Hb. Therefore, the end portions of the adjacent wiring lines W1a and W2a are connected in series via the via Ha, the wiring line W9, and the via Hb. Therefore, the directions of the currents flowing through the adjacent wiring lines W1a and W2a are the same. Further, the directions of the magnetic flux generated in the close wiring lines W1a and W2a due to the parasitic inductance are also substantially the same.

  Further, as shown in FIG. 2A, the left end portion of the close wiring line W1a is electrically connected to one electrode terminal of the bypass capacitor 13 through the lead wiring W3. The other electrode terminal of the bypass capacitor 13 is electrically connected to the via Hc via the wire W4. Accordingly, the other electrode terminal is electrically connected to the ground conductor surface 22 of the intermediate wiring layer WL2 through the via Hc. On the other hand, the other end on the right side of the close wiring line W1a is a portion facing the one end on the right side of the close wiring line W2a (the part connected to the via Hb) although not explicitly shown in FIG. It is electrically connected to the power supply terminal of the circuit element 10 through the other wiring portion of the line W1. Further, the other end on the left side of the close wiring line W2a is also a portion facing the one end on the left side of the close wiring line W1a (a portion connected to the via Ha) although not explicitly shown in FIG. It is electrically connected to the external power supply 12 through the other wiring portion of the line W 2 and the connector circuit 11.

The noise filter of the present embodiment is configured to include close wiring lines W1a and W2a and a bypass capacitor 13. The adjacent wiring lines W1a and W2a have a pair of parasitic inductors magnetically coupled to each other to cause mutual induction. FIG. 3A schematically shows a mutual induction circuit including the parasitic inductor 41 of the close wiring line W1a and the parasitic inductor 42 of the close wiring line W2a, and FIG. 3B shows the mutual induction circuit. Is a diagram showing a T-type equivalent circuit of FIG. When currents i ₁ and i ₂ flow into the parasitic inductors 41 and 42 from the nodes a 1 and a 2, respectively, mutual inductance -M is formed between the parasitic inductors 41 and 42. Assuming that the nodes b1 and b2 have a common potential, the mutual induction circuit comprises three inductors 51, 52, 53 having three inductances L1 + M, L2 + M, -M as shown in FIG. 3B. It can be considered as an equivalent circuit. This type of equivalent circuit is called a T-type equivalent circuit.

Here, when adjacent wiring lines W1a and W2a face each other at a distance d (unit: m) and line lengths of both adjacent wiring lines W1a and W2a are R (unit: m), adjacent wiring lines W1a , W2a (unit: H = Wb / A) is given by, for example, the following approximate expression (1).
M = (μ ₀ / (2π)) × R × (ln (2 R / d) −1) (1)

Here, μ ₀ is the permeability of vacuum (= 4π × 10 ⁻⁷ H / m).

FIG. 4 is a diagram schematically showing the main part of the equivalent circuit of the multilayer printed circuit board 1 having a noise filter. The equivalent circuit shown in FIG. 4 includes a circuit element 10, the T-type equivalent circuit described above, a bypass capacitor 13, a parasitic inductor 54 having a wiring inductance L4, and a connector circuit 11. The equivalent inductance of the inductor 51 is L1 + M, and the equivalent inductance of the inductor 52 is L2 + M. Further, the bypass capacitor 13 includes a capacitor component 13C having a capacitance C and a parasitic inductor 13 _ESL having a residual inductance Lp which is an equivalent series inductance (ESL). Here, the parasitic inductor 54 is formed by the via Hc of FIGS. 2 (A) and 2 (B). In FIG. 4, for convenience of description, the display of other circuit elements (for example, the resistance component and the parasitic inductor component of the lead wire W3) of the multilayer printed circuit board 1 is omitted.

The bypass circuit of this embodiment is constituted by the lead wire W3, the bypass capacitor 13, the wire W4 and the via Hc shown in FIG. 2A. In this bypass circuit, when the adjacent wiring lines W1a and W2a are magnetically coupled, as shown in FIG. 4, an inductor 53 having a negative inductance -M appears equivalently. That is, the inductor 53 is equivalently connected to the series connection point Np between the inductors 51 and 52. Therefore, at this time, in the bypass circuit, the inductor 53 having the negative inductance -M, the capacitor component 13C, and the parasitic inductor 13 _ESL are connected in series.

  Here, the ground conductor surface 22 is interposed between the adjacent wiring lines W1a and W2a of the upper wiring layer WL1 and the wiring line W9 of the lower wiring layer WL3. Therefore, the magnetic flux generated from the wiring line W9 on the back side is shielded by the ground conductor surface 22 and is not linked to the adjacent wiring lines W1a and W2a. Therefore, the magnitude of the mutual inductance between the inductors 51 and 52 in FIG. 4 can be prevented from being reduced by the influence of the magnetic flux generated from the wiring line W9.

  On the other hand, with regard to the wiring inductance L4 of the via Hc, the wiring inductance L4 can be approximately calculated based on the dimensions (for example, length and via diameter) of the via Hc. Also, by measuring the characteristics of the bypass capacitor 13, it is possible to calculate the residual inductance Lp.

  Therefore, by designing the inductance -M so that the impedances of the negative inductance -M, the wiring inductance L4 of the via Hc, and the residual inductance Lp of the bypass capacitor 13 cancel each other out, the impedance of the bypass circuit becomes the capacitor component 13C. Can be equivalent to the impedance of the For example, using the above equation (1), it is possible to design so that the negative inductance -M is an optimal value. As a result, since the bypass path in the bypass circuit does not substantially include an inductance component, it is possible to prevent the deterioration of the bypass performance even if the frequency of the electromagnetic noise propagating through the power supply wiring pattern W1 is high.

  Here, it is also possible to design the inductance -M in consideration of the parasitic inductance of the lead wire W3 and the wire W4 used for mounting the bypass capacitor 13.

  If the ground conductor surface 22 does not intervene between the adjacent wiring lines W1a and W2a and the wiring line W9 of the lower wiring layer WL3, the adjacent wiring lines W1a and W2a are generated from the magnetic flux generated from the wiring line W9. It can not be shielded. Therefore, the multilayer printed circuit board 1 must be designed in consideration of the electromagnetic coupling among the upper wiring layer WL1, the intermediate wiring layer WL2, and the lower wiring layer WL3, and the manufacturing cost of the multilayer printed circuit board 1 is increased. On the other hand, in the present embodiment, since the magnetic flux from the lower wiring layer WL3 to the upper wiring layer WL1 is shielded by the ground conductor surface 22, there is an advantage that the impedance design of the bypass circuit becomes easy.

  As described above, in the multilayer printed circuit board 1 of the first embodiment, the adjacent wiring lines W1a and W2a are connected in series via the wiring line W9, and face each other to form mutual inductance by magnetic coupling. And extend in the same direction. The negative inductance -M that appears equivalently to the magnetic coupling can cancel the parasitic inductance of the entire bypass circuit including the bypass capacitor 13. Therefore, it is possible to suppress the deterioration of the bypass performance of the bypass capacitor 13 without adding a new electronic component. Therefore, electromagnetic noise propagating in the power supply wiring pattern W1 can be effectively removed.

  Here, in order to cancel the parasitic inductance of the bypass circuit, it is conceivable to additionally mount an electronic component such as an inductor. However, the addition of a new electronic component causes an increase in the manufacturing cost of the printed circuit board, and the new electronic component may adversely affect the other wiring or other electronic component on the printed circuit board by electromagnetically acting. There is. The multilayer printed circuit board 1 of the present embodiment can suppress the deterioration of the bypass performance without additionally mounting such an electronic component.

Second Embodiment
Next, Embodiment 2 according to the present invention will be described. 5 (A), (B) and (C) are plan views of wiring layers constituting the multilayer printed circuit board of the second embodiment. The configuration of the multilayer printed circuit board of the present embodiment uses the upper wiring layer WL1m of FIG. 5A instead of the upper wiring layer WL1 of FIG. 2A, and the lower wiring layer of FIG. The configuration is the same as that of the multilayer printed circuit board 1 of the first embodiment except that the lower wiring layer WL3m of FIG. 5C is used instead of WL3.

  As shown in FIG. 5A, the upper wiring layer WL1m is provided with the circuit element 10 and the connector circuit 11 in the same manner as the upper wiring layer WL1 of the first embodiment. Further, the upper wiring layer WL1m has power supply wiring patterns W1 and W2 and ground wirings W5 and W6 in the same manner as the upper wiring layer WL1 of the first embodiment.

  On the other hand, as shown in FIG. 5C, the bypass capacitor 13 is provided in the lower wiring layer WL3m. In the lower wiring layer WL3 m, a wiring line W9 electrically connecting the vias Ha and Hb, a lead wiring W10 electrically connecting one electrode terminal of the bypass capacitor 13 to the via Ha, and the bypass capacitor 13 A wire W11 is formed, which electrically connects the other electrode terminal of the upper electrode to the via Hc. The via Hc is electrically connected to both the intermediate wiring layer WL2 and the lower wiring layer WL3m, but is not electrically connected to the upper wiring layer WL1m. Therefore, the other electrode terminal of the bypass capacitor 13 is connected to the ground conductor surface 22.

  Also in the multilayer printed circuit board of the second embodiment, as in the first embodiment, the equivalent circuit shown in FIG. 4 can be configured. Therefore, the parasitic inductance of the entire bypass circuit including the via Ha and the bypass capacitor 13 can be canceled by the negative inductance -M equivalently appearing corresponding to the magnetic coupling between the adjacent wiring lines W1a and W2a. Therefore, it is possible to suppress the deterioration of the bypass performance of the bypass capacitor 13 without adding a new electronic component. Therefore, electromagnetic noise propagating in the power supply wiring pattern W1 can be effectively removed.

Third Embodiment
Next, a third embodiment of the present invention will be described. The multilayer printed circuit board of the third embodiment is configured by disposing a magnetic body between the upper wiring layer WL1 or WL1m and the ground conductor surface 22 in the first embodiment or the second embodiment. This magnetic body is disposed at least in the region between the adjacent wiring lines W1a and W2a in plan view.

  FIG. 6 is a diagram showing an example of the arrangement range of the magnetic body 23 with respect to the upper wiring layer WL1 of the first embodiment. As shown in FIG. 6, the magnetic body 23 is disposed in a region including the adjacent wiring lines W1a and W2a in a plan view. The magnetic body 23 is preferably a ferrite magnetic body having high permeability to a high frequency signal of several MHz or more. Also, for example, a resin sheet in which soft magnetic metal powder is dispersed, or a ferrite plating film can be used as the magnetic body 23. When a resin sheet is used, the resin sheet may be interposed between the first insulating layer I1 and the second insulating layer I2. When a ferrite plating film is used, a ferrite plating film having a thickness of about several μm may be formed on the ground conductor surface 22.

  In FIG. 6, the magnetic body 23 is disposed in the vicinity of the adjacent wiring lines W1a and W2a, and in the region between the adjacent wiring lines W1a and W2a and the ground conductor surface 22. Therefore, since the magnetic flux generated from the close wiring lines W1a and W2a flows inside the magnetic body 23, it becomes difficult to interlink with the ground conductor surface 22. As a result, the eddy current is less likely to flow to the ground conductor surface 22, and the amount of reaction flux due to the eddy current is reduced. Therefore, the dimensions of the adjacent wiring lines W1a and W2a necessary to obtain the inductance -M can be reduced.

  As mentioned above, although various embodiments according to the present invention have been described with reference to the drawings, these embodiments are merely examples of the present invention, and various embodiments other than these embodiments can be adopted. For example, although all of the said Embodiment 1-3 are multilayer printed circuit boards of 3 layer structure, it is not limited to this. The present invention is applicable to a multilayer printed circuit board having four or more wiring layers.

  Further, instead of the external power supply 12, a power supply element which is an internal power supply may be mounted on the multilayer printed circuit board of the first to third embodiments. Even in this case, it is possible to suppress the propagation of high frequency electromagnetic noise to the mounted power supply element.

  In the scope of the present invention, free combinations of the embodiments, deformation of any component of each embodiment, or omission of any component of each embodiment can be made.

  DESCRIPTION OF SYMBOLS 1 multilayer printed circuit board, 10 circuit elements, 11 connector circuits, 12 external power supplies, 13 bypass capacitors, 22 ground conductor surfaces, 23 magnetic materials, 41, 42 parasitic inductors, 51 to 54 inductors, WL1, WL1m upper wiring layer (first Wiring layer), WL2 intermediate wiring layer, WL3, WL3 lower wiring layer (second wiring layer), I1 first insulating layer, I2 second insulating layer, W1, W2 power supply wiring pattern, W1a, W2a proximity wiring line (first And second wiring line), W3, W10 lead wiring, W4, W11 wiring, W5, W6 ground wiring, W9 wiring line, Ha to He vias (interlayer connection holes).

Claims (7)

A printed circuit board having a structure in which a first wiring layer and a second wiring layer are stacked via an insulating layer,
First and second wiring lines formed as part of the first wiring layer;
It is arrange | positioned at said 1st wiring layer, has a pair of electrode terminal, and one electrode terminal of said pair of electrode terminals is electrically connected with the one end part of said 1st wiring line. With a bypass capacitor,
A third wiring line formed as a part of the second wiring layer;
A first interlayer connection hole formed through the insulating layer to electrically connect the one end of the first wiring line to one end of the third wiring line;
And a second interlayer connection hole formed through the insulating layer to electrically connect one end of the second wiring line to the other end of the third wiring line.
The first wiring line and the second wiring line face each other and extend in parallel with each other so as to form mutual inductance by magnetic coupling, and the one end portion of the first wiring line is The other end of the second wiring line is opposed, and the one end of the second wiring line is opposed to the other end of the first wiring line.
Printed circuit board characterized by A printed circuit board having a structure in which a first wiring layer and a second wiring layer are stacked via an insulating layer,
First and second wiring lines formed as part of the first wiring layer;
A third wiring line formed as a part of the second wiring layer;
It is arrange | positioned at said 2nd wiring layer, has a pair of electrode terminal, and one electrode terminal of said pair of electrode terminals is electrically connected with the one end part of said 3rd wiring line. With a bypass capacitor,
A first interlayer connection hole formed through the insulating layer to electrically connect one end of the first wiring line to the one end of the third wiring line;
And a second interlayer connection hole formed through the insulating layer to electrically connect one end of the second wiring line to the other end of the third wiring line.
The first wiring line and the second wiring line face each other and extend in parallel with each other so as to form mutual inductance by magnetic coupling, and the one end portion of the first wiring line is The other end of the second wiring line is opposed, and the one end of the second wiring line is opposed to the other end of the first wiring line.
Printed circuit board characterized by   The printed circuit board according to claim 1 or 2, wherein the first wiring line and the second wiring line form an equivalent negative inductance by the magnetic coupling. substrate. The printed circuit board according to any one of claims 1 to 3, further comprising a circuit element disposed in the first wiring layer,
The other end of the first wiring line is electrically connected to a power supply terminal of the circuit element,
The other end of the second wiring line is electrically connected to a power supply,
Printed circuit board characterized by The printed circuit board according to claim 4, wherein
An intermediate wiring layer disposed between the first wiring layer and the second wiring layer inside the insulating layer and having a conductor surface electrically grounded;
A printed circuit board, further comprising: a third interlayer connection hole formed inside the insulating layer and electrically connecting the other of the pair of electrode terminals to the conductor surface. The printed circuit board according to claim 5, further comprising a magnetic body disposed between the conductor surface and the first wiring layer.
The magnetic body is disposed in a region between at least the first wiring line and the second wiring line in a plan view from the thickness direction of the first wiring layer.
Printed circuit board characterized by   The printed circuit board according to claim 6, wherein the magnetic body is a ferrite magnetic body.

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