JP2016006816A - Transformer and multilayer substrate - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a coil pattern type transformer which achieves downsizing of a device and low costs while securing a function needed for the device.SOLUTION: A transformer (100) according to the invention includes: a multilayer substrate (1) on which multiple conductive layers (L1 to L4) are laminated through an interlayer insulator (10); a first coil pattern (13) formed in a first conductive layer (L2) of the multiple conductive layers which is covered by the interlayer insulator; and a second coil pattern (14) which is formed in a second conductive layer (L3) of the multiple conductive layers which is covered by the interlayer insulator. The first coil pattern and the second coil pattern are disposed so that at least parts of the first coil pattern and the second coil pattern are overlapped in a plan view. The multilayer substrate does not have a through hole for disposing a magnetic material serving as a core which penetrates through the first coil pattern and the second coil pattern.

Description

  The present invention relates to a transformer and a multilayer substrate, for example, a coil pattern type transformer formed on a multilayer substrate.

  In field devices and control devices, signal processing based on the detection results of the primary side sensor circuit that monitors temperature, flow rate, pressure, etc. and the detection result of the primary side sensor circuit in order to prevent electric shock or equipment failure In some cases, it is necessary to insulate the secondary side data processing circuit (for example, CPU) that performs control processing. For example, in a temperature controller (temperature controller), a thermocouple is directly mounted on a heater to which AC 240 V is applied, so that a secondary data processing circuit composed of a CPU or the like and a primary sensor circuit are connected. As the withstand voltage, for example, a withstand voltage (IEC61010-1 standard) of AC 3000 V or higher is required. For this reason, in field devices and control devices, an insulating switching power supply device is often used as a power supply device that supplies power to a primary sensor circuit.

  The insulated switching power supply device has a configuration in which a primary side circuit and a secondary side circuit are insulated by a transformer. As a transformer used for an insulating switching power supply device, a transformer formed using a wiring pattern of a printed board is known in addition to a transformer as an external component mounted on the printed board.

  A transformer formed by using a wiring pattern on a printed circuit board is a spiral wiring pattern (hereinafter referred to as “a wiring pattern” formed on different conductive layers of a printed circuit board composed of a plurality of conductive layers stacked with an insulating layer interposed therebetween. This is realized by arranging the coil patterns so as to be magnetically coupled. Hereinafter, a transformer formed using a wiring pattern of a printed board is referred to as a “coil pattern type transformer”.

  As conventional coil pattern type transformers, for example, Patent Documents 1 and 2 below disclose a transformer with a core (magnetic material).

JP-A-10-149929 JP 2005-110552 A

However, in the coil pattern type transformer with a core disclosed in Patent Documents 1 and 2, a large opening (through hole) for inserting the core must be formed in the printed circuit board. The effective area of the printed circuit board for mounting is reduced. In addition, since a coil pattern type transformer with a core generally uses a MnZn-based material having low insulation as a core material, a sufficient insulation distance between the primary side and the secondary side of the coil pattern ( It is necessary to secure a clearance and creepage distance. In particular, in the field device and the control device, since a sensor circuit and an insulating switching power supply device are provided for each channel in order to measure the temperature of a plurality of locations (channels), the primary side and the secondary side of the coil pattern It is necessary to secure not only the insulation distance but also the insulation distance between the channels.
That is, when a coil pattern type transformer with a core is used, the size of the printed circuit board must be increased in order to ensure the effective area of the printed circuit board and the insulation distance, thereby reducing the size and cost of the device. It is disadvantageous in terms.

  In addition, the transformers disclosed in Patent Documents 1 and 2 connect IVH (in which an inner via formed in an inner layer is used to connect coil patterns formed in a plurality of conductive layers including the uppermost layer and the lowermost layer of a printed circuit board ( Since it is formed by an Interstitial Via Hole) method or a build-up method, there is a problem that the manufacturing cost of the printed circuit board is increased as compared with a method using only through vias (through holes).

  On the other hand, in field devices and control devices, the power consumption of the primary side sensor circuit is as small as several tens of mW, for example. Therefore, a large power capacity is required as an insulated switching power supply device that supplies power to the primary side sensor circuit. It has not been. However, when a transformer with a core represented by Patent Documents 1 and 2 is used in an insulated switching power supply device, the power capacity that can be supplied by the insulated switching power supply device is higher than the power required for the sensor circuit on the primary side. It became larger and sometimes over-spec.

  As described above, when a coil pattern type transformer with a core as disclosed in Patent Documents 1 and 2 is used in an insulated switching power supply, the power capacity may be increased depending on the application to which the insulated switching power supply is applied. In addition to over-spec, there are cases where it is disadvantageous in terms of downsizing and cost of equipment.

  The present invention has been made to solve the above-described problems, and is a coil pattern type transformer capable of reducing the size and cost of the device while ensuring the performance required for the device. The purpose is to provide.

  The transformer (100 to 400) according to the present invention includes a multilayer substrate (1) in which a plurality of conductive layers (L1 to L4 (L1 to L6)) are stacked via an interlayer insulating film (10), and the plurality of conductive layers. A first coil pattern (13 (13_1)) formed in the first conductive layer (L2) covered with the interlayer insulating film among the layers, and the interlayer insulating film covered among the plurality of conductive layers. A second coil pattern (14 (14_2)) formed on the second conductive layer (L3 (L5)), and the first coil pattern and the second coil pattern are planarly viewed. And the multilayer substrate does not have a through hole for arranging a magnetic body as a core that penetrates the first coil pattern and the second coil pattern. It is characterized by.

  The transformer is formed in a region surrounded by the first coil pattern in the first conductive layer in a plan view, and is connected to one end of the first coil pattern (21 (31) And in the plan view, the second conductive layer is formed so as to overlap at least partly with the second coil pattern in a region surrounded by the second coil pattern in the second conductive layer. And a second capacitor pattern (22 (34)) connected to one end of the second capacitor pattern.

  The transformer (100, 200) includes a first wiring pattern (11) and a second wiring pattern (12) formed in the uppermost conductive layer (L1) in the stacking direction among the plurality of conductive layers; A third wiring pattern (15) and a fourth wiring pattern (16) formed in the lowest conductive layer in the stacking direction among the plurality of conductive layers, and further comprising one end of the first coil pattern And the first wiring pattern are connected via a first through via (V1), and the other end of the first coil pattern and the second wiring pattern are connected to a second through via (V2). ), One end of the second coil pattern and the third wiring pattern are connected via a third through via (V3), and the other end of the second coil pattern and the third wiring pattern The fourth wiring pattern is the fourth through via V4) may be connected via a.

  The transformer (300) includes a third coil pattern (13_2) formed in a third conductive layer (L3) between the first conductive layer and the second conductive layer in the multilayer substrate, A fourth coil pattern (14_2) formed in a fourth conductive layer (L4) between the third conductive layer and the second conductive layer in the multilayer substrate; A third capacitor pattern (32) formed in a region surrounded by the third coil pattern in the conductive layer and connected to one end of the third coil pattern; and the fourth conductive layer in the fourth conductive layer in a plan view. A fourth capacitor pattern (33) formed in a region surrounded by the fourth coil pattern and connected to one end of the fourth coil pattern; and the first coil pattern (13_1) The second coil pattern (14_2), the third coil pattern (13_2), and the fourth coil pattern (14_1) are arranged so that at least a part thereof overlaps in plan view, The first capacitor pattern (31), the second capacitor pattern (34), the third capacitor pattern (32), and the fourth capacitor pattern (33) are at least partially in plan view. Are arranged in an overlapping manner, and the first coil pattern and the third coil pattern are connected in series via a first through via (V5), and the second coil pattern and the first coil pattern are connected to each other in series. The fourth coil pattern may be connected in series via the second through via (V6).

  In the transformer (400), the third coil formed in the third conductive layer (L3) between the first conductive layer (L2) and the second conductive layer (L5) in the multilayer substrate. A pattern (14_1), a fourth coil pattern (13_2) formed on the fourth conductive layer (L4) between the third conductive layer and the second conductive layer in the multilayer substrate, and a plane A third capacitor pattern (33) formed in a region surrounded by the third coil pattern in the third conductive layer in a view and connected to one end of the third coil pattern; And a fourth capacitor pattern (32) formed in a region surrounded by the fourth coil pattern in the fourth conductive layer and connected to one end of the fourth coil pattern, and the first coil The turn, the second coil pattern, the third coil pattern, and the fourth coil pattern are arranged so as to overlap in plan view, and the first capacitor pattern and the second coil pattern The capacitor pattern, the third capacitor pattern, and the fourth capacitor pattern are arranged so as to overlap in a plan view, and the first coil pattern and the fourth coil pattern are The second coil pattern and the third coil pattern may be connected in series via one through via (V5), and the second coil pattern and the third coil pattern may be connected in series via a second through via (V6).

  The multilayer substrate (1 to 4) according to the present invention has at least two conductive layers covered with an interlayer insulating film (10) excluding the uppermost conductive layer and the lowermost conductive layer (L1, L4, L6) in the stacking direction. The layers (L2 to L5) include a plurality of coil patterns (13, 14, 13_1, 13_2, 14_1, 14_2) arranged to overlap each other in plan view.

  The multilayer substrate may have a capacitor pattern (21, 22, 31 to 34) formed in a region surrounded by the coil pattern in plan view in the conductive layer on which the coil pattern is formed.

  The multilayer substrate includes a plurality of wiring patterns (11, 12, 15, 16) formed on the uppermost conductive layer or the lowermost conductive layer, and ends of the coil patterns corresponding to the wiring patterns. May further include through vias (V1 to V4) for connecting.

  In the above description, the reference numerals with parentheses merely exemplify what are included in the concept of the constituent elements with the reference numerals in the drawings.

  As described above, according to the transformer of the present invention, it is possible to reduce the size and cost of the device while ensuring the performance required for the device.

FIG. 1A is a diagram schematically showing a plane (conductive layer L1) of a coil pattern type transformer according to Embodiment 1 of the present invention. FIG. 1B is a diagram schematically showing a plane (conductive layer L2) of the coil pattern type transformer according to Embodiment 1 of the present invention. FIG. 1C is a diagram schematically showing a plane (conductive layer L3) of the coil pattern type transformer according to Embodiment 1 of the present invention. FIG. 1D is a diagram schematically showing a plane (conductive layer L4) of the coil pattern type transformer according to Embodiment 1 of the present invention. FIG. 2A is a diagram schematically showing a cross section of the coil pattern type transformer according to Embodiment 1 of the present invention. FIG. 2B is a diagram schematically showing another cross section of the coil pattern type transformer according to Embodiment 1 of the present invention. FIG. 3A is a diagram illustrating an example of mounting electronic components on the uppermost layer of the multilayer substrate. FIG. 3B is a diagram illustrating an example of mounting electronic components in the lowest layer of the multilayer board. FIG. 4 is a diagram for explaining the positional relationship between the coil pattern and the through via. FIG. 5A is a diagram schematically showing a plane (conductive layer L1) of the coil pattern type transformer according to Embodiment 2 of the present invention. FIG. 5B is a diagram schematically showing a plane (conductive layer L2) of the coil pattern type transformer according to Embodiment 2 of the present invention. FIG. 5C is a diagram schematically showing a plane (conductive layer L3) of the coil pattern type transformer according to Embodiment 2 of the present invention. FIG. 5D is a diagram schematically showing a plane (conductive layer L4) of the coil pattern type transformer according to Embodiment 2 of the present invention. FIG. 6A is a diagram schematically showing a cross section of a coil pattern type transformer according to Embodiment 2 of the present invention. FIG. 6B is a diagram schematically showing another cross section of the coil pattern type transformer according to Embodiment 2 of the present invention. FIG. 7 is a diagram showing an equivalent circuit example of the coil pattern type transformer according to Embodiment 2 of the present invention. FIG. 8 is a diagram for explaining the distribution of eddy currents generated by the coil pattern. FIG. 9A is a diagram schematically showing a plane (conductive layer L1) of a coil pattern type transformer according to Embodiment 3 of the present invention. FIG. 9B is a diagram schematically showing a plane (conductive layer L2) of the coil pattern type transformer according to Embodiment 3 of the present invention. FIG. 9C is a diagram schematically showing a plane (conductive layer L3) of the coil pattern type transformer according to Embodiment 3 of the present invention. FIG. 9D is a diagram schematically showing a plane (conductive layer L4) of the coil pattern type transformer according to Embodiment 3 of the present invention. FIG. 9E is a diagram schematically showing a plane (conductive layer L5) of the coil pattern type transformer according to Embodiment 3 of the present invention. FIG. 9F is a diagram schematically showing a plane (conductive layer L6) of the coil pattern type transformer according to Embodiment 3 of the present invention. FIG. 10A is a diagram schematically showing a cross section of a coil pattern type transformer according to Embodiment 3 of the present invention. FIG. 10B is a diagram schematically showing another cross section of the coil pattern type transformer according to Embodiment 3 of the present invention. FIG. 11A is a diagram schematically showing a plane (conductive layer L1) of the coil pattern type transformer according to Embodiment 4 of the present invention. FIG. 11B is a diagram schematically showing a plane (conductive layer L2) of the coil pattern type transformer according to Embodiment 4 of the present invention. FIG. 11C is a diagram schematically showing a plane (conductive layer L3) of the coil pattern type transformer according to Embodiment 4 of the present invention. FIG. 11D is a diagram schematically showing a plane (conductive layer L4) of the coil pattern type transformer according to Embodiment 4 of the present invention. FIG. 11E is a diagram schematically showing a plane (conductive layer L5) of the coil pattern type transformer according to Embodiment 4 of the present invention. FIG. 11F is a diagram schematically showing a plane (conductive layer L6) of the coil pattern type transformer according to Embodiment 4 of the present invention. FIG. 12A is a diagram schematically showing a cross section of a coil pattern type transformer according to Embodiment 4 of the present invention. FIG. 12B is a diagram schematically showing another cross section of the coil pattern type transformer according to Embodiment 4 of the present invention.

Hereinafter, embodiments of the present invention will be described with reference to the drawings.
<< Embodiment 1 >>
FIGS. 1A to 1D, FIGS. 2A and 2B show the structure of a multilayer substrate on which a coil pattern type transformer according to an embodiment of the present invention is formed. 1A to 1D show schematic planes of the conductive layers L1 to L4 of the multilayer substrate 1, respectively. 2A shows a schematic cross-sectional structure of the multilayer substrate 1 in the A-XA section in FIGS. 1A to 1D, and FIG. 2B shows the multilayer substrate 1 in the B-XB section in FIGS. 1A to 1D. A schematic cross-sectional structure is shown.

As shown in FIGS. 1A to 1D and FIGS. 2A and 2B, the transformer 100 according to the first embodiment is formed on a multilayer substrate 1 in which a plurality of conductive layers L1 to L4 are stacked with an interlayer insulating film 10 interposed therebetween. A coil pattern type transformer without a core.
1A to 1D, 2A, and 2B, only the structure related to the transformer 100 in the multilayer substrate 1 is shown for convenience of explanation.

  The multilayer board 1 is a printed board, for example, a multilayer board (through multilayer board) having no inner via. 1A to 1D, FIG. 2A, and FIG. 2B illustrate the multilayer substrate 1 in which four conductive layers L1 to L4 are stacked, but the number of conductive layers is not particularly limited. In the following description, the positive side of the direction X (stacking direction) X perpendicular to the plane of the multilayer substrate 1 is referred to as “up” and the negative side is referred to as “down”.

  The interlayer insulating film 10 is made of an insulating material such as epoxy resin or polyimide, for example. In addition, the wiring pattern formed in the conductive layers L1 to L4 is made of a metal material whose main component is, for example, copper (Cu).

  As shown in FIGS. 1A to 1D and FIGS. 2A and 2B, wiring patterns 11 and 12 are formed in the conductive layer L1 (uppermost layer). A coil pattern 13 is formed on the conductive layer L2. One end of the coil pattern 13 is connected to the wiring pattern 11 via the via V1, and the other end of the coil pattern 13 is connected to the wiring pattern 12 via the via V2.

  A coil pattern 14 is formed on the conductive layer L3. Wiring patterns 15 and 16 are formed in the conductive layer L4 (lowermost layer). The wiring pattern 15 is connected to one end of the coil pattern 14 via the via V3, and the wiring pattern 16 is connected to the other end of the coil pattern 14 via the via V4.

  The coil patterns 13 and 14 are formed in the inner conductor layer together with other wiring patterns, for example, in the manufacturing process of the through multilayer board. Specifically, the coil patterns 13 and 14 are formed by patterning a wiring pattern having a predetermined wiring width W in a spiral shape with a predetermined wiring interval S. The wiring width L and the wiring interval S of the coil patterns 13 and 14 are determined according to the required transformer characteristics.

  The coil patterns 13 and 14 are formed in the inner conductive layer excluding the uppermost conductive layer L1 and the lowermost conductive layer L4 of the multilayer substrate 1. For example, the coil pattern 13 is formed on the conductive layer L <b> 2 covered with the interlayer insulating film 10, and the coil pattern 14 is formed on the conductive layer L <b> 3 covered with the interlayer insulating film 10.

  The coil pattern 13 and the coil pattern 14 are disposed so as to be magnetically coupled. Specifically, as shown in FIGS. 1A to 1D and FIGS. 2A and 2B, the coil pattern 13 and the coil pattern 14 are arranged so as to overlap in a plan view. Thereby, the coil pattern 13 functions as a primary coil of the transformer 100, and the coil pattern 14 functions as a secondary coil of the transformer 100.

  The vias V <b> 1 to V <b> 4 are through vias (through holes) that penetrate each layer of the multilayer substrate 1. The through via may fill the entire through hole with a metal material as shown in FIGS. 2A and 2B as long as the wiring pattern between different target layers can be electrically connected. A metal material may be formed only on the side surfaces of the metal.

The coil pattern type transformer 100 according to the first embodiment described above has the following merits.
Since the transformer 100 according to the first embodiment is a transformer having no core, the multilayer substrate 1 does not have an opening (through hole) for inserting the core. Thereby, the effective area of a multilayer board | substrate can be enlarged compared with the conventional transformer with a core. For example, as shown in FIGS. 3A and 3B, capacitors AR_L1 and AR_L4 surrounded by coil patterns 13 and 14 on the front surface (uppermost conductive layer L1) and back surface (lowermost conductive layer L4) of the multilayer substrate 1 Since the electronic components 17_1 to 17_8 other than the transformer such as the IC chip can be mounted, it is possible to suppress an increase in the substrate size as compared with the conventional coil pattern type transformer with a core.

  In addition, since the transformer 100 according to the first embodiment does not have a core, the degree of magnetic coupling is smaller than that of a transformer with a core. However, the temperature sensor and the pressure sensor mounted on the field device and the control device described above. When used as a transformer of an insulating switching power supply device that supplies power to a sensor circuit such as the above, it is possible to ensure a sufficient power capacity. For example, the outer shape (vertical x horizontal) of the transformer is 20 mm × 10 mm, the wiring width L of the coil pattern is 0.1 mm, the wiring interval S of the coil pattern is 0.1 mm, the number of turns (number of turns) of the coil pattern is 5, and the coil pattern When the transformer 100 is manufactured by setting the distance in the stacking direction between the coil 13 and the coil pattern 14 (the thickness of the interlayer insulating film 10 between the conductive layer L2 and the conductive layer L3) to 0.4 mm, power of 50 mW can be supplied. It becomes.

Further, according to the transformer 100 according to the first embodiment, the coil pattern 13 and the coil pattern 14 are formed in the conductive layer (inner layer) other than the uppermost conductive layer and the lowermost conductive layer of the multilayer substrate 1. The insulation distance between the primary side and the secondary side of the transformer 100 can be shortened.
For example, in the international standard IEC61010-1 for safety of electrical measuring instruments, the primary and secondary coils (coil patterns) of the transformer are arranged on the surface of the printed circuit board (for example, the uppermost conductive layer L1 or the lowermost conductive layer L4). ) Or the inner layer of the printed circuit board (for example, the conductive layers L2 and L3), the creepage distance between the transformer primary side and secondary side reinforced insulation (at 240V AC) differs. Specifically, if the primary and secondary coils are formed on the surface of the printed circuit board, a creepage distance of 6 mm or more is required, and the primary and secondary coils are formed on the inner layer of the printed circuit board. If it is, 0.4 mm or more is required as the creepage distance. For example, as shown in FIG. 4, the creeping distance between the via V3 connected to the secondary coil pattern 14 and the primary coil pattern 13 is such that the coil pattern 13 is formed on the surface layer (for example, the conductive layer L1). If the coil pattern 13 is formed on the inner layer (for example, the conductive layer L2), then la ≧ 0.4 mm.

  Therefore, as in the transformer 100 according to the first embodiment, the coil pattern 13 and the coil pattern 14 are formed on a conductive layer (inner layer) other than the uppermost layer and the lowermost layer of the multilayer substrate 1, so that Compared to the case where the coil patterns are formed in the uppermost layer and the lowermost layer as in the transformers disclosed in 1 and 2, the creepage distances of the primary side and secondary side coils (coil patterns) of the transformer 100 are shortened. be able to. As a result, it is possible to increase the breakdown voltage while suppressing an increase in the substrate size of the multilayer substrate 1.

  Furthermore, as in the transformer 100 according to the first embodiment, by using a through via instead of an inner via as the vias V1 to V4, the manufacturing cost of the multilayer substrate 1 can be suppressed. For example, as a method of ensuring the above-described insulation distance between the via V3 and the coil pattern 13, in addition to physically separating the via V3 and the coil pattern 13, the via V3 is not an through via but an inner via (non-through via). However, when using an inner via, a complicated construction method such as a build-up construction method or an IVH construction method is required, which increases the manufacturing cost of the substrate. On the other hand, according to the transformer 100 according to the first embodiment, since only through vias are used as vias for interlayer connection, the coil pattern type transformer 100 can be manufactured at a lower cost.

  As described above, according to the coil pattern type transformer according to the present invention, the substrate size and manufacturing cost of the multilayer substrate can be suppressed, so that the size and cost of the device can be reduced. For example, by adopting the coil pattern type transformer according to the present invention as a transformer of an insulation type switching power supply device that does not require a large power capacity such as the above-described field devices and control devices, the performance required for the device is secured. However, it is possible to reduce the size and cost of the device.

<< Embodiment 2 >>
The transformer 200 according to the second embodiment is different from the transformer 100 according to the first embodiment in that a capacitor pattern is formed in a region surrounded by a coil pattern in the inner layer of the multilayer substrate. It is the same. In the multilayer substrate 2 according to the second embodiment, the same components as those in the multilayer substrate 1 according to the first embodiment are denoted by the same reference numerals, and detailed description thereof is omitted.

  5A to 5D and FIGS. 6A and 6B show the structure of the transformer 200 according to the second embodiment. 5A to 5D show schematic planes of the conductive layers L1 to L4 of the multilayer substrate 2, respectively. 6A shows a schematic cross-sectional structure of the multilayer substrate 2 in the A-XA section in FIGS. 5A to 5D, and FIG. 6B shows the multilayer substrate 2 in the B-XB section in FIGS. 5A to 5D. A schematic cross-sectional structure is shown.

As shown in FIGS. 5A to 5D and FIGS. 6A and 6B, the capacitor pattern 21 is formed in a region (region inside the coil pattern 13) surrounded by the coil pattern 13 of the conductive layer L2 in plan view. Further, the capacitor pattern 22 is formed in a region (region inside the coil pattern 14) surrounded by the coil pattern 14 of the conductive layer L3 in plan view.
Here, the “capacitor pattern” is an electrode pattern (wiring pattern) formed on the conductive layer so as to constitute an electrode of the capacitor. The area of the capacitor pattern (wiring width and wiring length of the wiring pattern) is adjusted so that the capacitance of the capacitor becomes a desired value.
Capacitor pattern 21 and capacitor pattern 22 are arranged so as to overlap each other in plan view, thereby forming a capacitor using interlayer insulating film 10 sandwiched between capacitor pattern 21 and capacitor pattern 22 as a dielectric. The capacitor pattern 21 is connected to the coil pattern 13 and the wiring pattern 12 through the via V2, and the capacitor pattern 22 is connected to the coil pattern 14 and the wiring pattern 15 through the via V3.

  As a result, the capacitor pattern 21 and the capacitor pattern 22 use the interlayer insulating film 10 sandwiched between the two capacitor patterns 21 and 22 as a dielectric, and between the primary side and secondary side coils (coil patterns) of the transformer 200. Configure the capacitor to be connected.

  The coil pattern type transformer 200 according to the second embodiment described above has the following merits. Details will be described below.

Conventionally, in an insulation type switching power supply device, there is a problem that common mode noise is generated via a stray capacitance existing between a primary coil and a secondary coil of a transformer. According to the coil pattern type transformer 200 according to the second embodiment, it is possible to suppress the occurrence of common mode noise due to switching noise propagated from the primary side to the secondary side via the stray capacitance Cs.
FIG. 7 shows an equivalent circuit of the coil pattern type transformer 200 according to the second embodiment.
As shown in the figure, stray capacitance (parasitic capacitance) Cs exists between the primary side coil Lx (coil pattern 13) of the transformer 200 and the secondary side coil Ly (coil pattern 14). Consider a case where the transformer 200 is employed as an insulating transformer of an insulated switching power supply device, and the terminals Tp1 and Tp2 of the transformer 200 are connected to the high potential side and the terminals Tn1 and Tn2 of the transformer 200 are connected to the low potential (ground) side. In this case, a feedback loop is formed in which switching noise propagated from the primary coil terminal Tp1 to the secondary coil terminal Tp2 via the stray capacitance Cs returns to the primary side via the capacitor Csw. With this feedback loop, it is possible to suppress the occurrence of common mode noise due to switching noise.

  The capacitor Csw can be realized by a chip capacitor. However, as described above, since insulation is required between the primary side and the secondary side of the transformer, a high withstand voltage chip capacitor is required. Increases size and cost of parts. On the other hand, according to the coil pattern type transformer 200 according to the second embodiment, the capacitor Csw is formed by the capacitor patterns 21 and 22 formed in the inner layer of the multilayer substrate 2 as compared with the case where a chip capacitor is used. Cost can be reduced.

  In addition, according to the coil pattern type transformer 200 according to the second embodiment, the capacitor patterns 21 and 22 are formed in the region surrounded by the coil patterns 13 and 14, thereby suppressing the reduction in transmission efficiency due to the eddy current. Is possible. Details will be described below.

FIG. 8 shows an example of the distribution of eddy currents generated by the coil pattern. This figure illustrates the distribution of eddy currents when a metal pattern (solid pattern) is formed in each of the area AR2 surrounded by the coil pattern 50 and the area AR3 outside the coil pattern 50 in plan view.
As shown in the figure, when the metal pattern is formed in the area AR2 surrounded by the coil pattern 50 and the outer area AR3, the eddy current due to the magnetic field generated by the coil pattern 50 is the area AR1 in which the coil pattern 50 is formed. The region AR2 and the outer region AR3 that are concentrated in (the hatched portion in FIG. 8) and surrounded by the coil pattern 50 hardly occur. That is, by forming a metal pattern around the coil pattern, the range in which eddy current is generated can be reduced.

  Therefore, by forming the capacitor patterns 21 and 22 inside the coil patterns 13 and 14 as in the transformer 200 according to the second embodiment, eddy currents generated inside the coil patterns 13 and 14 can be suppressed. Therefore, it is possible to reduce the transmission efficiency due to the eddy current. In addition, as shown in FIG. 7, when the capacitor patterns 21 and 22 formed inside the coil patterns 13 and 14 are connected to the low potential (ground) side, the capacitor patterns 21 and 22 are electrostatic shields of the coil patterns 13 and 14. Therefore, a noise reduction effect can be expected.

  Furthermore, according to the coil pattern type transformer 200 according to the second embodiment, the capacitor patterns 21 and 22 are formed not on the outside of the coil patterns 13 and 14 but on the inside thereof, thereby increasing the coil diameter of the coil patterns 13 and 14. Easy to do. Thereby, it becomes easy to produce a transformer having a large inductance while suppressing the substrate size of the multilayer substrate 2. According to this, for example, in an insulation type switching power supply device or the like, by using a transformer having a large inductance, the transformer can be driven by a signal having a low frequency. Further, for example, in a magnetic resonance type resonance circuit, the use of a transformer having a large inductance can reduce the capacitance of the capacitor of the resonance circuit. Therefore, when selecting a capacitor, a capacitor with high accuracy and good temperature characteristics is selected. This contributes to the improvement of the characteristics of the resonant circuit.

  As described above, according to the transformer 200 according to the second embodiment, similarly to the transformer 100 according to the first embodiment, the substrate size and the manufacturing cost of the multilayer substrate can be suppressed. It becomes possible to plan. Further, by forming the capacitor pattern on the inner side of the coil pattern as described above, it is possible to realize a reduction in transmission efficiency due to an eddy current and a reduction in noise at a lower cost.

<< Embodiment 3 >>
The transformer 300 according to the third embodiment is different from the transformer 200 according to the second embodiment in that a coil pattern and a capacitor pattern are formed on a multilayer substrate having six conductive layers. It is the same. In the multilayer substrate 3 according to the third embodiment, the same components as those in the multilayer substrate 2 according to the second embodiment are denoted by the same reference numerals, and detailed description thereof is omitted.

  9A to 9F and FIGS. 10A and 10B show the structure of the transformer 300 according to the third embodiment. 9A to 9F show schematic planes of the conductive layers L1 to L6 of the multilayer substrate 3, respectively. 10A shows a schematic cross-sectional structure of the multilayer substrate 3 in the A-XA section in FIGS. 9A to 9F, and FIG. 10B shows the multilayer substrate 3 in the B-XB section in FIGS. 9A to 9F. A schematic cross-sectional structure is shown.

  As shown in FIGS. 9A to 9F and FIGS. 10A and 10B, wiring patterns 11 and 12 are formed in the conductive layer L1 (uppermost layer). In the conductive layer L2, a coil pattern 13_1 constituting a primary coil of the transformer 300 and a capacitor pattern 31 are formed. The capacitor pattern 31 is formed in a region surrounded by the coil pattern 13_1. One end of the coil pattern 13_1 is connected to the wiring pattern 12 through the via V1 and to the capacitor pattern 31.

  In the conductive layer L3, a coil pattern 13_2 constituting a primary coil of the transformer 300 and a capacitor pattern 32 are formed. The capacitor pattern 32 is formed in a region surrounded by the coil pattern 13_2. One end of the coil pattern 13_2 is connected to the other end of the coil pattern 13_1 through the via V5. The other end of the coil pattern 13_2 is connected to the wiring pattern 11 of the conductive layer L1 through the via V2.

  In the conductive layer L4, a coil pattern 14_1 constituting a secondary coil of the transformer 300 and a capacitor pattern 33 are formed. The capacitor pattern 33 is formed in a region surrounded by the coil pattern 14_1.

  In the conductive layer L5, a coil pattern 14_2 constituting a secondary coil of the transformer 300 and a capacitor pattern 34 are formed. The capacitor pattern 34 is formed in a region surrounded by the coil pattern 14_2. One end of the coil pattern 14_2 is connected to one end of the coil pattern 14_1 through the via V6.

  Wiring patterns 15 and 16 are formed on the conductive layer L6 (lowermost layer). The wiring pattern 15 is connected to the other end of the coil pattern 14_1 through the via V3. Further, the wiring pattern 16 is connected to the capacitor pattern 33 and the capacitor pattern 34 through the via V4, and is connected to the other end of the coil pattern 14_2.

  The vias V <b> 1 to V <b> 6 are through vias (through holes), similarly to the multilayer substrate 1 according to the first embodiment.

  The coil patterns 13_1 and 13_2 and the coil patterns 14_1 and 14_2 are disposed so as to be magnetically coupled. Specifically, as shown in FIGS. 9A to 9F and FIGS. 10A and 10B, the coil patterns 13_1 and 13_2 and the coil patterns 14_1 and 14_2 are arranged so that at least a part thereof is overlapped in plan view. Thereby, the coil pattern 13_1 and the coil pattern 13_2 connected in series function as a primary coil of the transformer 300, and the coil pattern 14_1 and the coil pattern 14_2 connected in series are the secondary side of the transformer 300. It functions as a coil.

  Further, as shown in FIGS. 9A to 9F and FIGS. 10A and 10B, the capacitor patterns 31 and 32 and the capacitor patterns 33 and 34 are arranged so that at least a part thereof is overlapped in plan view. Thereby, a plurality of capacitors are formed between the primary side and secondary side coils (coil patterns) of the transformer 300 by the capacitor patterns 31 to 34. For example, a capacitor composed of a capacitor pattern 32 and a capacitor pattern 33, a capacitor composed of a capacitor pattern 32 and a capacitor pattern 34, a capacitor composed of a capacitor pattern 31 and a capacitor pattern 33, and a capacitor pattern 31 And the capacitor pattern 34 are formed between the primary and secondary coils of the transformer 300. Of these capacitors, the capacitor constituted by the capacitor pattern 32 and the capacitor pattern 33 has the largest capacitance value.

  As described above, according to the transformer 300 according to the third embodiment, the inductance of the transformer can be further increased by forming the coil pattern on the plurality of conductive layers and connecting them in series.

  Moreover, by forming the capacitor pattern on the plurality of conductive layers, the capacitor connected to the primary side and the secondary side of the transformer can be further increased, thereby further reducing noise and suppressing the reduction in transmission efficiency. I can expect.

<< Embodiment 4 >>
The transformer 400 according to the fourth embodiment is different from the transformer 300 according to the third embodiment in that the primary side coil pattern and the capacitor pattern and the secondary side coil pattern and the capacitor pattern are alternately formed in the stacking direction. However, the other points are the same as those of the transformer 300. In the transformer 400 according to the fourth embodiment, the same components as those of the transformer 300 according to the third embodiment are denoted by the same reference numerals, and detailed description thereof is omitted.

  11A to 11F and FIGS. 12A and 12B show the structure of the transformer 400 according to the fourth embodiment. 11A to 11F show schematic planes of the conductive layers L1 to L6 of the multilayer substrate 4, respectively. 12A shows a schematic cross-sectional structure of the multilayer substrate 4 in the A-XA section in FIGS. 11A to 11F, and FIG. 12B shows the multilayer substrate 4 in the B-XB section in FIGS. 11A to 11F. A schematic cross-sectional structure is shown.

  As shown in FIGS. 11A to 11F and FIGS. 12A and 12B, wiring patterns 11 and 12 are formed in the conductive layer L1 (uppermost layer). In the conductive layer L2, a coil pattern 13_1 constituting a primary coil of the transformer 400 and a capacitor pattern 31 are formed. The capacitor pattern 31 is formed in a region surrounded by the coil pattern 13_1. One end of the coil pattern 13_1 is connected to the wiring pattern 12 through the via V1 and to the capacitor pattern 31.

  In the conductive layer L3, a coil pattern 14_1 constituting a secondary coil of the transformer 300 and a capacitor pattern 33 are formed. The capacitor pattern 33 is formed in a region surrounded by the coil pattern 14_1.

  In the conductive layer L4, a coil pattern 13_2 constituting a primary coil of the transformer 400 and a capacitor pattern 32 are formed. The capacitor pattern 32 is formed in a region surrounded by the coil pattern 13_2. One end of the coil pattern 13_2 is connected to the other end of the coil pattern 13_1 through the via V5. The other end of the coil pattern 13_2 is connected to the wiring pattern 11 through the via V2. Further, the capacitor pattern 32 is connected to the capacitor pattern 31 through the via V1, and is also connected to one end of the coil pattern 13_1 and the wiring pattern 12.

  In the conductive layer L5, a coil pattern 14_2 constituting a secondary coil of the transformer 400 and a capacitor pattern 34 are formed. The capacitor pattern 34 is formed in a region surrounded by the coil pattern 14_2. One end of the coil pattern 14_2 is connected to one end of the coil pattern 14_1 through the via V6.

  Wiring patterns 15 and 16 are formed on the conductive layer L6 (lowermost layer). The wiring pattern 15 is connected to the other end of the coil pattern 14_1 through the via V3. Further, the wiring pattern 16 is connected to the capacitor pattern 34 through the via V4, and is connected to the other end of the coil pattern 14_2 and the capacitor pattern 33.

  Similar to the multilayer substrate 3 according to the third embodiment, the coil pattern 13_1 and the coil pattern 13_2 connected in series function as a coil on the primary side of the transformer 400, and the coil pattern 14_1 and the coil pattern connected in series. 14_2 functions as a secondary coil of the transformer 400.

  11A to 11F and FIGS. 12A and 12B, the primary side of the transformer 400 is formed by alternately stacking the primary side coil patterns 13_1 and 13_2 and the secondary side coil patterns 14_1 and 14_2. The degree of coupling between the second coil and the secondary coil can be further improved.

  11A to 11F and FIGS. 12A and 12B, a capacitor pattern 31, a capacitor pattern 32, a capacitor pattern 33, and a capacitor pattern 34 are used to form primary and secondary coils ( A plurality of capacitors are formed between the coil patterns). For example, a capacitor constituted by the capacitor pattern 31 and the capacitor pattern 33, a capacitor constituted by the capacitor pattern 33 and the capacitor pattern 32, a capacitor constituted by the capacitor pattern 32 and the capacitor pattern 34, and the capacitor pattern 31 And the capacitor pattern 34 are formed between the primary and secondary coils of the transformer 300.

  As described above, the capacitor patterns 31, 32 connected to the primary side coil patterns 13_1, 13_2 and the capacitor patterns 33, 34 connected to the secondary side coil patterns 14_1, 14_2 are alternately stacked. The capacitance of the capacitor formed between the primary side coil and the secondary side coil can be further increased.

  As described above, according to the transformer 400 according to the fourth embodiment, the primary coil and the secondary coil are formed by alternately laminating the primary coil pattern and the secondary coil pattern. The degree of coupling with can be increased.

  Also, by alternately stacking the capacitor pattern connected to the primary coil pattern and the capacitor pattern connected to the secondary coil pattern, the capacitance of the capacitor connected to the primary side and secondary side of the transformer Since the value can be further increased, further noise reduction and suppression of a decrease in transmission efficiency can be expected.

  Although the invention made by the present inventors has been specifically described based on the embodiments, it is needless to say that the present invention is not limited thereto and can be variously modified without departing from the gist thereof. Yes.

  For example, like the four-layer and six-layer multilayer substrates exemplified in Embodiments 1 to 4, the coil pattern type transformer according to the present invention can be formed on a multilayer substrate having six or more layers.

  Further, in the above embodiment, the case where the coil pattern type transformer according to the present invention is applied to the insulation transformer of the insulation type switching power supply device is illustrated, but the present invention is not limited to this and may be applied to other applications. Is possible. For example, the present invention can be applied to a digital isolator that transmits and receives signals through a transformer. In this case, the transformer is driven by the modulation data instead of the switching pulse.

  In the above embodiment, the wiring patterns 11 and 12 are formed on the uppermost conductive layer L1, and the wiring patterns 15 and 16 are formed on the lowermost conductive layers L4 and L6. However, the wiring patterns 11 and 12 and the wiring patterns 15 and 16 may be formed on either the uppermost conductive layer L1 or the lowermost conductive layers L4 and L6.

  DESCRIPTION OF SYMBOLS 1-4 ... Multilayer substrate, L1-L6 ... Conductive layer, 10 ... Interlayer insulating film, 11, 12, 15, 16 ... Wiring pattern, 13, 13_1, 13_2, 14, 14_1, 14_2 ... Coil pattern, 21, 22, 31-34 ... Capacitor pattern, Cs ... Stray capacitance, Csw ... Capacitor, V1-V6 ... Via, 17_1-17_8 ... Electronic component, 100-400 ... Transformer.

Claims (8)

A multilayer substrate in which a plurality of conductive layers are stacked via an interlayer insulating film;
A first coil pattern formed on a first conductive layer covered with the interlayer insulating film among the plurality of conductive layers;
A second coil pattern formed on a second conductive layer covered with the interlayer insulating film among the plurality of conductive layers;
The first coil pattern and the second coil pattern are arranged so that at least a part thereof overlaps in plan view,
The said multilayer substrate does not have a through-hole for arrange | positioning the magnetic body as a core which penetrates the said 1st coil pattern and the said 2nd coil pattern. The trans | transformer characterized by the above-mentioned. The transformer according to claim 1,
A first capacitor pattern formed in a region surrounded by the first coil pattern in the first conductive layer in plan view and connected to one end of the first coil pattern;
In a plan view, the second conductive layer is formed in a region surrounded by the second coil pattern so as to overlap at least partly with the first capacitor pattern, and at one end of the second coil pattern. And a second capacitor pattern connected thereto. The transformer according to claim 1 or 2,
A first wiring pattern and a second wiring pattern formed on the uppermost conductive layer in the stacking direction among the plurality of conductive layers;
A third wiring pattern and a fourth wiring pattern formed in the lowest conductive layer in the stacking direction of the plurality of conductive layers;
One end of the first coil pattern and the first wiring pattern are connected via a first through via,
The other end of the first coil pattern and the second wiring pattern are connected via a second through via,
One end of the second coil pattern and the third wiring pattern are connected via a third through via,
The other end of the second coil pattern and the fourth wiring pattern are connected via a fourth through via. The transformer according to claim 2,
A third coil pattern formed in a third conductive layer between the first conductive layer and the second conductive layer in the multilayer substrate;
A fourth coil pattern formed in a fourth conductive layer between the third conductive layer and the second conductive layer in the multilayer substrate;
A third capacitor pattern formed in a region surrounded by the third coil pattern in the third conductive layer in plan view and connected to one end of the third coil pattern;
A fourth capacitor pattern formed in a region surrounded by the fourth coil pattern in the fourth conductive layer in plan view, and connected to one end of the fourth coil pattern;
The first coil pattern, the second coil pattern, the third coil pattern, and the fourth coil pattern are arranged with an overlap in plan view,
The first capacitor pattern, the second capacitor pattern, the third capacitor pattern, and the fourth capacitor pattern are arranged so as to overlap in plan view,
The first coil pattern and the third coil pattern are connected in series via a first through via,
The second coil pattern and the fourth coil pattern are connected in series through a second through via. The transformer according to claim 2,
A third coil pattern formed in a third conductive layer between the first conductive layer and the second conductive layer in the multilayer substrate;
A fourth coil pattern formed in a fourth conductive layer between the third conductive layer and the second conductive layer in the multilayer substrate;
A third capacitor pattern formed in a region surrounded by the third coil pattern in the third conductive layer in plan view and connected to one end of the third coil pattern;
A fourth capacitor pattern formed in a region surrounded by the fourth coil pattern in the fourth conductive layer in plan view and connected to one end of the fourth coil pattern;
The first coil pattern, the second coil pattern, the third coil pattern, and the fourth coil pattern are arranged with an overlap in plan view,
The first capacitor pattern, the second capacitor pattern, the third capacitor pattern, and the fourth capacitor pattern are arranged so as to overlap in plan view,
The first coil pattern and the fourth coil pattern are connected in series via a first through via,
The transformer, wherein the second coil pattern and the third coil pattern are connected in series via a second through via. At least two conductive layers covered with an interlayer insulating film excluding the uppermost conductive layer and the lowermost conductive layer in the stacking direction have a plurality of coil patterns arranged so as to overlap each other in plan view. A multilayer board characterized by The multilayer substrate according to claim 5, wherein
A multilayer substrate, further comprising a capacitor pattern formed in a region surrounded by the coil pattern in plan view of the conductive layer on which the coil pattern is formed. The multilayer substrate according to claim 5 or 6,
A plurality of wiring patterns formed in the uppermost conductive layer or the lowermost conductive layer;
The multilayer substrate further comprising a through via that connects the wiring pattern and the corresponding end of the coil pattern.

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