WO2012153835A1 - Printed wiring board - Google Patents

Printed wiring board Download PDF

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Publication number
WO2012153835A1
WO2012153835A1 PCT/JP2012/062122 JP2012062122W WO2012153835A1 WO 2012153835 A1 WO2012153835 A1 WO 2012153835A1 JP 2012062122 W JP2012062122 W JP 2012062122W WO 2012153835 A1 WO2012153835 A1 WO 2012153835A1
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WIPO (PCT)
Prior art keywords
power supply
hole
wiring board
gnd
bypass capacitor
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PCT/JP2012/062122
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French (fr)
Japanese (ja)
Inventor
貴士 足立
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シャープ株式会社
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Publication of WO2012153835A1 publication Critical patent/WO2012153835A1/en

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    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/0213—Electrical arrangements not otherwise provided for
    • H05K1/0216—Reduction of cross-talk, noise or electromagnetic interference
    • H05K1/023—Reduction of cross-talk, noise or electromagnetic interference using auxiliary mounted passive components or auxiliary substances
    • H05K1/0231—Capacitors or dielectric substances
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/11—Printed elements for providing electric connections to or between printed circuits
    • H05K1/111—Pads for surface mounting, e.g. lay-out
    • H05K1/112—Pads for surface mounting, e.g. lay-out directly combined with via connections

Definitions

  • the present invention generally relates to a printed wiring board, and more particularly to a mounting structure of a bypass capacitor for reducing power feeding system electromagnetic noise.
  • Patent Document 1 Japanese Patent No. 3610127
  • Patent Document 2 Japanese Patent Laid-Open No. 2010-98162 disclose a wiring board using a bypass capacitor.
  • the printed circuit board disclosed in Patent Document 1 has a plurality of printed patterns wired in four directions on the front surface of a two-layer printed wiring board in which a printed circuit pattern is formed on the front surface and the back surface through an insulating base. It is a printed circuit board for mounting a circuit element.
  • FIG. 4A is a plan view showing the surface side of the printed wiring board disclosed in Patent Document 1.
  • FIG. 4B is a perspective plan view showing the back side of the printed wiring board disclosed in Patent Document 1.
  • FIG. 4A and 4B a plurality of lands 102 on which electronic circuit elements are mounted are disposed on the surface 101a.
  • a ground pattern 103 is disposed on the front surface 101a and the back surface 101b.
  • a main power supply pattern 104 is disposed on the back surface 101b.
  • On the back surface 101 b a power supply branch pattern 105 that branches from the main power supply pattern 104 and connects to a part of the plurality of lands 102 is provided.
  • a bypass capacitor is disposed between the power supply branch pattern 105 and the ground pattern 103.
  • the power supply branch pattern 105 is based on the connection portion 106 between the bypass capacitor and the power supply branch pattern 105, and the power supply from the connection portion 106 is higher than the inductance from the connection portion 106 to the land 102 connecting the electronic circuit and the power supply branch pattern 105.
  • the inductance to the branch pattern 105 and the main power supply pattern 104 is formed to be large.
  • an ideal T-type low-pass filter can be formed, the high frequency current loop of the power supply system can be reduced, and the radiation noise generated in the power supply line can be reduced.
  • FIG. 5 is a plan view showing the configuration of the printed wiring board disclosed in Patent Document 2.
  • FIG. 5 in the printed wiring board disclosed in Patent Document 2, power is supplied to semiconductor device 202 by power supply wiring 210 and ground lead wiring 211 connected to the power supply layer and ground layer of printed wiring board 201. ing.
  • the power supply terminal 203 of the semiconductor device 202 is connected to the bypass capacitor 207 via the power supply wiring 210.
  • One end of the bypass capacitor 207 is connected to the power supply layer via a via hole 205 connected to the power supply layer.
  • the other end of the bypass capacitor 207 is connected to the ground layer via the via hole 206b.
  • the ground terminal 204 of the semiconductor device 202 is connected to the ground layer via the via hole 206 a via the ground lead wiring 211.
  • the power supply wiring 210 connecting the bypass capacitor 207 and the power supply terminal 203 and the via hole 206a and the via hole 206b connected to the ground layer are arranged in the same straight line, so that the power supply current 208 and the ground current 209 are arranged. Therefore, the impedance of the power feeding system can be reduced and the electromagnetic noise can be reduced.
  • the printed circuit board disclosed in Patent Document 1 has a structure in which a bypass capacitor is mounted on the back side of an IC (Integrated Circuit) in order to reduce a high frequency current loop of a power supply system. For this reason, there are problems that the work of separately mounting the IC and the bypass capacitor on the front surface and the back surface of the substrate is complicated, and the thickness of the printed wiring board is increased.
  • IC Integrated Circuit
  • an object of the present invention is to solve the above-mentioned problem, and an IC and a bypass capacitor can be mounted on the same surface of the wiring board without using a multilayer wiring board having a complicated structure, and electromagnetic noise can be reduced. It is to provide a printed wiring board.
  • the printed wiring board according to the present invention includes a semiconductor element and a bypass capacitor mounted on the first surface, and a first power supply wiring and a GND pattern formed on the second surface.
  • the semiconductor element has a power supply pin and a GND pin.
  • the printed wiring board further includes a first GND wiring and a second GND wiring formed on the first surface, a first through hole, a second through hole, and a third through hole.
  • the first terminal of the bypass capacitor is connected to the power supply pin and the first power supply wiring through the first through hole.
  • the second terminal of the bypass capacitor is connected to the second through hole.
  • the GND pin of the semiconductor element is connected to the GND pattern from the first GND wiring on the first surface through the third through hole.
  • an IC and a bypass capacitor can be mounted on the same surface of a wiring board without using a multilayer wiring board having a complicated structure, and a printed wiring board that can reduce electromagnetic noise is provided. Can be provided.
  • FIG. 10 is a plan view showing a surface side of a printed wiring board disclosed in Patent Document 1.
  • FIG. FIG. 6 is a perspective plan view showing the back side of a printed wiring board disclosed in Patent Document 1.
  • 10 is a plan view showing a configuration of a printed wiring board disclosed in Patent Document 2.
  • FIG. 1A is a plan view showing the surface side of the printed wiring board according to Embodiment 1 of the present invention.
  • FIG. 1B is a perspective plan view showing the back side of the printed wiring board according to Embodiment 1 of the present invention.
  • FIG. 1C is a perspective plan view showing the front surface side and the back surface side of the printed wiring board according to Embodiment 1 of the present invention superimposed on each other.
  • FIGS. 1A, 1B, and 1C in the printed wiring board according to the present embodiment, patterns are formed on the front surface and the back surface of the insulating base, respectively, and the structure is simpler than that of the multilayer printed wiring board. A layer printed wiring board is used.
  • a mounting region 3 on which the semiconductor element 1 and the bypass capacitor 2 are mounted is provided on the surface side as the first surface of the printed wiring board.
  • a GND pattern 4 occupying a large area of the second surface, and a first power supply wiring 5 insulated and separated from the GND pattern 4 Is formed.
  • the periphery of the mounting region 3 is covered with a conductive GND pattern 6 in order to prevent external radiation noise from entering.
  • the semiconductor element 1 has a plurality of connection pins including a power supply pin 11 and a GND pin 12 for power supply around the semiconductor element 1.
  • the power supply pin 11 is connected to the second power supply wiring 13, and the GND pin 12 is connected to the first GND wiring 14.
  • the bypass capacitor 2 is disposed in the vicinity of the power supply pin 11 of the semiconductor element 1.
  • the first terminal 21 of the bypass capacitor 2 is connected to the power supply pin 11 by the second power supply wiring 13, and the second terminal 22 of the bypass capacitor 2 is connected to the second GND wiring 15.
  • the second power supply wiring 13 on the first surface and the first power supply wiring 5 on the second surface are connected to the second power supply wiring 13 of the bypass capacitor 2. They are connected to each other through a first through hole 31 disposed in the vicinity of one terminal 21.
  • the second GND wiring 15 on the first surface and the GND pattern 4 on the second surface are connected to each other through the second through hole 32 disposed between the first power supply wiring 5 and the semiconductor element 1 in the substrate surface.
  • the first GND wiring 14 on the first surface and the GND pattern 4 on the second surface are connected to each other via a third through hole 33 disposed between the second through hole 32 and the GND pin 12.
  • the second through hole 32 is disposed between the first power supply wiring 5 and the semiconductor element 1 in the substrate surface, so that the GND current 41 flowing between the GND pin 12 and the second through hole 32 is obtained. Is formed on a substantially straight line without intersecting the first power supply wiring 5. For this reason, the current loop between the semiconductor element 1 and the bypass capacitor 2 is reduced, and electromagnetic noise generated from the power feeding system of the semiconductor element 1 can be reduced.
  • the arrangement of the first through hole 31, the second through hole 32, and the third through hole 33 can be adjusted within the above range.
  • FIG. 2A is a current distribution diagram showing the surface side of the substrate, which is the result of the near magnetic field analysis of the printed wiring board.
  • FIG. 2B is a current distribution diagram showing the result of the near magnetic field analysis of the printed wiring board and showing the back side of the board.
  • the same reference numerals are given to the portions showing the same parts as in FIG.
  • the power supply current 42 flowing between the power supply pin 11 and the bypass capacitor 2 and the GND pattern 4 as shown in FIG. 2B are provided.
  • the GND current 41 flowing between the second through hole 32 and the third through hole 33 flows through the shortest path without bypassing the first power supply wiring 5.
  • Embodiment 2 are perspective plan views showing the front surface side and the back surface side of the printed wiring board according to Embodiment 2 of the present invention in an overlapping manner.
  • the printed wiring board in the present embodiment is obtained by changing the arrangement of the first through hole 31, the second through hole 32, the third through hole 33, and the bypass capacitor 2.
  • Other configurations are the same as those in the first embodiment. The same. Hereinafter, the description of the same structure as in the first embodiment will not be repeated.
  • the first through hole 31 is arranged outside the first power supply wiring 5.
  • the first power supply wiring 5 overlaps the current loop between the semiconductor element 1 and the bypass capacitor 2, the effect of noise suppression is reduced.
  • the first power supply wiring 5 can be accommodated between the first through hole 31 and the second through hole 32, the circuit area on the back surface side can be reduced.
  • the first through hole 31 and the second through hole 32 are disposed on both sides of the bypass capacitor 2 in the short direction.
  • the bypass capacitor 2 and the second through hole 32 can be arranged close to the semiconductor element 1, the current loop between the semiconductor element 1 and the bypass capacitor 2 can be reduced. Further, since the mounting region 3 on the front surface side can be reduced, the printed wiring board can be reduced in size.
  • the first through hole 31 and the second through hole 32 are arranged on both sides of the bypass capacitor 2 in the longitudinal direction.
  • the first power supply wiring 5 can be arranged close to the semiconductor element 1, the circuit area on the back surface side and the mounting region 3 on the front surface side can be reduced, and the printed wiring board can be further miniaturized. Can do.
  • the GND pin 12 of the semiconductor element 1 is provided on the same side as the power supply pin 11 or on another upper side and lower side. Is assumed. Even in such a case, the third through hole 33 is disposed in the in-plane position between the second through hole 32 and the GND pin 12, so that the GND pin 12 and the bypass capacitor 2 of the semiconductor element 1 are arranged.
  • the path of the GND current 41 flowing between the second terminal 22 is the shortest path without bypassing the first power supply wiring 5. For this reason, the current loop between the semiconductor element 1 and the bypass capacitor 2 can be minimized, and radiation noise can be suppressed.

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  • Physics & Mathematics (AREA)
  • Electromagnetism (AREA)
  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Structure Of Printed Boards (AREA)

Abstract

A first terminal (21) of a bypass capacitor (2) is connected to a power supply pin (11) of a semiconductor element (1) and, via a first through hole (31), to first power supply wiring (5). A second terminal (22) of the bypass capacitor (2) is connected to a second through hole (32). A GND pin (12) of the semiconductor element (1) is connected from a first GND wiring (14) to a GND pattern (4) via a third through hole (33). The current flowing between the GND pin (12) and the second through hole (32) is formed not to cross the first power supply wiring (5) by forming the second through hole (32) between the first power supply wiring (5) and the semiconductor element (1). Because of this constitution, an IC and bypass capacitor can be mounted on the same surface of the wiring board and electromagnetic noise can be reduced without using a multilayer wiring board with a complicated structure.

Description

プリント配線基板Printed wiring board
　この発明は、一般的には、プリント配線基板に関し、より特定的には、給電系電磁雑音を低減するためのバイパスコンデンサの実装構造に関するものである。 The present invention generally relates to a printed wiring board, and more particularly to a mounting structure of a bypass capacitor for reducing power feeding system electromagnetic noise.
　半導体素子の高速、高機能化に伴う、半導体素子に集積されるトランジスタ数の増加や、動作周波数の向上により、半導体素子の給電系端子から放射される放射ノイズやＥＭＩ（Electro-Magnetic　Interference：電磁雑音）が増大している。 Due to the increase in the number of transistors integrated in semiconductor elements and the improvement in operating frequency due to higher speed and higher functionality of semiconductor elements, radiation noise radiated from power supply system terminals and EMI (Electro-Magnetic Interference) Noise) is increasing.
　このため、半導体素子を実装するプリント配線基板においては、電源パターンおよびＧＮＤ（グランド）パターンを広い面積で対向させて大きな容量結合を得るようにしたり、電源端子およびＧＮＤ端子の間にバイパスコンデンサを挿入したり、電源線や信号線にローパスフィルタを入れるなどして、このような放射ノイズの対策を行なっている。たとえば、特許文献１（特許第３６１０１２７号公報）および特許文献２（特開２０１０－９８１６２号公報）には、バイパスコンデンサを使用した配線基板が開示されている。 For this reason, in a printed wiring board on which a semiconductor element is mounted, the power supply pattern and the GND (ground) pattern are made to face each other over a wide area so as to obtain a large capacitive coupling, or a bypass capacitor is inserted between the power supply terminal and the GND terminal. And measures against such radiated noise are taken by inserting a low-pass filter in the power line and signal line. For example, Patent Document 1 (Japanese Patent No. 3610127) and Patent Document 2 (Japanese Patent Laid-Open No. 2010-98162) disclose a wiring board using a bypass capacitor.
　特許文献１に開示された印刷回路基板は、絶縁基部を介して表面と裏面とに印刷回路パターンを形成した２層プリント配線板の表面上に、４方向に配線された複数の印刷パターンに電子回路素子を実装するための印刷回路基板である。 The printed circuit board disclosed in Patent Document 1 has a plurality of printed patterns wired in four directions on the front surface of a two-layer printed wiring board in which a printed circuit pattern is formed on the front surface and the back surface through an insulating base. It is a printed circuit board for mounting a circuit element.
　図４Ａは、特許文献１に開示されたプリント配線基板の表面側を示す平面図である。図４Ｂは、特許文献１に開示されたプリント配線基板の裏面側を示す透視平面図である。図４Ａおよび図４Ｂを参照して、表面１０１ａには、電子回路素子を実装する複数のランド１０２が配設されている。表面１０１ａおよび裏面１０１ｂには、接地パターン１０３が配設されている。裏面１０１ｂには、基幹電源パターン１０４が配設されている。裏面１０１ｂには、基幹電源パターン１０４から分岐して複数のランド１０２の一部に接続する、電源分岐パターン１０５が配設されている。電源分岐パターン１０５と接地パターン１０３との間には、バイパスコンデンサが配設されている。電源分岐パターン１０５は、バイパスコンデンサと電源分岐パターン１０５との接続部１０６を基準として、接続部１０６から電子回路と電源分岐パターン１０５とを接続するランド１０２までのインダクタンスよりも、接続部１０６から電源分岐パターン１０５および基幹電源パターン１０４までのインダクタンスが大きくなるように形成されている。 FIG. 4A is a plan view showing the surface side of the printed wiring board disclosed in Patent Document 1. FIG. 4B is a perspective plan view showing the back side of the printed wiring board disclosed in Patent Document 1. FIG. 4A and 4B, a plurality of lands 102 on which electronic circuit elements are mounted are disposed on the surface 101a. A ground pattern 103 is disposed on the front surface 101a and the back surface 101b. A main power supply pattern 104 is disposed on the back surface 101b. On the back surface 101 b, a power supply branch pattern 105 that branches from the main power supply pattern 104 and connects to a part of the plurality of lands 102 is provided. A bypass capacitor is disposed between the power supply branch pattern 105 and the ground pattern 103. The power supply branch pattern 105 is based on the connection portion 106 between the bypass capacitor and the power supply branch pattern 105, and the power supply from the connection portion 106 is higher than the inductance from the connection portion 106 to the land 102 connecting the electronic circuit and the power supply branch pattern 105. The inductance to the branch pattern 105 and the main power supply pattern 104 is formed to be large.
　上記の構成により、理想的なＴ型のローパスフィルタを形成し、電源系の高周波電流のループを小さくすることができ、電源ラインで発生する放射ノイズを小さくすることができる。 With the above configuration, an ideal T-type low-pass filter can be formed, the high frequency current loop of the power supply system can be reduced, and the radiation noise generated in the power supply line can be reduced.
　図５は、特許文献２に開示されたプリント配線基板の構成を示す平面図である。図５を参照して、特許文献２に開示されたプリント配線基板では、プリント配線基板２０１の電源層およびグランド層と接続された電源配線２１０およびグランド引き出し配線２１１により、半導体装置２０２に給電を行っている。半導体装置２０２の電源端子２０３は、電源配線２１０を経由してバイパスコンデンサ２０７に接続されている。バイパスコンデンサ２０７の一端は、電源層と接続されるビアホール２０５を介して電源層へ接続されている。バイパスコンデンサ２０７の他端は、ビアホール２０６ｂを介してグランド層へ接続されている。また、半導体装置２０２のグランド端子２０４は、グランド引き出し配線２１１を経由してビアホール２０６ａを介してグランド層へ接続されている。 FIG. 5 is a plan view showing the configuration of the printed wiring board disclosed in Patent Document 2. FIG. Referring to FIG. 5, in the printed wiring board disclosed in Patent Document 2, power is supplied to semiconductor device 202 by power supply wiring 210 and ground lead wiring 211 connected to the power supply layer and ground layer of printed wiring board 201. ing. The power supply terminal 203 of the semiconductor device 202 is connected to the bypass capacitor 207 via the power supply wiring 210. One end of the bypass capacitor 207 is connected to the power supply layer via a via hole 205 connected to the power supply layer. The other end of the bypass capacitor 207 is connected to the ground layer via the via hole 206b. The ground terminal 204 of the semiconductor device 202 is connected to the ground layer via the via hole 206 a via the ground lead wiring 211.
　上記構成において、バイパスコンデンサ２０７と電源端子２０３とを接続する電源配線２１０と、グランド層と接続されるビアホール２０６ａおよびビアホール２０６ｂとが同一直線状に配置されることにより、電源電流２０８とグランド電流２０９とが密結合状態で流れるため、給電系の低インピーダンス化と電磁雑音の低減とを実現することができる。 In the above configuration, the power supply wiring 210 connecting the bypass capacitor 207 and the power supply terminal 203 and the via hole 206a and the via hole 206b connected to the ground layer are arranged in the same straight line, so that the power supply current 208 and the ground current 209 are arranged. Therefore, the impedance of the power feeding system can be reduced and the electromagnetic noise can be reduced.
特許第３６１０１２７号公報Japanese Patent No. 3610127 特開２０１０－９８１６２号公報JP 2010-98162 A
　しかしながら、上記の特許文献１に開示された印刷回路基板および特許文献２に開示されたプリント配線基板は、下記のような問題を有する。 However, the printed circuit board disclosed in Patent Document 1 and the printed wiring board disclosed in Patent Document 2 have the following problems.
　特許文献１に開示された印刷回路基板は、電源系の高周波電流のループを小さくするため、ＩＣ（Integrated　Circuit）の裏側にバイパスコンデンサを実装する構造を有する。このため、基板の表面と裏面とにＩＣおよびバイパスコンデンサを分けて実装する作業が複雑化したり、プリント配線基板の厚さが増加したりする問題がある。 The printed circuit board disclosed in Patent Document 1 has a structure in which a bypass capacitor is mounted on the back side of an IC (Integrated Circuit) in order to reduce a high frequency current loop of a power supply system. For this reason, there are problems that the work of separately mounting the IC and the bypass capacitor on the front surface and the back surface of the substrate is complicated, and the thickness of the printed wiring board is increased.
　また、特許文献２に開示されたプリント配線基板では、プリント配線基板２０１として、電源層とグランド層とを異なる層構造として多層配線基板を用いることにより、上記の構成を達成している。このため、基板の構造が複雑になるという問題がある。 In the printed wiring board disclosed in Patent Document 2, the above-described configuration is achieved by using a multilayer wiring board having a power supply layer and a ground layer as different layer structures as the printed wiring board 201. For this reason, there exists a problem that the structure of a board | substrate becomes complicated.
　そこでこの発明の課題は、上記の課題を解決することであり、構造が複雑な多層配線基板を用いずに、ＩＣおよびバイパスコンデンサを配線基板の同一面上に実装できるとともに、電磁雑音を低減できるプリント配線基板を提供することである。 Therefore, an object of the present invention is to solve the above-mentioned problem, and an IC and a bypass capacitor can be mounted on the same surface of the wiring board without using a multilayer wiring board having a complicated structure, and electromagnetic noise can be reduced. It is to provide a printed wiring board.
　この発明に従ったプリント配線基板は、第１面に実装された半導体素子およびバイパスコンデンサと、第２面に形成された第１電源配線およびＧＮＤパターンとを備える。半導体素子は、電源ピンおよびＧＮＤピンを有する。プリント配線基板は、第１面に形成された第１ＧＮＤ配線および第２ＧＮＤ配線と、第１スルーホール、第２スルーホールおよび第３スルーホールとをさらに備える。バイパスコンデンサの第１端子は、電源ピンと、第１スルーホールを介して第１電源配線とに接続される。バイパスコンデンサの第２端子は、第２スルーホールに接続される。半導体素子のＧＮＤピンは、第１面上の第１ＧＮＤ配線から第３スルーホールを介してＧＮＤパターンに接続される。第２スルーホールを第１電源配線と半導体素子との間に形成することにより、ＧＮＤピンと第２スルーホールとの間に流れる電流が第１電源配線と交差しないように形成される。 The printed wiring board according to the present invention includes a semiconductor element and a bypass capacitor mounted on the first surface, and a first power supply wiring and a GND pattern formed on the second surface. The semiconductor element has a power supply pin and a GND pin. The printed wiring board further includes a first GND wiring and a second GND wiring formed on the first surface, a first through hole, a second through hole, and a third through hole. The first terminal of the bypass capacitor is connected to the power supply pin and the first power supply wiring through the first through hole. The second terminal of the bypass capacitor is connected to the second through hole. The GND pin of the semiconductor element is connected to the GND pattern from the first GND wiring on the first surface through the third through hole. By forming the second through hole between the first power supply wiring and the semiconductor element, the current flowing between the GND pin and the second through hole is formed so as not to cross the first power supply wiring.
　以上に説明したように、この発明に従えば、構造が複雑な多層配線基板を用いずに、ＩＣおよびバイパスコンデンサを配線基板の同一面上に実装できるとともに、電磁雑音を低減できるプリント配線基板を提供することができる。 As described above, according to the present invention, an IC and a bypass capacitor can be mounted on the same surface of a wiring board without using a multilayer wiring board having a complicated structure, and a printed wiring board that can reduce electromagnetic noise is provided. Can be provided.
この発明の実施の形態１におけるプリント配線基板の表面側を示す平面図である。It is a top view which shows the surface side of the printed wiring board in Embodiment 1 of this invention. この発明の実施の形態１におけるプリント配線基板の裏面側を示す透視平面図である。It is a see-through | perspective plan view which shows the back surface side of the printed wiring board in Embodiment 1 of this invention. この発明の実施の形態１におけるプリント配線基板の表面側と裏面側を重ねて示した透視平面図である。It is the see-through | perspective plan view which piled up and showed the surface side and back surface side of the printed wiring board in Embodiment 1 of this invention. プリント配線基板を近傍磁界解析した結果であり、基板の表面側を示す電流分布図である。It is the result of having carried out the near magnetic field analysis of the printed wiring board, and is a current distribution diagram showing the surface side of the board. プリント配線基板を近傍磁界解析した結果であり、基板の裏面側を示す電流分布図である。It is the result of having carried out the near magnetic field analysis of the printed wiring board, and is a current distribution diagram showing the back side of the board. この発明の実施の形態２におけるプリント配線基板の表面側と裏面側とを重ねて示した透視平面図である。It is the see-through | perspective plan view which piled up and showed the surface side and back surface side of the printed wiring board in Embodiment 2 of this invention. この発明の実施の形態２における別のプリント配線基板の表面側と裏面側とを重ねて示した透視平面図である。It is the see-through | perspective plan view which piled up and showed the surface side and back surface side of another printed wiring board in Embodiment 2 of this invention. この発明の実施の形態２におけるさらに別のプリント配線基板の表面側と裏面側とを重ねて示した透視平面図である。It is the see-through | perspective top view which piled up and showed the surface side and back surface side of another printed wiring board in Embodiment 2 of this invention. 特許文献１に開示されたプリント配線基板の表面側を示す平面図である。10 is a plan view showing a surface side of a printed wiring board disclosed in Patent Document 1. FIG. 特許文献１に開示されたプリント配線基板の裏面側を示す透視平面図である。FIG. 6 is a perspective plan view showing the back side of a printed wiring board disclosed in Patent Document 1. 特許文献２に開示されたプリント配線基板の構成を示す平面図である。10 is a plan view showing a configuration of a printed wiring board disclosed in Patent Document 2. FIG.
　この発明の実施の形態について、図面を参照して説明する。なお、以下で参照する図面では、同一またはそれに相当する部材には、同じ番号が付されている。 Embodiments of the present invention will be described with reference to the drawings. In the drawings referred to below, the same or corresponding members are denoted by the same reference numerals.
　（実施の形態１）
　図１Ａは、この発明の実施の形態１におけるプリント配線基板の表面側を示す平面図である。図１Ｂは、この発明の実施の形態１におけるプリント配線基板の裏面側を示す透視平面図である。図１Ｃは、この発明の実施の形態１におけるプリント配線基板の表面側と裏面側を重ねて示した透視平面図である。図１Ａ、図１Ｂおよび図１Ｃを参照して、本実施の形態におけるプリント配線基板においては、絶縁基部の表面と裏面とにそれぞれパターンが形成され、多層プリント配線基板よりも簡単な構造を有する２層プリント配線基板が用いられている。 (Embodiment 1)
FIG. 1A is a plan view showing the surface side of the printed wiring board according to Embodiment 1 of the present invention. FIG. 1B is a perspective plan view showing the back side of the printed wiring board according to Embodiment 1 of the present invention. FIG. 1C is a perspective plan view showing the front surface side and the back surface side of the printed wiring board according to Embodiment 1 of the present invention superimposed on each other. Referring to FIGS. 1A, 1B, and 1C, in the printed wiring board according to the present embodiment, patterns are formed on the front surface and the back surface of the insulating base, respectively, and the structure is simpler than that of the multilayer printed wiring board. A layer printed wiring board is used.
　プリント配線基板の第１面としての表面側には、図１Ａに示されるように、半導体素子１とバイパスコンデンサ２とが実装される実装領域３が設けられている。プリント配線基板の第２面としての裏面側には、図１Ｂに示されるように、第２面の多くの面積を占めるＧＮＤパターン４と、ＧＮＤパターン４と絶縁分離された第１電源配線５とが形成されている。実装領域３の周囲は、外部からの放射ノイズの混入を防止するために、導電性のＧＮＤパターン６により覆われている。 As shown in FIG. 1A, a mounting region 3 on which the semiconductor element 1 and the bypass capacitor 2 are mounted is provided on the surface side as the first surface of the printed wiring board. As shown in FIG. 1B, on the back surface side as the second surface of the printed wiring board, a GND pattern 4 occupying a large area of the second surface, and a first power supply wiring 5 insulated and separated from the GND pattern 4 Is formed. The periphery of the mounting region 3 is covered with a conductive GND pattern 6 in order to prevent external radiation noise from entering.
　半導体素子１は、その周囲に、給電用の電源ピン１１およびＧＮＤピン１２を含む複数の接続ピンを有する。電源ピン１１が第２電源配線１３に接続され、ＧＮＤピン１２が第１ＧＮＤ配線１４に接続されている。 The semiconductor element 1 has a plurality of connection pins including a power supply pin 11 and a GND pin 12 for power supply around the semiconductor element 1. The power supply pin 11 is connected to the second power supply wiring 13, and the GND pin 12 is connected to the first GND wiring 14.
　バイパスコンデンサ２は、半導体素子１の電源ピン１１の近傍に配置されている。バイパスコンデンサ２の第１端子２１が、第２電源配線１３によって電源ピン１１と接続され、バイパスコンデンサ２の第２端子２２が、第２ＧＮＤ配線１５に接続されている。 The bypass capacitor 2 is disposed in the vicinity of the power supply pin 11 of the semiconductor element 1. The first terminal 21 of the bypass capacitor 2 is connected to the power supply pin 11 by the second power supply wiring 13, and the second terminal 22 of the bypass capacitor 2 is connected to the second GND wiring 15.
　さらに、プリント配線基板の第１面および第２面においては、図１Ｃに示されるように、第１面の第２電源配線１３および第２面の第１電源配線５が、バイパスコンデンサ２の第１端子２１の近傍に配置された第１スルーホール３１を介して互いに接続されている。 Further, on the first surface and the second surface of the printed circuit board, as shown in FIG. 1C, the second power supply wiring 13 on the first surface and the first power supply wiring 5 on the second surface are connected to the second power supply wiring 13 of the bypass capacitor 2. They are connected to each other through a first through hole 31 disposed in the vicinity of one terminal 21.
　また、第１面の第２ＧＮＤ配線１５および第２面のＧＮＤパターン４が、基板面内の第１電源配線５と半導体素子１との間に配置された第２スルーホール３２を介して互いに接続されている。第１面の第１ＧＮＤ配線１４および第２面のＧＮＤパターン４が、第２スルーホール３２とＧＮＤピン１２との間に配置された第３スルーホール３３を介して互いに接続されている。 Further, the second GND wiring 15 on the first surface and the GND pattern 4 on the second surface are connected to each other through the second through hole 32 disposed between the first power supply wiring 5 and the semiconductor element 1 in the substrate surface. Has been. The first GND wiring 14 on the first surface and the GND pattern 4 on the second surface are connected to each other via a third through hole 33 disposed between the second through hole 32 and the GND pin 12.
　上記の構成において、第２スルーホール３２が基板面内の第１電源配線５と半導体素子１との間に配置されることにより、ＧＮＤピン１２および第２スルーホール３２の間に流れるＧＮＤ電流４１の経路が、第１電源配線５と交差することなく略直線上に形成される。このため、半導体素子１とバイパスコンデンサ２との間の電流ループが小さくなり、半導体素子１の給電系から発生する電磁雑音を低減することができる。 In the above configuration, the second through hole 32 is disposed between the first power supply wiring 5 and the semiconductor element 1 in the substrate surface, so that the GND current 41 flowing between the GND pin 12 and the second through hole 32 is obtained. Is formed on a substantially straight line without intersecting the first power supply wiring 5. For this reason, the current loop between the semiconductor element 1 and the bypass capacitor 2 is reduced, and electromagnetic noise generated from the power feeding system of the semiconductor element 1 can be reduced.
　また、第１スルーホール３１、第２スルーホール３２および第３スルーホール３３は、上記の範囲内で配置を調整することが可能である。たとえば、半導体素子１のＧＮＤピン１２とバイパスコンデンサ２の第２端子２２との間に流れるＧＮＤ電流４１の経路と、半導体素子１の電源ピン１１とバイパスコンデンサ２の第１端子２１との間に流れる電源電流４２の経路とが略平行となるように、第１スルーホール３１、第２スルーホール３２および第３スルーホール３３を配置することにより、ＧＮＤ電流４１と電源電流４２との未結合電流が減少し、給電系インピーダンスを低減させることができる。 Further, the arrangement of the first through hole 31, the second through hole 32, and the third through hole 33 can be adjusted within the above range. For example, the path of the GND current 41 flowing between the GND pin 12 of the semiconductor element 1 and the second terminal 22 of the bypass capacitor 2 and between the power supply pin 11 of the semiconductor element 1 and the first terminal 21 of the bypass capacitor 2. By disposing the first through hole 31, the second through hole 32, and the third through hole 33 so that the path of the flowing power supply current 42 is substantially parallel, the uncoupled current between the GND current 41 and the power supply current 42 The power supply system impedance can be reduced.
　図２Ａは、プリント配線基板を近傍磁界解析した結果であり、基板の表面側を示す電流分布図である。図２Ｂは、プリント配線基板を近傍磁界解析した結果であり、基板の裏面側を示す電流分布図である。図中では、図１と同じ部分を示す個所には同じ符号が付記されている。 FIG. 2A is a current distribution diagram showing the surface side of the substrate, which is the result of the near magnetic field analysis of the printed wiring board. FIG. 2B is a current distribution diagram showing the result of the near magnetic field analysis of the printed wiring board and showing the back side of the board. In the figure, the same reference numerals are given to the portions showing the same parts as in FIG.
　本実施の形態におけるプリント配線基板においては、図２Ａに示されるように、電源ピン１１およびバイパスコンデンサ２の間に流れる電源電流４２と、図２Ｂに示されるように、ＧＮＤパターン４に設けられた第２スルーホール３２および第３スルーホール３３の間に流れるＧＮＤ電流４１とが、第１電源配線５を迂回せずに最短経路で流れる。 In the printed wiring board according to the present embodiment, as shown in FIG. 2A, the power supply current 42 flowing between the power supply pin 11 and the bypass capacitor 2 and the GND pattern 4 as shown in FIG. 2B are provided. The GND current 41 flowing between the second through hole 32 and the third through hole 33 flows through the shortest path without bypassing the first power supply wiring 5.
　（実施の形態２）
　図３Ａ、図３Ｂおよび図３Ｃは、この発明の実施の形態２におけるプリント配線基板の表面側と裏面側とを重ねて示した透視平面図である。本実施の形態におけるプリント配線基板は、第１スルーホール３１、第２スルーホール３２、第３スルーホール３３およびバイパスコンデンサ２の配置を変更したものであり、他の構成については実施の形態１と同じである。以下、実施の形態１と重複する構造については、その説明を繰り返さない。 (Embodiment 2)
3A, 3B, and 3C are perspective plan views showing the front surface side and the back surface side of the printed wiring board according to Embodiment 2 of the present invention in an overlapping manner. The printed wiring board in the present embodiment is obtained by changing the arrangement of the first through hole 31, the second through hole 32, the third through hole 33, and the bypass capacitor 2. Other configurations are the same as those in the first embodiment. The same. Hereinafter, the description of the same structure as in the first embodiment will not be repeated.
　図３Ａを参照して、第１スルーホール３１が、第１電源配線５の外側に配置されている。このような構成では、第１電源配線５が半導体素子１およびバイパスコンデンサ２の間の電流ループに重なるため、ノイズ抑制の効果は下がる。一方、第１スルーホール３１および第２スルーホール３２の間に第１電源配線５を収めることができるため、裏面側の回路面積を小さくまとめることができる。 Referring to FIG. 3A, the first through hole 31 is arranged outside the first power supply wiring 5. In such a configuration, since the first power supply wiring 5 overlaps the current loop between the semiconductor element 1 and the bypass capacitor 2, the effect of noise suppression is reduced. On the other hand, since the first power supply wiring 5 can be accommodated between the first through hole 31 and the second through hole 32, the circuit area on the back surface side can be reduced.
　図３Ｂを参照して、バイパスコンデンサ２の短手方向の両側に第１スルーホール３１および第２スルーホール３２が配置されている。このような構成では、バイパスコンデンサ２および第２スルーホール３２を半導体素子１に近づけて配置できるため、半導体素子１およびバイパスコンデンサ２の間の電流ループを小さくすることができる。また、表面側の実装領域３を小さくすることができるため、プリント配線基板を小型化することができる。 Referring to FIG. 3B, the first through hole 31 and the second through hole 32 are disposed on both sides of the bypass capacitor 2 in the short direction. In such a configuration, since the bypass capacitor 2 and the second through hole 32 can be arranged close to the semiconductor element 1, the current loop between the semiconductor element 1 and the bypass capacitor 2 can be reduced. Further, since the mounting region 3 on the front surface side can be reduced, the printed wiring board can be reduced in size.
　図３Ｃを参照して、バイパスコンデンサ２の長手方向の両側に第１スルーホール３１および第２スルーホール３２が配置されている。このような構成では、第１電源配線５を半導体素子１に近づけて配置できるため、裏面側の回路面積や表面側の実装領域３を小さくすることができ、プリント配線基板をさらに小型化することができる。 Referring to FIG. 3C, the first through hole 31 and the second through hole 32 are arranged on both sides of the bypass capacitor 2 in the longitudinal direction. In such a configuration, since the first power supply wiring 5 can be arranged close to the semiconductor element 1, the circuit area on the back surface side and the mounting region 3 on the front surface side can be reduced, and the printed wiring board can be further miniaturized. Can do.
　なお、実施の形態１および実施の形態２における他の構成の配置として、半導体素子１のＧＮＤピン１２が、電源ピン１１と同じ辺部や、別の上辺部、下辺部に設けられている場合を想定する。このような場合であっても、第３スルーホール３３が第２スルーホール３２とＧＮＤピン１２との間の面内位置に配置されることにより、半導体素子１のＧＮＤピン１２とバイパスコンデンサ２の第２端子２２との間に流れるＧＮＤ電流４１の経路が、第１電源配線５を迂回することなく最短経路となる。このため、半導体素子１およびバイパスコンデンサ２の間の電流ループを最小とすることができ、放射ノイズを抑えることができる。 As another arrangement in the first embodiment and the second embodiment, the GND pin 12 of the semiconductor element 1 is provided on the same side as the power supply pin 11 or on another upper side and lower side. Is assumed. Even in such a case, the third through hole 33 is disposed in the in-plane position between the second through hole 32 and the GND pin 12, so that the GND pin 12 and the bypass capacitor 2 of the semiconductor element 1 are arranged. The path of the GND current 41 flowing between the second terminal 22 is the shortest path without bypassing the first power supply wiring 5. For this reason, the current loop between the semiconductor element 1 and the bypass capacitor 2 can be minimized, and radiation noise can be suppressed.
　また、本発明は上述した実施の形態に限定されるものではなく、請求項に示した範囲で種々の変更が可能であり、実施の形態に開示された技術的手段を組み合わせて得られる実施の形態についても本発明の技術的範囲に含まれる。 Further, the present invention is not limited to the above-described embodiments, and various modifications are possible within the scope shown in the claims, and the embodiments obtained by combining the technical means disclosed in the embodiments. The form is also included in the technical scope of the present invention.
　たとえば、各実施の形態において、半導体素子１に対してバイパスコンデンサ２を１個実装する例を示したが、半導体素子１が複数の電源ピン１１を有するときは、各電源ピン１１のそれぞれにバイパスコンデンサ２を配置して、本発明を適用することが可能である。 For example, in each embodiment, an example in which one bypass capacitor 2 is mounted on the semiconductor element 1 has been described. However, when the semiconductor element 1 has a plurality of power supply pins 11, a bypass is provided for each power supply pin 11. It is possible to apply the present invention by disposing the capacitor 2.
　１　半導体素子、２　コンデンサ、３　実装領域、４　ＧＮＤパターン（裏面側）、５　第１電源配線、６　ＧＮＤパターン（表面側）、１１　電源ピン、１２　ＧＮＤピン、１３　第２電源配線、１４　第１ＧＮＤ配線、１５　第２ＧＮＤ配線、２１　第１端子、２２　第２端子、３１　第１スルーホール、３２　第２スルーホール、３３　第３スルーホール、４１　ＧＮＤ電流、４２　電源電流。 1 semiconductor element, 2 capacitor, 3 mounting area, 4 GND pattern (back side), 5 1st power supply wiring, 6 GND pattern (front side), 11 power supply pin, 12 GND pin, 13 2nd power supply wiring, 14 1st GND Wiring, 15 2nd GND wiring, 21 1st terminal, 22 2nd terminal, 31 1st through hole, 32 2nd through hole, 33 3rd through hole, 41 GND current, 42 power supply current.

Claims (4)

  1. 　第１面に実装された半導体素子（１）およびバイパスコンデンサ（２）と、第２面に形成された第１電源配線（５）およびＧＮＤパターン（４）とを備えるプリント配線基板であって、
    　前記半導体素子（１）は、電源ピン（１１）およびＧＮＤピン（１２）を有し、
    　前記プリント配線基板は、第１面に形成された第１ＧＮＤ配線（１４）および第２ＧＮＤ配線（１５）と、第１スルーホール（３１）、第２スルーホール（３２）および第３スルーホール（３３）とをさらに備え、
    　前記バイパスコンデンサ（２）の第１端子（２１）は、前記電源ピン（１１）と、前記第１スルーホール（３１）を介して前記第１電源配線（５）とに接続され、
    　前記バイパスコンデンサ（２）の第２端子（２２）は、前記第２スルーホール（３２）に接続され、
    　前記半導体素子（１）の前記ＧＮＤピン（１２）は、第１面上の前記第１ＧＮＤ配線（１４）から前記第３スルーホール（３３）を介して前記ＧＮＤパターン（４）に接続され、
    　前記第２スルーホール（３２）を前記第１電源配線（５）と前記半導体素子（１）との間に形成することにより、前記ＧＮＤピン（１２）と前記第２スルーホール（３２）との間に流れる電流が前記第１電源配線（５）と交差しないように形成される、プリント配線基板。     A printed wiring board comprising a semiconductor element (1) and a bypass capacitor (2) mounted on a first surface, and a first power supply wiring (5) and a GND pattern (4) formed on a second surface,
    The semiconductor element (1) has a power supply pin (11) and a GND pin (12),
    The printed wiring board includes a first GND wiring (14) and a second GND wiring (15) formed on a first surface, a first through hole (31), a second through hole (32), and a third through hole (33). )
    The first terminal (21) of the bypass capacitor (2) is connected to the power supply pin (11) and the first power supply wiring (5) through the first through hole (31),
    The second terminal (22) of the bypass capacitor (2) is connected to the second through hole (32),
    The GND pin (12) of the semiconductor element (1) is connected to the GND pattern (4) from the first GND wiring (14) on the first surface through the third through hole (33),
    By forming the second through hole (32) between the first power supply wiring (5) and the semiconductor element (1), the GND pin (12) and the second through hole (32) A printed wiring board formed so that a current flowing therebetween does not intersect the first power supply wiring (5).
  2. 　前記半導体素子（１）と前記バイパスコンデンサ（２）との間に形成される電流ループに重ならないように前記第１電源配線（５）が配置されている、請求項１に記載のプリント配線基板。 The printed wiring board according to claim 1, wherein the first power supply wiring (5) is disposed so as not to overlap a current loop formed between the semiconductor element (1) and the bypass capacitor (2). .
  3. 　前記半導体素子（１）と前記バイパスコンデンサ（２）との間に形成される電流ループが最小となる位置に、前記バイパスコンデンサ（２）、前記第２スルーホール（３２）および前記第３スルーホール（３３）が配置されている、請求項１に記載のプリント配線基板。 The bypass capacitor (2), the second through hole (32), and the third through hole are located at positions where a current loop formed between the semiconductor element (1) and the bypass capacitor (2) is minimized. The printed wiring board according to claim 1, wherein (33) is arranged.
  4. 　前記第２スルーホール（３２）および前記第３スルーホール（３３）は、前記バイパスコンデンサ（２）の第１端子（２１）と前記電源ピン（１１）とを接続する第２電源配線（１３）と略平行になるように配置されている、請求項１に記載のプリント配線基板。 The second through-hole (32) and the third through-hole (33) are connected to the second power supply wiring (13) for connecting the first terminal (21) of the bypass capacitor (2) and the power supply pin (11). The printed wiring board according to claim 1, wherein the printed wiring board is disposed so as to be substantially parallel to the printed circuit board.
PCT/JP2012/062122 2011-05-12 2012-05-11 Printed wiring board WO2012153835A1 (en)

Applications Claiming Priority (2)

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JP2011-106852 2011-05-12
JP2011106852A JP2012238724A (en) 2011-05-12 2011-05-12 Printed wiring board

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WO2012153835A1 true WO2012153835A1 (en) 2012-11-15

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103531552A (en) * 2013-10-25 2014-01-22 深圳市华星光电技术有限公司 Chip structure and circuit structure

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN108463048B (en) 2017-02-21 2022-04-15 拉碧斯半导体株式会社 Substrate circuit device

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0954788A (en) * 1995-08-11 1997-02-25 Canon Inc Method for designing printing circuit board, printing circuit board and electronic equipment provided with printing circuit board
JP2000091785A (en) * 1998-09-14 2000-03-31 Yaskawa Electric Corp Power-supply-pattern-connection structure of electronic circuit component
WO2006112010A1 (en) * 2005-04-13 2006-10-26 Renesas Technology Corp. Electronic device
JP2009224735A (en) * 2008-03-19 2009-10-01 Nec Infrontia Corp Multilayer printed circuit board and electronic equipment using the same

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0954788A (en) * 1995-08-11 1997-02-25 Canon Inc Method for designing printing circuit board, printing circuit board and electronic equipment provided with printing circuit board
JP2000091785A (en) * 1998-09-14 2000-03-31 Yaskawa Electric Corp Power-supply-pattern-connection structure of electronic circuit component
WO2006112010A1 (en) * 2005-04-13 2006-10-26 Renesas Technology Corp. Electronic device
JP2009224735A (en) * 2008-03-19 2009-10-01 Nec Infrontia Corp Multilayer printed circuit board and electronic equipment using the same

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103531552A (en) * 2013-10-25 2014-01-22 深圳市华星光电技术有限公司 Chip structure and circuit structure
US9345124B2 (en) 2013-10-25 2016-05-17 Shenzhen China Star Optoelectronics Technology Co., Ltd. Chip and circuit structure

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