JP4983906B2 - Electronic component built-in module - Google Patents

Description

  The present invention relates to an electronic component built-in module in which an electronic component is embedded (built in) inside a substrate.

  In recent years, modularization has been implemented in which electronic components such as active components such as semiconductor devices such as IC chips (bare chips: die) used in electronic devices and passive components such as capacitors (capacitors), inductors, thermistors, resistors, etc. are mounted. Therefore, there is an increasing desire for miniaturization and thinning of such modules.

  In order to meet such a demand, for example, in Patent Document 1, as a module on which an active component or a passive component is mounted, a stud output terminal higher than the electronic component is provided on a substrate on which the electronic component is placed. There has been proposed a microconverter in which an electronic component and a microinductor are arranged so as to be placed in a vertical direction with respect to a substrate surface by installing a microinductor thereon. It is used as.

Japanese Patent Laid-Open No. 2004-63676

  In the micro-converter as the power supply circuit having such a structure, the electronic components constituting the power supply circuit have been reduced in voltage, current and frequency, and the structure is further increased. There is a need to ensure placement restrictions and mechanical strength associated with downsizing. As a result, in the structure of the microconverter as disclosed in Patent Document 1, various wiring patterns (conductors) constituting various signal lines are formed close to each other, and the distance between the conductors is thus reduced. If it is very short, an equivalent capacitor (capacitor) is formed between these conductors by capacitive coupling (capacitive coupling) which is a kind of electrostatic coupling. In this case, each signal passing through various signal lines includes a high-frequency noise component due to such capacitive coupling. Capacitive coupling that can occur equivalently in this way can cause malfunction, functional failure, and performance degradation of the power supply circuit and its control circuit.

  For example, a power supply circuit that performs voltage conversion generally feeds back an output voltage (a voltage after smoothing a switched high-frequency voltage) to a control circuit to maintain a reference voltage constant. A signal line is formed. When the feedback signal line and the driving signal line for driving the power supply circuit are formed close to each other, the distance between these different types of signal lines is short. Therefore, it is very susceptible to the above-described capacitive coupling (noise is likely to enter through the capacitive coupling). Therefore, the feedback signal is disturbed, it becomes difficult to keep the reference voltage of the power supply circuit constant, and it is difficult to perform desired accurate voltage conversion (that is, the power supply circuit malfunctions). More generally speaking, the feedback signal line is capacitively coupled with the driving signal line formed in the vicinity thereof, and is one of the major factors that induce deterioration in the purity of various signals including the feedback signal. turn into.

  Therefore, the present invention has been made in view of such circumstances, and noise caused by capacitive coupling that may be caused when various signal lines are formed close to each other, and noise that affects various signal lines. It is an object of the present invention to provide an electronic component built-in module that can be sufficiently suppressed or blocked, thereby reliably preventing malfunction of an electronic circuit and stably maintaining accurate operation.

  In order to solve the above problems, an electronic component built-in module according to the present invention includes a substrate in which a first electronic component is incorporated, and a second electronic component placed on the substrate. , A feedback signal line for monitoring an output signal output from the electronic component built-in module via the second electronic component, and a switching signal line connected to the second electronic component are provided. Each of the signal lines, that is, the feedback signal line and the switching signal line has a portion extending in a direction away from each other (so as to be separated from each other) in the surface direction of the substrate. In other words, at least one of the feedback signal line and the switching signal line extends at a part of the signal line away from the other. Alternatively, the feedback signal line and the switching signal line may be expressed as including portions that do not extend in parallel to each other.

  In the above configuration, the surface direction of the substrate (plan view when the substrate is viewed from the vertical direction; the same applies hereinafter), the feedback signal line, and the switching signal line respectively extend in directions away from each other. Therefore, at least in those portions, the feedback signal line is kept away from the switching signal line. Therefore, a signal (switching signal) passing through the switching signal line includes a noise (high frequency noise and / or harmonic noise) component, and the noise is a feedback signal through capacitive coupling of both signal lines. Even if it tries to penetrate (transmit) or enter the line, the formation of the capacitive coupling is prevented (blocked, avoided) or the magnitude of the capacitive coupling is reduced, so that the signal for feedback from the switching signal line. Noise that can enter the line is easily suppressed or blocked.

  In other words, since the distance between the signal lines increases, the distance between the electrodes of the equivalent (virtual) capacitor that forms the capacitive coupling increases, so that it is difficult to form capacitive coupling or the capacitance is reduced. Therefore, noise that can enter or enter through the capacitive coupling is reduced or reduced. As a result, a feedback signal with high reliability, that is, high purity is ensured, and even when the electronic component built-in substrate (and thus the electronic component built-in module) has a multilayer and complicated wiring structure, the complicated signal path is traced. Signal transmission can be performed stably.

  In the present specification, the “electronic component built-in substrate” means not only an individual substrate (individual piece, individual product) which is a unit substrate in which the first electronic component is built, but also an aggregate substrate having a plurality of the individual substrates ( The “first electronic component” is not particularly limited in its type, for example, an active component such as a semiconductor device such as an IC chip used in a normal electronic device, Specifically, for example, a digital IC having a very high operating frequency such as a CPU (Central Processing Unit) or a DSP (Digital Signal Processor), or an analog IC such as a high-frequency amplifier, an antenna switch, or a high-frequency oscillation circuit can be given. It is done. Further, the type of “second electronic component” mounted on the “electronic component built-in substrate” and constituting a part of the “electronic component built-in module” is not particularly limited. It is a passive component that is a source of electromagnetic waves (noise) such as an inductor, and is particularly effective when it is switched at high speed.

  Also, the substrate is provided with a signal line for input voltage input to the electronic component built-in module, and the signal line for feedback and the signal line for input voltage are separated from each other in the plane direction of the substrate. It has a part extending in the direction. In other words, at least one of the feedback signal line and the input voltage signal line extends away from the other in at least a part of the signal line.

  In the above configuration, the feedback signal line and the input voltage signal line each have a portion extending away from each other in the surface direction of the substrate (when the substrate is viewed in plan). At least in those portions, the feedback signal line is also kept away from the input voltage signal line. Therefore, noise (high frequency noise and / or harmonic noise) component is included in the signal (input voltage signal) that passes through the signal line for input voltage, and the noise is used for feedback through capacitive coupling of both signal lines. Even if it tries to enter or enter the signal line, the formation of the capacitive coupling is prevented or the magnitude of the capacitive coupling is reduced, so that the signal line for the input voltage can enter the signal line for the feedback. Noise is easily suppressed or blocked, and as a result, a highly pure feedback signal is further ensured.

  Moreover, it is preferable that a first ground layer connected to a predetermined ground potential is formed on the substrate between the feedback signal line and the second electronic component.

  With this configuration, the first ground layer is laid so as to cover (cover) the feedback signal line from the second electronic component, so that magnetic flux is generated from the second electronic component (for example, the inductor). Even if leakage occurs (the leakage magnetic flux becomes a high-frequency noise component and affects the power supply circuit), the first ground layer functions as an electromagnetic wave shield against electromagnetic waves that can be incident on the feedback signal line from the outside. To do. Thus, the feedback signal line is not affected by noise caused by the leakage magnetic flux generated from the second electronic component, and a stable operation is ensured. Further, if the grounded first ground layer is formed so that the feedback signal line is also covered (covered) by other signal lines such as the switching signal line, the feedback signal line is provided. Since mutual interference and capacitive coupling between the signal line and other signal lines such as a switching signal line are prevented, noise resulting from the capacitive coupling can be more effectively suppressed and blocked.

  More specifically, when the first ground layer is formed so as to cover the mounting region of the first electronic component and to have a larger area than the mounting region of the first electronic component in the surface direction of the substrate, Since the function as an electromagnetic wave shield is further improved, it is suitable.

  Furthermore, it is preferable that a second ground layer connected to a predetermined ground potential is formed on the substrate in the vicinity of the signal line for switching. If comprised in this way, it will become easy to interpose a 2nd ground layer between the signal line for switching, and the signal line for feedback which is other signal lines. Alternatively, since the second ground layer is close to the switching signal line, one of the switching signal line and the feedback signal line is easily covered with the other. Therefore, mutual interference and capacitive coupling between the switching signal line and the feedback signal line are further prevented, so that noise caused by the capacitive coupling can be more effectively suppressed and blocked.

  Further, since the second ground layer can also function as an electromagnetic wave shield against electromagnetic waves that can be incident on the feedback signal line from the outside, it is possible to further stabilize the signal passing through the feedback signal line. Further, in a circuit that performs switching control at a high frequency (high speed), noise is particularly likely to occur at the time of a sharp signal rising or falling, but by providing such a second ground layer, such a timing is provided. The generation of noise that is likely to occur is suppressed. From these viewpoints, it is more effective that the second ground layer is provided in the same layer as the layer in which the feedback signal line is formed.

  The feedback signal line is formed to include a portion extending so as to cross at least one of the switching signal line and the input voltage signal line in the surface direction of the substrate. With this configuration, the switching signal line and the input voltage signal line are formed in the same layer as the feedback signal line and close to the feedback signal line. Even in such a case, there are always portions where the switching signal line and the input voltage signal line are not parallel to the feedback signal line. Therefore, in such a part, capacitive coupling between the feedback signal line and another signal line is extremely difficult to occur. Therefore, the noise from each of the switching signal line and the input voltage signal line can be further effectively suppressed from entering or entering the feedback signal line via capacitive coupling.

  Further, when the first electronic component is arranged so that the output terminal of the first electronic component faces away from the second electronic component (so-called face-down), the output terminal of the first electronic component is The output terminal of the first electronic component can be further separated from the second electronic component as compared with the case where it is arranged to face the second electronic component side, and is structurally positioned around the first electronic component. A possible signal line is also moved relatively far away from the second electronic component. Therefore, the noise caused by the coupling of the noise caused by the leakage magnetic flux from the second electronic component to the feedback signal line can be further suppressed and blocked.

  According to the electronic component built-in module of the present invention, the feedback signal line and the switching signal line each have a portion extending in a direction away from each other in the surface direction of the substrate. Even if the switching signal lines are formed close to each other, it is possible to prevent the capacitive coupling from being formed between the signal lines or to reduce the size of the capacitive coupling. This makes it possible to suppress or block noise that can enter the signal line for feedback via such capacitive coupling, thereby reliably preventing malfunctions of the electronic component built-in module, etc. Can be maintained.

1 is a cross-sectional view schematically showing a structure of a DCDC converter 1 which is a preferred embodiment of an electronic component built-in module according to the present invention. FIG. 2 is an equivalent circuit diagram of the DCDC converter 1 shown in FIG. 1. It is process drawing which shows an example of the procedure which manufactures the electronic component built-in board | substrate 2. As shown in FIG. It is process drawing which shows an example of the procedure which manufactures the electronic component built-in board | substrate 2. As shown in FIG. It is process drawing which shows an example of the procedure which manufactures the electronic component built-in board | substrate 2. As shown in FIG. It is process drawing which shows an example of the procedure which manufactures the electronic component built-in board | substrate 2. As shown in FIG. It is process drawing which shows an example of the procedure which manufactures the electronic component built-in board | substrate 2. As shown in FIG. It is process drawing which shows an example of the procedure which manufactures the electronic component built-in board | substrate 2. As shown in FIG. It is process drawing which shows an example of the procedure which manufactures the electronic component built-in board | substrate 2. As shown in FIG. It is process drawing which shows an example of the procedure which manufactures the electronic component built-in board | substrate 2. As shown in FIG. It is process drawing which shows an example of the procedure which manufactures the electronic component built-in board | substrate 2. As shown in FIG. It is process drawing which shows an example of the procedure which manufactures the electronic component built-in board | substrate 2. As shown in FIG. It is process drawing which shows an example of the procedure which manufactures the electronic component built-in board | substrate 2. As shown in FIG. It is principal part sectional drawing which showed typically the electronic component built-in board 2 of this embodiment. It is a wiring diagram when the 1st wiring layer 31 is planarly viewed from the ground side along the II line shown in FIG. It is a wiring diagram when the 2nd wiring layer 32 is planarly viewed from the ground side along the II-II line shown in FIG. FIG. 15 is a structural diagram of the electronic component built-in substrate 2 when the third insulating layer 43 is viewed from the end of the terminals 71 to 74 of the IC chip 7 arranged on the ground side along the line III-III shown in FIG. 14. . FIG. 15 is a wiring structure diagram when the third wiring layer 33 is viewed in plan from the ground side along the IV-IV line shown in FIG. 14. FIG. 15 is a wiring structure diagram when the fourth wiring layer is viewed from the ground side along the VV line shown in FIG. 14.

  Embodiments of the present invention will be described below with reference to the drawings. In the drawings, the same elements are denoted by the same reference numerals, and redundant description is omitted. Further, the positional relationship such as up, down, left and right is based on the positional relationship shown in the drawings unless otherwise specified. Furthermore, the dimensional ratios in the drawings are not limited to the illustrated ratios. Further, the following embodiments are exemplifications for explaining the present invention, and are not intended to limit the present invention only to the embodiments. Furthermore, the present invention can be variously modified without departing from the gist thereof.

  FIG. 1 is a cross-sectional view schematically showing the structure of a DCDC converter 1 (electronic component built-in module) which is a preferred embodiment of an electronic component built-in module according to the present invention, and FIG. 2 is an equivalent circuit of the DCDC converter 1. FIG.

  The DCDC converter 1 includes, for example, an inductor 8 (second electronic component: passive) connected to an electronic component built-in substrate 2 (substrate) and bonding regions (electrode pads) 61 and 62 of the electronic component built-in substrate 2 via a bonding portion 81. The electronic component built-in substrate 2 contains, for example, an IC chip 7 (first electronic component: active component). In addition to the inductor 8, a passive component such as a capacitor (capacitor) may be further placed on the electronic component built-in substrate 2. In FIG. 1, among the passive components constituting the DCDC converter 1, The state where only the inductor 8 is mounted on the electronic component built-in substrate 2 is shown.

As shown in the equivalent circuit diagram of FIG. 2, the IC chip 7 includes a control circuit C that performs switching control on the input voltage V _IN and outputs a desired output voltage V _OUT , and a switch circuit that performs the actual switching operation. It consists of S1 and S2. In the equivalent circuit diagram of FIG. 2, passive components of capacitors (capacitors) C1 and C2 are further placed on the electronic component built-in substrate 2 shown in FIG. 1 in addition to the inductor 8 (denoted as L in FIG. 2). It shows the state being done.

  In the DCDC converter 1, the first insulating layer 41, the second insulating layer 42, the third insulating layer 43, the fourth insulating layer 44, and the fifth insulating layer 45, the first wiring layer 31, and the second wiring from the bottom layer. The layer 32, the third wiring layer 33, and the fourth wiring layer 34 are sequentially stacked, and the IC chip 7 is embedded at a predetermined position inside the third insulating layer 43. The first insulating layer 41, which is the lowest layer, is formed with at least three various output terminals 21 to 23 (for example, BGA: Ball Grid Array, so-called user terminals) for electrical connection with external elements. The input voltage terminal 21 applies a voltage to the DCDC converter 1, the output voltage terminal 22 outputs an arbitrary voltage from the DCDC converter 1, and the ground (GND) terminal grounded to a ground potential (ground; for example, 0V voltage). 23.

  FIG. 1 shows a state in which the output voltage terminal 22 is visually recognized on the back side of the drawing from the cross section on the input voltage terminal 21 and ground terminal 23 side.

  The IC chip 7 of this embodiment is also provided with output terminals on the lowermost layer side (internal electrodes, bumps, lands, etc.) in order to be electrically connected to the first wiring layer 31 to the fourth wiring layer 34. These output terminals are at least three output terminals connected to at least three various output terminals 21 to 23 formed on the bottom layer of the electronic component built-in substrate 2 of the DCDC converter 1, that is, the input voltage terminal 71 ( In addition to an input voltage terminal), a switch (SW) terminal 72 (switching terminal) that controls switching with respect to the input voltage, and a ground (GND) terminal 73 (ground terminal), an inductor 8 and a capacitor C2 ( (See FIG. 2: As mentioned above, not shown in FIG. 1) The smoothed output voltage is monitored and the output voltage is controlled to be within a preset reference voltage. And a fed back (FB) terminal 74 (terminal for feedback).

  Thus, the IC chip 7 is installed in a so-called face-down manner in which those terminals 71 to 74 are arranged toward the lowermost layer side of the electronic component built-in substrate 2. The input voltage terminal 71 and the switch terminal 72, and the ground terminal 73 and the feedback terminal 74 are provided so as to overlap each other in the depth direction of the paper surface in the viewing direction of FIG. In the figure, only the input voltage terminal 71 and the ground terminal 73 are shown.

  Further, the output terminal of the electronic component built-in substrate 2 corresponding to the feedback terminal 74 of the IC chip 7 is not formed. This is because the feedback terminal 74 of the IC chip 7 is for monitoring the output voltage after smoothing, so that the function is fulfilled if it is connected to the output voltage terminal 22 of the electronic component built-in substrate 2. .

  As described above, FIG. 1 shows a cross-sectional view when the IC chip 7 is broken at substantially the center and is viewed in plan from one side of the IC chip 7, and is an output terminal on one side of the IC chip 7. A configuration is shown in which the wiring terminals of the voltage terminal 71 and the ground terminal 73 are electrically connected to the input voltage terminal 21 and the ground terminal 23 on one side of the electronic component built-in substrate 2 respectively. Thus, the correspondence between the various output terminals 21 to 23 for external output formed on the electronic component built-in substrate 2 and the various terminals 71 to 74 of the IC chip 7 is as described above.

  Further, the structure in which the various terminals 71 to 74 of the IC chip 7 are connected inside the electronic component built-in substrate 2 is as follows. In other words, the input voltage terminal 71 of the IC chip 7 is connected to the second wiring layer 32 via the via conductor 95, and further formed on the first wiring layer 31 and the electronic component built-in substrate 2 via the via conductor 92. Connected to the input voltage terminal 21. The input voltage terminal 71 of the IC chip 7 includes a via conductor 95, a via conductor 93 connected to the third wiring layer 33, a via conductor 94 connected to the fourth wiring layer 34, and an electrode pad 63 that is a bonding region. And is connected to the capacitor C1.

  The switch terminal 72 of the IC chip 7 is connected to the second wiring layer 32 through the via conductor 95, and further, the via conductor 93 connected to the third wiring layer 33 and the via conductor connected to the fourth wiring layer 34. 94 and the inductor 8 through the electrode pad 62 which is a bonding region.

  The ground terminal 73 of the IC chip 7 is connected to the second wiring layer 32 via the via conductor 95, and further, the ground terminal formed on the first wiring layer 31 and the electronic component built-in substrate 2 via the via conductor 92. 23. The ground terminal 73 of the IC chip 7 includes a via conductor 95, a via conductor 93 connected to the third wiring layer 33, a via conductor 94 connected to the fourth wiring layer 34, and an electrode pad 64, which is a bonding region. 66 to the capacitors C1 and C2.

  The feedback terminal 74 of the IC chip 7 is connected to the second wiring layer 32 via the via conductor 95, and is connected to the output voltage terminal 22 formed on the first wiring layer 31 and the electronic component built-in substrate 2 via the via conductor 92. Connected. The feedback terminal 74 of the IC chip 7 includes a via conductor 95, a via conductor 93 connected to the third wiring layer 33, a via conductor 94 connected to the fourth wiring layer 34, and an electrode pad 61 that is a bonding region. Via the via conductors 95, 93 and 94 and the electrode pad 65 which is a junction region.

  3 to 13 are process diagrams (process flow diagrams) showing an example of a procedure for manufacturing the semiconductor-embedded substrate 2 of the DCDC converter 1. FIG.

  First, a well-known technique such as drilling a double-sided copper-clad glass epoxy, which is a double-sided CCL (Copper Clad Laminate), performing electroless plating and electrolytic plating, and then removing unnecessary portions of the plating film by etching or the like. Then, the core substrate 3 on which the patterned third wiring layer 33 and fourth wiring layer 34 are formed is prepared (FIG. 3).

  Next, an insulating resin film is vacuum-pressed on the core substrate 3 to laminate an uncured third insulating layer 43 to form an RCC (Resin Coated Copper) structure (FIG. 4).

  Then, after the IC chip 7 is placed in a so-called face-up state on the uncured third insulating layer 43 (FIG. 5), it is again covered with an uncured resin, and the inside of the third insulating layer 43 Then, the IC chip 7 is embedded, and the third insulating layer 43 is cured. Next, after unnecessary portions of the second wiring layer 32 formed by overlapping the copper foil on the third insulating layer 43 are removed by etching or the like, via holes are formed in a place where the second wiring layer 32 is removed by a known method. 93H and 95H are formed, the third wiring layer 33 is exposed at the bottom of the via hole 93H, and the terminals 71 to 74 of the IC chip 7 (the input voltage terminal 71 and the ground are shown in the figure) at the bottom of the via hole 95H. (Only two terminals 73 are shown) are exposed (FIG. 6).

  Then, copper or the like is plated on the core substrate 3 in which the via holes 93H and 95H are formed, and the second wiring layer 32 and the third wiring layer 33, and the second wiring layer and the terminals 71 to 74 of the IC chip 7 are provided. Are connected by via conductors 93 and 95, respectively (FIG. 7).

  Next, the second wiring layer 32 is patterned by etching or the like to form a wiring pattern of the second wiring layer 32 (FIG. 8). Next, the second wiring layer 32 and the inside of the via holes 93H and 95H are filled with resin to form an uncured second insulating layer 42, and a copper foil or the like is further laminated thereon to form the first wiring layer 31. Then, the second insulating layer 42 is cured by pressing the entire substrate by hot pressing or the like, and at the same time, the first wiring layer 31 to the fourth wiring layer 34 and the second insulating layer 42 to be laminated are stacked. ˜Adhesion between the fourth insulating layer 44 and the IC chip 7 is improved (FIG. 9).

  Thereafter, unnecessary portions of the first wiring layer 31 and the fourth wiring layer 34 which are the outermost layers in that state are removed by etching or the like, and via holes 92H and 94H are formed, and at the bottoms thereof, respectively. The second wiring layer 32 and the third wiring layer 33 are exposed (FIG. 10).

  Next, copper plating is performed on the inside of the via holes 92H and 94H, and on the first wiring layer 31 and the fourth wiring layer 34, so that the first wiring layer 31, the second wiring layer 32, and the third wiring layer 33 are formed. The fourth wiring layer 34 is connected to the via conductors 92 and 94, respectively (FIG. 11). Next, the first wiring layer 31 and the fourth wiring layer 34 are patterned by etching or the like to form a wiring pattern (FIG. 12).

  Then, a solder resist is applied on the wiring patterns of the first wiring layer 31 and the fourth wiring layer 34 and on appropriate portions other than those wiring patterns, and the first insulating layer 41 and the fifth insulating layer 41 are mask layers. By forming the insulating layer 45, the electronic component built-in substrate 2 is obtained (FIG. 13). Then, in a state where the electronic component built-in substrate 2 is inverted and turned upside down, a passive component such as an inductor 8 and a capacitor is placed thereon and connected to complete the DCDC converter 1.

  The wiring structure when the electronic component built-in substrate 2 formed in this way is viewed in plan from the ground side (opposite side of the inductor 8) for each of the wiring layers 31 to 34 is specifically described with reference to FIGS. explain. First, FIG. 14 is a main part sectional view schematically showing the electronic component built-in substrate 2 of the present embodiment. 15 is a wiring structure diagram (II line sectional view) when the first wiring layer 31 is viewed from the ground side along the II line shown in FIG.

  In the first wiring layer 31, an input voltage wiring pattern 31Vi, a ground (grounding) wiring pattern 31G, and an output voltage wiring pattern 31Vo are formed. The first wiring layer 31 has an output terminal for electrical connection with an external element, and has an input voltage terminal 21, an output voltage terminal 22, and a ground terminal 23. Further, an input voltage via conductor 92Vi, an output voltage via conductor 92Vo, and a ground via conductor 92G are formed to connect to the second wiring layer 32 to be laminated. The ground wiring pattern 31G formed in the first wiring layer 31 integrally connects the two ground vias 92G and the ground terminal 23 formed in the electronic component built-in substrate 2. The various wiring patterns 31Vi, Vo, G connect the various output terminals 21 to 23 and the via conductors 92 corresponding to the various output terminals 21 to 23.

  FIG. 16 is a wiring structure diagram (II-II line cross-sectional view) when the second wiring layer 32 is viewed from the ground side along the line II-II shown in FIG. The second wiring layer 32 includes two input voltage wiring patterns 32Vi (driving signal lines), a ground wiring pattern 32G (driving signal lines), and a switching wiring pattern 32S (switching). Signal line), output voltage wiring pattern 32Vo (driving signal line), and feedback wiring pattern 32F (feedback signal line).

  The second wiring layer 32 is formed with an input voltage via conductor 92Vi, an output voltage via conductor 92Vo, and a ground via conductor 92G for connection to the first wiring layer 31 described above. In order to connect to the three wiring layers 33, two input voltage via conductors 92Vi, two output voltage via conductors 93Vo, two switching via conductors 93S, and two ground via conductors 93G are formed. The Various via conductors 95Vi, 95G, 95F, and 95S connected to the terminals 71 to 74 of the IC chip 7 are formed.

  Both ends of the input voltage wiring pattern 32Vi are connected to the input voltage via conductors 92Vi and 93Vi or the input voltage via conductors 93Vi and the via conductor 95Vi connected to the input voltage terminal 71 of the IC chip 7 to output voltage. Both ends of the wiring pattern 32V0 are connected to output voltage via conductors 92Vo and 93Vo. The switching wiring pattern 32S is integrally connected with a via conductor 95S connected to the switch terminal 72 of the IC chip 7 and a switching via conductor 93S. The ground wiring pattern 32G is integrally connected to the via conductor 95G connected to the ground terminal 73 of the IC chip 7 and the ground via conductors 92G and 93G.

  Here, the feedback wiring pattern 32F is connected to the feedback terminal 74, the via conductor 95F, and the output voltage via conductors 92Vo, 93Vo, and 93Vo.

  The feedback wiring pattern 32F is formed so as to have a portion not parallel to any of the wiring patterns 32Vi and 32Vi for the input voltage and the wiring pattern 32S for switching, and preferably for the input voltage. The wiring patterns 32Vi and 32Vi and the switching wiring pattern 32S are formed so as to cross (longitudinal) the extending direction. More specifically, the feedback wiring pattern 32F is formed between the input voltage wiring patterns 32Vi and 32Vi and the switching wiring pattern 32S in the surface direction of the substrate 2, and the input voltage The wiring patterns 32Vi and 32Vi for switching and the wiring pattern 32S for switching extend away from each other.

  In the present embodiment (FIG. 16), a part of the feedback wiring pattern 32F crosses between the terminals 71 and 73 and the terminals 72 and 74 along the long side of the IC chip 7 and is input. The voltage wiring patterns 32Vi and 32Vi and the switching wiring pattern 32S are formed so as to cross the extending direction. In other words, a part of the feedback wiring pattern 32F is formed so as to pass through substantially the center of the IC chip 7, and is substantially orthogonal to the input voltage wiring patterns 32Vi and 32Vi and the switching wiring pattern 32S. It is provided so that it may extend.

  In general, since the input voltage signal is directly transmitted to the input voltage wiring patterns 32Vi and 32Vi and the switching signal is directly transmitted to the switching wiring pattern 32S, both the wiring patterns 32Vi, 32Vi, and 32S are transmitted to the wiring patterns 32Vi, 32Vi, and 32S. , Noise (high frequency component and / or harmonic component) is likely to be carried (easy to be included). However, in this way, in the surface direction of the electronic component built-in substrate 2, each of the input voltage wiring pattern 32Vi and the switching wiring pattern 32S is formed on the left and right with the feedback wiring pattern 32F as the center. Further, by forming the feedback wiring pattern 32F so as to extend away from the input voltage wiring pattern 32Vi and the switching wiring pattern 32S, the wiring patterns 32F, 32Vi, and 32S are formed. As a result, the formation of significant capacitive coupling between various signal lines is prevented, or the magnitude of capacitive coupling is effectively reduced. As a result, it is possible to suppress or block noise from being superimposed on the wiring pattern 32F, which is a feedback signal line, and further stabilize the noise.

  Further, at least a part of the feedback wiring pattern 32F is located on the inner side of the outer periphery (outer frame) of the mounting area (mounting area) A7 of the IC chip 7 in a state where the electronic component built-in substrate 2 is viewed in plan view. It is formed. In other words, at least a part of the feedback wiring pattern 32F is under the placement of the IC chip 7 and in a state where the electronic component built-in substrate 2 is viewed in plan (in the plane direction of the electronic component built-in substrate 2). It is formed so as to overlap with the chip 7.

  Further, since the feedback wiring pattern 32F is formed so as to be substantially orthogonal to the leakage magnetic flux generated from the inductor 8, the electronic component built-in board 2 has the leakage magnetic flux generated from the inductor 8 with respect to the feedback wiring pattern 32F. Can be made the least affected. In particular, when the feedback wiring pattern 32F extends in the same direction as the direction connecting the terminals of the inductor 8, and the internal structure of the inductor 8 is a solenoid coil having a winding direction above the electronic component built-in substrate 2. Is a technology that works more effectively.

  Also, a ground wiring pattern 32G is preferably formed near the feedback wiring pattern 32F so as to surround at least a part of the feedback wiring pattern 32F. The ground wiring patterns 32G are ground via conductors 93G and 93G formed at both end portions of the substrate 2 and at the side end portions of the IC chip 7, and via conductors 95G connected to the ground terminals 73 of the IC chip 7. , And a ground layer (second ground layer) in which the via conductors 92G and 92G for ground are integrally formed. In the present embodiment (FIG. 16), the ground wiring pattern 32G is formed not only around the feedback wiring pattern 32F but also around the switching wiring pattern 32S.

  By forming the ground layer in the second wiring layer 32 in this way, the second wiring layer 32 is directly connected to a predetermined ground potential (ground). Therefore, from the second wiring layer 32 to the predetermined ground potential. The shortest path is formed. Thereby, the impedance value in the ground path can be reduced. In addition, since such a ground layer is formed around the feedback wiring pattern 32F, the feedback signal passing through the wiring pattern 32F, which is the feedback signal line, becomes more stable, and the operation of the power supply circuit is improved. It can be further stabilized. Furthermore, in the control circuit C, since switching is controlled at a high frequency, noise is particularly likely to occur at the time of steep rise and fall of a signal. However, by providing such a ground layer, Generation of noise that is likely to occur at timing can also be prevented.

  The feedback wiring pattern 32F is formed in the second wiring layer 32 spaced from the inductor 8, and is not only disposed farther from the inductor 8, but also in the second wiring layer 32. The wiring pattern 32F is formed in the placement area of the IC chip 7 and is disposed under the placement of the IC chip 7 so that the IC chip 7 shields a leakage magnetic flux generated from the inductor 8 (shield). Therefore, it is possible to suppress or block noise from being superimposed on the wiring pattern 32F, which is a feedback signal line that is easily affected by the leakage magnetic flux of the inductor 8, and stabilize the noise.

  Since the feedback wiring pattern 32F is a wiring formed only for monitoring the output voltage after smoothing, it may be a thin wiring pattern that allows current to flow slightly. Further, in the feedback wiring pattern 32F formed in this way, a current flows from the output voltage via conductors 92Vo, 93Vo, 93Vo at one end to the feedback terminal 74 at the other end, and this current is The inductor 8 flows in the direction opposite to the direction of the current flowing on the substrate. As a result, a magnetic field (demagnetizing field) in a direction opposite to the magnetic field generated from the inductor 8 is generated in the feedback wiring pattern 32F, so that the leakage magnetic flux generated from the inductor 8 can be reduced to some extent.

  17 shows the electronic component built-in substrate 2 when the third insulating layer 43 is viewed in plan view from the end of each terminal 71 to 74 of the IC chip 7 arranged on the ground side along the line III-III shown in FIG. It is a structure figure (III-III sectional view taken on the line). Inside the third insulating layer 43, the IC chip 7 is embedded, and various via conductors 93 for connecting to the terminals 71 to 74 of the IC chip 7 and the third wiring layer 33 are formed. These various via conductors 93 are formed at one end of the IC chip 7 and are provided almost directly above the via conductors 93 formed in the second wiring layer 32. The IC chip 7 is placed inside the third insulating layer 43 so that the terminals 71 to 74 are arranged on the side farther from the inductor 8 side (ground side).

  18 is a wiring structure diagram (IV-IV line cross-sectional view) when the third wiring layer 33 is viewed from the ground side along the line IV-IV shown in FIG. In the third wiring layer 33, a wiring pattern 33Vi for input voltage, a wiring pattern 33G for ground, a wiring pattern 33S for switching, and a wiring pattern 33Vo for output voltage are formed.

  The ground wiring pattern 33G is a ground layer (first ground layer) formed outside the placement area A7 of the IC chip 7 placed under the third wiring layer 33. The wiring pattern 33Vi for the input voltage, the wiring pattern 33S for switching, and the wiring pattern 33Vo for the output voltage are formed so as to cover substantially the entire mounting region (mounting region) of the inductor 8.

  As described above, in addition to the ground layer formed on the second wiring layer 32, the third wiring layer 33 between the inductor 8 and the IC chip 7 covers a wide range of ground so as to cover the IC chip 7. By forming the layer, it is possible to prevent the occurrence of noise that is likely to occur during switching control in the control circuit C. As a result, the mutual interference of various signal lines formed in the second wiring layer 32 is reduced. Can be prevented. In addition, the influence of electromagnetic noise caused by the leakage magnetic flux generated from the surface of the inductor 8 can be greatly suppressed or blocked.

  The ground layer formed in the third wiring layer 33 is preferably formed between the input voltage wiring pattern 33Vi and the output voltage wiring pattern 33Vo. By forming in this way, mutual interference between the input-side signal line and the output-side signal line formed in the third wiring layer 33 can be prevented, and not only the operation of the control circuit C but also the power The operation of the entire circuit can be further stabilized.

  In addition, by providing four input voltage via conductors 93Vi, 93Vi, 94Vi, and 94Vi, and connecting the input voltage wiring pattern 33Vi integrally with the plurality of via conductors, the wiring impedance generated on the input side can be further increased. Can be reduced.

  FIG. 19 is a wiring structure diagram (sectional view taken along the line VV) when the fourth wiring layer 34 is viewed from the ground side along the line VV shown in FIG. 14. The fourth wiring layer 34 includes an input voltage wiring pattern 34Vi, a ground wiring pattern 34G, a switching wiring pattern 34S, and an output voltage wiring pattern 34Vo. The wiring patterns 34Vi, 34G, and 34S, respectively. , 34V are connected to the input voltage via conductor 94Vi, the ground via conductor 94G, the switch via conductor 94S, and the output voltage via conductor 94Vo, respectively.

  And electrode pads 61-66 are installed on each wiring pattern 34Vi, 34G, 34S, and 34Vo. Each of the electrode pads 61 to 66 is disposed in the region of the respective wiring pattern 34Vi, 34G, 34S, 34Vo and outside the end of the region where the inductor 8 or the capacitors C1, C2 are placed. Is formed. The inductor 8 is placed on the electrode pads 61 and 62, the input-side capacitor C1 is placed on the electrode pads 63 and 64, and the output-side capacitor C2 is placed on the electrode pads 65 and 66. Thus, the DCDC converter 1 on which the inductor 8 and the capacitors C1 and C2 are mounted can be obtained.

  As described above, according to the present embodiment, the input voltage wiring pattern 32Vi and the switching wiring pattern 32S are formed on the left and right with the feedback wiring pattern 32F as the center in the surface direction of the electronic component built-in substrate 2. In addition, since the feedback wiring pattern 32F is formed to extend away from the input voltage wiring pattern 32Vi and the switching wiring pattern 32S, the wiring patterns 32F, 32Vi, Capacitive coupling can be prevented from occurring between the 32Ss, or even if such capacitive coupling occurs, the capacity can be reduced or reduced. Therefore, it is possible to effectively prevent noise from entering or entering the feedback wiring pattern 32F via capacitive coupling from the input voltage wiring pattern 32Vi and / or the switching wiring pattern 32S. Therefore, it is possible to perform signal transmission with high reliability, that is, high purity.

  Further, since the ground wiring pattern 32G is formed around the feedback wiring pattern 32F, it is possible to effectively prevent the fluctuation of the feedback signal passing through the feedback wiring pattern 32F. As described above, the noise suppression effect is enhanced and the feedback signal line can be stabilized, so that the operation of the power supply circuit can be more reliably stabilized.

  Furthermore, since a wide ground layer is formed on the third wiring layer 33 between the inductor 8 and the IC chip 7 so as to cover the IC chip 7, it is likely to occur during switching control in the control circuit C. Generation of noise can be effectively prevented, and as a result, mutual interference of various signal lines formed in the second wiring layer 32 can be prevented.

  As described above, the present invention is not limited to each of the above-described embodiments, and various modifications can be made as described above as long as the gist of the present invention is not changed. For example, in this embodiment, the input voltage wiring patterns 32Vi and 32Vi and the switching wiring pattern 32S are formed in the same layer as the layer (second wiring layer 32) where the feedback wiring pattern 32F is formed. However, in a state where the electronic component built-in substrate 2 is viewed in plan, the feedback wiring pattern 32F is formed to extend in a direction away from each of the input voltage wiring pattern 32Vi and the switching wiring pattern 32S. In this case, the input voltage wiring patterns 32Vi and 32Vi and the switching wiring pattern 32S are not necessarily formed in the same layer as the layer where the feedback wiring pattern 32F is formed.

  As described above, the electronic component built-in module according to the present invention can ensure the stable operation of the first electronic component such as an IC chip disposed in the vicinity of the second electronic component such as the inductor, thereby reliably preventing the malfunction. In addition to preventing deterioration of the purity of the feedback signal, in particular, it is possible to perform signal transmission with excellent reliability, so that devices, devices, systems, various devices, etc. with built-in electronic components, In particular, it can be widely and effectively used for those requiring miniaturization and high performance, as well as production and production thereof.

DESCRIPTION OF SYMBOLS 1 ... DCDC converter (electronic component built-in module), 2 ... Electronic component built-in board, 3 ... Core board | substrate, C ... Control circuit, S1, S2 ... Switch circuit, 7 ... IC chip (1st electronic component), A7 ... IC chip Placement area (mounting area), 8, L ... inductor (second electronic component), C1, C2 ... capacitor (capacitor), 21 ... input voltage terminal of electronic component built-in substrate, 22 ... output voltage of electronic component built-in substrate Terminals 23... Ground output terminals of the electronic component built-in substrate, 31 to 34... Wiring layer, 32 F... Feedback wiring pattern (feedback signal line), 32 Vi... Input voltage wiring pattern (drive signal line) , 32Vo ... Output voltage wiring pattern, 32S ... Switching wiring pattern (switching signal line), 32G ... Ground Wiring pattern (signal line for driving), 41 to 45 ... insulating layer, 61 to 66 ... electrode pad, 71 ... input voltage terminal, 72 ... switch output terminal, 73 ... ground terminal, 74 ... feedback terminal, 81 ... junction , 92 to 95: Via conductor, 92H to 95H: Via hole, V _IN ... input voltage, V _OUT ... output voltage.

Claims (8)

An electronic component built-in module comprising: a substrate in which a first electronic component is embedded; and a second electronic component placed on the substrate,
The board includes a feedback signal line for monitoring an output signal output from the electronic component built-in module via the second electronic component, and a switching signal line connected to the second electronic component. Is provided,
The feedback signal line and the switching signal line each have a portion extending in a direction away from each other in the surface direction of the substrate.
Electronic component built-in module. The board is provided with a signal line for input voltage input to the electronic component built-in module,
The feedback signal line and the input voltage signal line have portions extending in directions away from each other in the surface direction of the substrate.
The electronic component built-in module according to claim 1. The substrate is provided with a first ground layer connected to a predetermined ground potential between the feedback signal line and the second electronic component.
The electronic component built-in module according to claim 1 or 2. The first ground layer is formed so as to cover a mounting region of the first electronic component and have an area larger than the mounting region of the first electronic component in the surface direction of the substrate.
The electronic component built-in module according to claim 3. The substrate is provided with a second ground layer connected to a predetermined ground potential in the vicinity of the switching signal line.
The electronic component built-in module according to any one of claims 1 to 4. The second ground layer is provided in the same layer as the layer in which the switching signal line is formed.
The electronic component built-in module according to claim 5. The feedback signal line includes a portion extending to cross at least one of the switching signal line and the input voltage signal line in the plane direction of the substrate.
The electronic component built-in module according to claim 1. The first electronic component is disposed such that an output terminal of the first electronic component faces away from the second electronic component.
The electronic component built-in module according to claim 1.

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