JP5011338B2 - Wiring board with built-in capacitor - Google Patents

Description

  The present invention relates to a capacitor built-in wiring board in which a capacitor is housed in a housing hole opened in a core material.

  2. Description of the Related Art Conventionally, as a package structure for mounting a semiconductor element, a wiring board including a core material and a wiring stacked portion in which conductor layers and insulating layers are alternately stacked on top and bottom of the core material is widely known. This type of wiring board needs to be provided with a wiring structure for supplying power to the semiconductor chip from an external substrate. In order to stabilize and speed up the operation of the semiconductor chip, it is desirable to dispose the capacitor in the package and connect it to the power supply wiring to remove the noise of the power supply supplied to the semiconductor element. In this case, in the structure in which the capacitor is mounted on the semiconductor substrate, it is necessary to secure an arrangement region for that purpose, and the wiring distance between the capacitor and the semiconductor element becomes long, leading to an increase in wiring impedance. Therefore, in order to correct such a defect, a structure in which a capacitor is built in the wiring board has been proposed.

  On the other hand, in recent years, a structure for supplying a plurality of power supplies is widely adopted for semiconductor elements. For example, in the case of a processor chip, a configuration is known in which a first power supply is supplied to a processor core unit which is a main circuit, and a second power supply is supplied to peripheral I / O circuits and the like. In order to supply a plurality of different power supplies to a semiconductor element, it is possible to incorporate a plurality of capacitors corresponding to each semiconductor element in the wiring board as described above, but this leads to an increase in the size of the wiring board. That is undesirable. Therefore, a structure has been proposed in which one capacitor is divided into a plurality of regions, each region functions as a capacitor composed of a positive electrode and a negative electrode, and can be connected to a plurality of power supplies (see, for example, Patent Documents 1 and 2). .

JP 2007-96291 A JP 2008-270369 A

  In the package employing the above-described conventional structure, for example, when a capacitor divided into a plurality of regions corresponding to a plurality of power supplies is accommodated in a core material, via conductors are arranged in an array, and upper and lower terminal electrodes are arranged. It is necessary to connect to different power sources for each region. On the other hand, a predetermined conductor layer is formed on the upper portion of the wiring board so as to be opposed to the conductor layer on the upper surface of the capacitor at a short distance, and the conductor layer includes various conductor patterns. However, although the predetermined conductor layer usually includes conductor patterns for transmitting a plurality of power supplies, the arrangement of each conductor pattern does not always coincide with the capacitor area section below it. For example, a positional relationship in which the conductor pattern of the first power supply overlaps with the second power supply region of the capacitor in the stacking direction is directly below the portion where the conductor pattern of the first power supply is formed on the upper conductor layer. Originally, in order to avoid interference between different power sources, it is desirable not to make both conductor patterns close to each other, but in the conventional structure, different power sources are close to each other between a predetermined conductor layer and the upper surface of the capacitor. As a result, the crosstalk and the like may be generated, and the operation performance of the semiconductor element may be deteriorated.

  The present invention has been made to solve these problems. When a plurality of power supplies are supplied to a semiconductor element mounted on a wiring board with a built-in capacitor, the present invention is provided between a capacitor and a conductor layer facing the upper surface. An object of the present invention is to provide a wiring board with a built-in capacitor that can realize a high-speed and stable operation of a semiconductor element by sharing a region section corresponding to a plurality of power supplies and reducing crosstalk between different power supplies.

  In order to solve the above problems, a wiring board with a built-in capacitor according to the present invention includes a core material, a capacitor accommodated in the core material, and an insulating layer and a conductor layer alternately stacked on the upper surface side and the lower surface side of the core material. A stacked layer portion formed thereon, and configured to be capable of mounting a semiconductor element on top of the stacked portion, and a predetermined conductor layer adjacent to the capacitor in the stacked portion includes a first power supply wiring. A first conductive pattern and a second conductive pattern including a second power supply wiring are formed, and the capacitor includes a first region that forms a capacitance between the first positive electrode and the negative electrode, A second region that forms a capacitance between the positive electrode and the negative electrode of the first capacitor, and the first positive electrode terminal electrode is disposed on the surface of the capacitor on the predetermined conductor layer side. A first capacitor side conductor pattern including wiring connected to a power source; A second capacitor side conductor pattern including a wiring for connecting the second positive terminal electrode to the second power source is formed, and the first conductor pattern and the first capacitor side conductor pattern are The second conductor pattern and the second capacitor side conductor pattern have the same pattern shape and are directly opposed to each other in the stacking direction. It is configured.

  According to the wiring board of the present invention, when a plurality of different power supplies are supplied to a semiconductor element in a wiring board on which a semiconductor element is mounted and a capacitor is built in, the capacitor divided into regions according to the plurality of capacitors is located above the capacitor. Even if the arrangement is to face the conductor layers of the same, the conductor patterns of the same power supply are made to face each other in the stacking direction as the same pattern shape, while the arrangement in which the conductor patterns of different power supplies are directly facing each other in the stacking direction is avoided. it can. Therefore, it is possible to prevent occurrence of crosstalk when conductor patterns of different power sources face each other at a short distance, and it is possible to suppress power supply noise caused by crosstalk.

  As the capacitor of the present invention, a multilayer ceramic capacitor in which ceramic dielectric layers and internal electrode layers are alternately stacked and a plurality of via conductors connected to the internal electrode layers are arranged in an array can be employed. . In this case, the plurality of first positive electrode via conductors and the plurality of negative electrode via conductors are arranged in an array in the first region of the capacitor, and the second region of the capacitor includes the A plurality of via conductors for the second positive electrode and a plurality of via conductors for the negative electrode may be arranged in an array.

  On the surface of the capacitor according to the present invention, the first capacitor side conductor pattern may be formed in a central portion, and the second capacitor side conductor pattern may be formed in a peripheral portion. In this case, the first capacitor-side conductor pattern may form a protruding portion that protrudes from the central portion to a part of the peripheral portion and extends to the outer edge of the capacitor.

  In the present invention, the first power source may be a main power source supplied to the main circuit of the semiconductor element, and the second power source may be an I / O circuit power source supplied to the I / O circuit of the semiconductor element. Good.

  In order to solve the above problems, a wiring board with a built-in capacitor according to the present invention includes a core material, a capacitor accommodated in the core material, and an insulating layer and a conductor layer alternately on the upper surface side and the lower surface side of the core material. And a laminated portion formed on the laminated portion so that a semiconductor element can be placed on the laminated portion, and a predetermined conductor layer of the laminated portion includes N wirings of different power sources. Conductor patterns are formed, and the capacitor has N regions each forming a capacitance between each of the N positive electrodes and the negative electrode, and the N positive electrodes are disposed on the upper surface of the capacitor. N capacitor-side conductor patterns including wirings connecting the respective terminal electrodes to each of the N power sources are formed, and each of the N conductor patterns and the corresponding N capacitor side Each of the conductor patterns Identical to a by stacking direction pattern shape is configured so as to face directly.

  According to the present invention, in a wiring board with a built-in capacitor on which semiconductor elements that need to supply a plurality of different power supplies are placed, when suppressing power supply noise caused by crosstalk of each power supply, It is possible to realize an arrangement in which the region sections are shared with the conductor layers, the conductor patterns of the same power source are opposed to each other in the stacking direction, and the conductor patterns of different power sources are not directly opposed to each other. Thereby, it is possible to realize a wiring board with a built-in capacitor that can sufficiently reduce the above-described crosstalk and suppress noise caused by the crosstalk and realize high-speed and stable operation of the semiconductor element.

1 is a diagram showing a schematic cross-sectional structure of a wiring board 10 of the present embodiment. It is sectional drawing of the capacitor 70 of FIG. It is a top view of the capacitor 70 of FIG. 3 is a diagram showing a partially enlarged configuration of a conductor pattern in a region R1 of a conductor layer 71 of a capacitor 70. FIG. It is a figure which shows the area | region division of the range which opposes the capacitor 70 in the lamination direction among the conductor layers 21 of FIG. This is a first modification of the region division of the conductor layer 71 and the capacitor 70. It is the 2nd modification of the area | region division of the conductor layer 71 and the capacitor 70. FIG. It is the 3rd modification of the area | region division of the conductor layer 71 and the capacitor 70. FIG.

  Hereinafter, a preferred embodiment of a wiring board to which the present invention is applied will be described with reference to the drawings.

  FIG. 1 is a diagram showing a schematic cross-sectional structure of the wiring board of the present embodiment. The wiring board 10 shown in FIG. 1 has a structure including a core material 11, a first wiring laminated portion 20 on the upper surface side of the core material 11, and a second wiring laminated portion 30 on the lower surface side of the core material 11. Yes. In the wiring substrate 10 of the present embodiment, a semiconductor chip 60 as a semiconductor element is placed on an upper portion, and a capacitor 70 is incorporated below the semiconductor chip 60.

  The core material 11 is made of, for example, an epoxy resin containing glass fiber. A resin insulation layer 12 is laminated on the upper surface of the core material 11, and a resin insulation layer 13 is laminated on the lower surface of the core material 11. The core material 11 is formed with a housing hole 11a penetrating the center in a rectangular shape, and the capacitor 70 is housed in the housing hole 11a. A resin filler 50 is filled in a gap between the accommodation hole 11 a and the side surface of the capacitor 70. In this embodiment, the capacitor 70 is divided into two regions in the planar direction and functions as two independent capacitors connected to two power supply systems. The detailed structure of the capacitor 70 will be described later. As the resin filler 50, for example, a thermosetting resin made of a polymer material is used. The resin filler 50 has a role of fixing the capacitor 70 and acts so that the resin filler 50 absorbs deformation of the capacitor 70 and the core material 11.

  The core material 11 is formed with a plurality of through-hole conductors 42 penetrating predetermined portions in the stacking direction. The inside of the through-hole conductor 42 is filled with a closing body 43 made of, for example, glass epoxy. The through-hole conductor 42 and the closing body 43 extend vertically, penetrate through the upper and lower resin insulation layers 12 and 13 of the core material 11, and connect and conduct the upper conductor layer 21 and the lower conductor layer 31 in the stacking direction. Yes. The upper resin insulation layer 12 is formed with a plurality of via conductors 14 that connect and connect the conductor layer 71 formed on the upper surface of the capacitor 70 and the conductor layer 21 formed on the upper surface of the resin insulation layer 12 in the stacking direction. ing. The lower resin insulation layer 13 includes a plurality of via conductors 15 that connect and conduct the conductor layer 72 formed on the lower surface of the capacitor 70 and the conductor layer 31 formed on the lower surface of the resin insulation layer 13 in the stacking direction. Is formed.

  1 illustrates the case where the positions of the upper surface and the lower surface of the capacitor 70 coincide with the positions of the upper surface and the lower surface of the core material 11, but the positions of the upper surface and the lower surface of the capacitor 70 do not coincide with each other. However, the present invention can be applied. That is, the capacitor 70 may be thicker than the core material 11 and may protrude from the housing hole 11a, or the capacitor 70 may be thin and accommodated in a concave shape. The structure of the conductor layers 71 and 72 on the upper and lower surfaces of the capacitor 70 will be described later.

  The first wiring laminated portion 20 includes a conductor layer 21 formed on the upper surface of the resin insulating layer 12, a resin insulating layer 22 formed on the upper surface of the resin insulating layer 12 with the conductor layer 21 interposed therebetween, and a resin insulating layer 22 And a solder resist layer 24 covering the upper surface of the resin insulating layer 22. A plurality of via conductors 25 are provided at predetermined positions of the resin insulating layer 22 to connect the conductive layer 21 and the terminal pads 23 in the stacking direction. The solder resist layer 24 is opened at a plurality of locations to expose a plurality of terminal pads 23, and a plurality of solder bumps 40 are formed there. Each solder bump 40 is connected to each pad 61 of the semiconductor chip 60 placed on the wiring substrate 10.

  The second wiring laminated portion 30 includes a conductor layer 31 formed on the lower surface of the resin insulating layer 13, a resin insulating layer 32 stacked on the lower surface of the resin insulating layer 13 with the conductor layer 31 interposed therebetween, and a resin insulating layer 32. And a solder resist layer 34 covering the lower surface of the resin insulating layer 32. A plurality of via conductors 35 are provided at predetermined positions of the resin insulating layer 32 to connect and connect the conductor layer 31 and the BGA pad 33 in the stacking direction. The solder resist layer 34 is opened at a plurality of locations to expose a plurality of BGA pads 33 to which a plurality of solder balls 41 are connected. When the wiring board 10 is used as a BGA package, an external base material (not shown) and each part of the wiring board 10 can be electrically connected via a plurality of solder balls 41.

  Next, the structure of the capacitor 70 of FIG. 1 will be described with reference to FIGS. FIG. 2 is a sectional view of the capacitor 70, and FIG. 3 is a top view of the capacitor 70, respectively. The capacitor 70 of the present embodiment is a so-called via array type capacitor, and has a structure in which a plurality of ceramic dielectric layers 73 are laminated using a ceramic sintered body made of a high dielectric constant ceramic such as barium titanate. Have. As shown in FIG. 2, the capacitor 70 is divided into a central region R1 (first region) and a peripheral region R2 (second region) in the planar direction. In the region R1, a first capacitor is formed between the first positive electrode and the negative electrode, and in the region R2, a second capacitor is formed between the second positive electrode and the negative electrode. In the present embodiment, a first capacitor formed in the region R1 is connected between a power supply voltage VDD1 (first power supply) and a ground (negative electrode), which will be described later, and a second capacitor formed in the region R2 is connected. It is assumed that a connection is made between a power supply voltage VDD2 (second power supply) described later and the ground.

  In the region R1, the internal electrode layers 101 and the internal electrode layers 102 are alternately arranged between the ceramic dielectric layers 73. One internal electrode layer 101 functions as a first positive electrode, the other internal electrode layer 102 functions as a negative electrode, and both electrodes face each other with each ceramic dielectric layer 73 interposed therebetween. A capacity of 1 is formed. In the region R2, the internal electrode layers 201 and the internal electrode layers 202 are alternately arranged between the ceramic dielectric layers 73. One internal electrode layer 201 functions as an electrode for the second positive electrode, the other internal electrode layer 202 functions as an electrode for the negative electrode, and both electrodes face each other with each ceramic dielectric layer 73 interposed therebetween. Two capacitors are formed. In order to secure a certain distance between the first capacitor and the second capacitor to suppress interference, a boundary portion having a predetermined width is provided between the regions R1 and R2 of the capacitor 70.

  The capacitor 70 is formed with a plurality of via conductors 111, 112, 211, 212 in which nickel or the like is embedded in a large number of via holes penetrating all the ceramic dielectric layers 73 in the stacking direction. In the region R1, each via conductor 111 is connected to the internal electrode layer 101, each via conductor 112 is connected to the internal electrode layer 102, and one via conductor 111 and the other via conductor 112 are alternately arranged. Yes. In the region R2, each via conductor 211 is connected to the internal electrode layer 201, each via conductor 212 is connected to the internal electrode layer 202, and one via conductor 211 and the other via conductor 212 are alternately arranged. Yes.

  Each of the plurality of via conductors 111, 112, 211, 212 described above has an upper end connected to the terminal electrodes 121, 122, 221, 222 and a lower end connected to the terminal electrodes 131, 132, 231, 232. . That is, in the region R1, one via conductor 111 connects and conducts the upper terminal electrode 121 and the lower terminal electrode 131, and the other via conductor 112 connects and conducts the upper terminal electrode 122 and the lower terminal electrode 132. Yes. In the region R2, one via conductor 211 connects and connects the upper terminal electrode 221 and the lower terminal electrode 231, and the other via conductor 212 connects and connects the upper terminal electrode 222 and the lower terminal electrode 232. Yes.

  Here, referring to FIG. 3, the central region R1 is accompanied by two projecting portions R1a partially projecting into the peripheral region R2. That is, in the plane of the capacitor 70, the region R1 is in contact with the outer edge of the capacitor 70 through the two protrusions R1a in FIG. 3, and the region R2 has two regions on the left and right sides in FIG. Includes a symmetric region. These protrusions R1a are provided to take out electrodes to the outside when electrolytic plating is performed on the region R1 of the conductor layer 71 when the capacitor 70 is manufactured. As shown in FIG. 3, since the projecting portions R1a are provided in the two directions of the conductor layer 71, a large number of capacitors 70 can be arranged in the panel to be efficiently electroplated.

  In the conductor layer 71 of the capacitor 70, the first positive terminal electrode 121 and the negative terminal electrode 122 are alternately arranged in the region R1, and the second positive terminal electrode 221 and the region R2. Negative terminal electrodes 222 are alternately arranged. Although omitted in FIG. 3, the via conductors 111 and 112 and the terminal electrodes 131 and 132 are disposed below the terminal electrodes 121 and 122 in the region R1, and are disposed below the terminal electrodes 221 and 222 in the region R2. The via conductors 211 and 212 and the terminal electrodes 231 and 232 are arranged to overlap each other. In addition, arrangement | positioning in FIG. 3 is an example, Comprising: The shape and space | interval of each terminal electrode 121,122,221,222 can be set suitably.

  For the sake of simplicity, FIG. 3 shows a state in which a large number of terminal electrodes 121, 122, 221, and 222 having the same shape are regularly arranged, but in reality, each terminal electrode 121 is provided in the region R1. A conductor pattern connected to the power supply voltage VDD1 is formed, and a conductor pattern connecting each terminal electrode 221 to the power supply voltage VDD2 is formed in the region R2. 4 is a partially enlarged view showing the configuration of the conductor pattern in the region R1 of the conductor layer 71. As shown in FIG. As shown in FIG. 4, in the region R1, the conductor pattern P1 for the power supply voltage VDD1 is formed so as to integrally connect the terminal electrodes 121 for the first positive electrode. On the other hand, the conductor pattern P1 is not formed on the outer peripheral portion of each terminal electrode 122 for negative electrode, and each terminal electrode 122 and the conductor pattern P1 are electrically disconnected. In the case of the region R2, if the terminal electrodes 121 and 122 in FIG.

  Next, the configuration of the upper conductor layer 21 facing the capacitor 70 will be described with reference to FIG. FIG. 5 shows a region section of the conductor layer 21 in a range facing the capacitor 70 in the stacking direction. As shown in FIG. 5, the conductor layer 21 is divided into a central region R11 and a peripheral region R12. As is clear from comparison between FIG. 3 and FIG. 5, the region section of the conductor layer 21 matches the region section of the capacitor 70, and the region R <b> 11 of the conductor layer 21 has the same pattern shape as the region R <b> 1 of the capacitor 70. The region R12 of the conductor layer 21 has the same pattern shape as that of the region R2 of the capacitor 70, and is opposed to each other in the stacking direction. Similarly to the protrusion R1a of the region R1 of the capacitor 70, the region R11 is accompanied by two protrusions R11a protruding to the region R12 and in contact with the outer edge.

  In the conductor layer 21, a conductor pattern serving as a wiring for one power supply voltage VDD1 is formed in the region R11, and a conductor pattern serving as a wiring for the other power supply voltage VDD2 is formed in the region R12. The regions R11 and R12 may partially include other conductor patterns, but the conductor pattern of the power supply voltage VDD1 occupies most of the area of the region R11, and the conductor pattern of the power supply voltage VDD2 is included in the regions R11 and R12. It is desirable to occupy most of the area of the region R12. Thus, between the capacitor 70 and the conductor layer 21, the conductor pattern of the power supply voltage VDD1 is opposed in the stacking direction by the region R1 and the region R11, and the conductor pattern of the power supply voltage VDD2 is stacked in the stacking direction by the region R2 and the region R12. There is an opposing relationship.

  With the structure of the present embodiment described above, the capacitor 70 and the conductor layer 21 are configured in the same region section, and it is possible to avoid an arrangement in which conductor patterns of different power supply voltages VDD1 and VDD2 are directly opposed in the stacking direction at a short distance. . If conductor patterns of different power supply voltages VDD1 and VDD2 are arranged to face each other in the short distance stacking direction, crosstalk between the two increases. On the other hand, in the structure of the present embodiment, crosstalk between different power supply voltages VDD1 and VDD2 can be sufficiently reduced, and power supply noise caused by crosstalk can be suppressed. In the semiconductor chip 60, for example, the power supply voltage VDD1 is used as a main power supply supplied to the processor core unit, and the power supply voltage VDD2 is used as a power supply supplied to peripheral I / O circuits. In general, when interference occurs between the processor unit and the peripheral I / O circuit, there is a risk of malfunction in the operation of the semiconductor chip 60. By adopting the structure of this embodiment and suppressing noise, the semiconductor High speed and stable operation can be realized in the chip 60.

  The contents of the present invention have been specifically described above based on the present embodiment, but the present invention is not limited to the above-described embodiment, and various modifications can be made without departing from the scope of the present invention. In particular, there are various modified examples of the region division of the capacitor 70 and the region division of the conductor layer 21 facing the capacitor 70. In the following, FIGS. 6 to 8 show modified examples related to the region section of the conductor layer 21 corresponding to FIG. 5 and the region section of the capacitor 70 overlapping therewith. 6 to 8 are diagrams on the assumption that the conductor layer 21 and the capacitor 70 have the same area section.

  In the modified example of FIG. 6, the region division in the case where the protrusions R1a and R11a associated with the regions R1 and R11 are not provided is shown. That is, rectangular regions R1 and R11 are provided in the center, and peripheral regions R2 and R12 surrounding the periphery are provided. In FIG. 6, the central regions R <b> 1 and R <b> 11 are arranged in an island shape. However, when there is no particular limitation on the manufacturing of the capacitor 70, the structure of the modified example of FIG.

  In the modification of FIG. 7, region divisions in the case where the regions R1 and R11 and the regions R2 and R12 are arranged on both sides in the plane direction are shown. That is, regions R1 and R11 are provided in the right half of FIG. 7, and regions R2 and R12 are provided in the left half of FIG. For example, in the wiring substrate 10 on which the two semiconductor chips 60 are placed, one semiconductor chip 60 is disposed above the right half of FIG. 7, and the other semiconductor chip 60 is disposed above the left half of FIG. When both are used as separate power sources, the structure of the modified example of FIG. 7 can be employed.

  In the modified example of FIG. 8, region classification is shown in the case where three regions including regions R3 and R13 are arranged in addition to regions R1 and R11 and regions R2 and R12. That is, regions R1 and R11 are provided in the center of FIG. 8, regions R2 and R12 are provided on the left side of FIG. 8, regions R3 and R13 are newly provided on the right side of FIG. 8, and power supply voltages VDD1 and VDD2 are sequentially provided. , Connected to VDD3. For example, in the case where three semiconductor chips 60 of different power sources are mounted on the wiring board 10 and when three power sources are supplied for each region of one semiconductor chip 60, the structure of the modified example of FIG. be able to.

  In addition, even when the modification of FIG. 8 is further generalized and the conductor layer 21 and the capacitor 70 are divided into N regions, and different N power source conductor patterns are formed in each region, The present invention can be applied.

DESCRIPTION OF SYMBOLS 10 ... Wiring board 11 ... Core material 11a ... Accommodating hole part 21, 31 ... Conductor layer 12, 13, 22, 32 ... Resin insulating layer 14, 15, 25, 35 ... Via conductor 20 ... 1st wiring laminated part 23 ... Terminal Pads 24, 34 ... solder resist layer 30 ... second wiring laminated portion 33 ... BGA pad 40 ... solder bump 41 ... solder ball 42 ... through-hole conductor 43 ... occlusion body 50 ... resin filler 60 ... semiconductor chip 61 ... pad 70 ... Capacitors 71, 72 ... Conductor layer 73 ... Dielectric layers 101, 102, 201, 202 ... Internal electrode layers 111, 112, 211, 212 ... Via conductors 121, 122, 131, 132, 221, 222, 231, 232 ... Terminal electrode

Claims (7)

A core material; a capacitor accommodated in the core material; and a laminated portion in which an insulating layer and a conductor layer are alternately laminated on the upper surface side and the lower surface side of the core material. A wiring board that can be placed,
A first conductor pattern including a first power supply wiring and a second conductor pattern including a second power supply wiring are formed in a predetermined conductor layer adjacent to the capacitor in the stacked portion,
The capacitor has a first region that forms a capacitance between the first positive electrode and the negative electrode, and a second region that forms a capacitance between the second positive electrode and the negative electrode,
On the surface of the capacitor on the side of the predetermined conductor layer, a first capacitor side conductor pattern including a wiring connecting the first positive electrode terminal electrode to the first power source, and the second capacitor A second capacitor side conductor pattern including a wiring for connecting a positive electrode terminal electrode to the second power source is formed;
The first conductor pattern and the first capacitor side conductor pattern have the same pattern shape and are directly opposed in the stacking direction. The second conductor pattern and the second capacitor side conductor pattern are A wiring board with a built-in capacitor, which has the same pattern shape and is directly opposed in the stacking direction.   The capacitor is a multilayer ceramic capacitor in which ceramic dielectric layers and internal electrode layers are alternately stacked, and a plurality of via conductors connected to the internal electrode layers are arranged in an array. The wiring board with a built-in capacitor described in 1. In the first region of the capacitor, a plurality of via conductors for the first positive electrode and a plurality of via conductors for the negative electrode are arranged in an array,
A plurality of via conductors for the second positive electrode and a plurality of via conductors for the negative electrode are arranged in an array in the second region of the capacitor;
The wiring board with a built-in capacitor according to claim 2.   The first capacitor side conductor pattern is formed at a central portion of the surface of the capacitor, and the second capacitor side conductor pattern is formed at a peripheral portion of the surface of the capacitor. The wiring board with a built-in capacitor according to any one of 1 to 3.   The first capacitor-side conductor pattern is formed in a protruding portion that protrudes from the central portion to a part of the peripheral portion and extends to the outer edge of the capacitor, in addition to the central portion. The wiring board with a built-in capacitor according to claim 4.   The first power source is a main power source supplied to a main circuit of the semiconductor element, and the second power source is an I / O circuit power source supplied to an I / O circuit of the semiconductor element. The wiring board with a built-in capacitor according to any one of claims 1 to 5. A core material; a capacitor accommodated in the core material; and a laminated portion in which an insulating layer and a conductor layer are alternately laminated on the upper surface side and the lower surface side of the core material, and a semiconductor element is provided above the laminated portion. A wiring board that can be placed,
N conductor patterns including each of N different power supply wirings are formed on a predetermined conductor layer of the laminated portion,
The capacitor has N regions each forming a capacitance between each of the N positive electrodes and the negative electrode,
On the upper surface of the capacitor, N capacitor-side conductor patterns including wirings connecting the N terminal electrodes for the positive electrodes to the N power sources are formed,
Each of the N conductor patterns and the corresponding N capacitor-side conductor patterns have the same pattern shape and are directly opposed to each other in the stacking direction.

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