JP2007129046A - Mounting structure of capacitor array - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To solve the problem that mounting work of a chip-type capacitor becomes still more difficult, causing poor mounting or making it impossible to mount, derived from more difficulty because of the short distance between the lands formed in the grid terminal of a mounting board as a multiple-pin BGA semiconductor device progresses, since surface mounting of a chip-type capacitor is conventionally carried out along the array direction of the grid terminal. <P>SOLUTION: A mounting structure 10 of a capacitor array is constituted such that a low ESL capacitor array 12 is mounted by soldering to a grid terminal 11A formed in the opposite side of a mounting board 11 where a BGA semiconductor device 20 is mounted. The low ESL capacitor array 12 may be arranged obliquely at an angle θ of 45° to the arranging direction of the grid terminal 11A. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a structure in which a capacitor array is mounted on the opposite surface of a substrate on which a ball grid array semiconductor device is mounted. More specifically, the present invention can deal with a grid terminal having a narrow pitch until it is difficult to mount a capacitor. The present invention relates to a capacitor mounting structure.

  Semiconductor devices have become multi-pinned along with higher performance and higher functionality. In addition, the demand for high-density mounting of semiconductor devices has become stronger as electronic devices become smaller and lighter. As the number of pins of a semiconductor device increases, the number of terminals increases, and the pitch of the terminals is rapidly reduced due to the demand for high-density mounting. Therefore, as a semiconductor device that meets such requirements, for example, a ball grid array (hereinafter referred to as “BGA”) type semiconductor device has been put into practical use.

  A decoupling capacitor that compensates for the function of the BGA semiconductor device is surface-mounted on the substrate on which the BGA semiconductor device is mounted. When mounting a decoupling capacitor on a substrate, a chip capacitor is disposed along the arrangement direction with respect to a grid terminal conventionally formed on the opposite surface of the substrate on which the BGA semiconductor device is mounted, Implemented.

  For example, Patent Document 1 proposes a multilayer capacitor, a semiconductor device, and an electronic circuit board. In this electronic circuit board, a three-terminal capacitor is used as a decoupling capacitor. By using a three-terminal capacitor, sufficient capacity, low self-inductance, and high LC resonance frequency are realized. Also in this case, the three-terminal capacitors are arranged and mounted along the arrangement direction of the grid terminals.

JP2002-025856

  However, since the conventional chip-type capacitors are surface-mounted along the grid terminal arrangement direction, the distance between the land portions formed on the grid terminals of the mounting board becomes shorter as the number of pins of the BGA semiconductor device increases. As a result, the mounting work of the chip type capacitor becomes more and more difficult, which may lead to mounting failure or mounting failure. Further, in the technique of the electronic circuit board disclosed in Patent Document 1, since a three-terminal capacitor is used as a decoupling capacitor, the ground electrode and the grid terminal of the mounting board corresponding to the ground electrode are separated from each other, and the wiring between them becomes longer, resulting in an inductance. The component increases and the insertion loss characteristic deteriorates. Further, when a plurality of three-terminal capacitors are mounted, the power supply terminal and the ground terminal of the BGA semiconductor device have to be mounted in series.

  The present invention has been made to solve the above-described problem, and can mount a capacitor reliably even when the distance between grid terminals of a mounting board of a BGA semiconductor device is shortened, and has a high frequency insertion loss characteristic of the capacitor. Further, it is an object of the present invention to provide a capacitor array mounting structure capable of efficiently mounting capacitors on power supply terminals and ground terminals of a BGA semiconductor device.

  A capacitor array mounting structure according to claim 1 of the present invention is a capacitor array mounting structure in which a capacitor array is mounted by soldering on a grid terminal of a substrate on which a ball grid array type semiconductor device is mounted. The capacitor array is disposed obliquely with respect to the arrangement direction of the grid terminals.

  According to a second aspect of the present invention, there is provided a capacitor array mounting structure according to the first aspect, wherein the capacitor array is a low ESL chip type capacitor array.

  According to the first and second aspects of the present invention, the capacitor can be reliably mounted even when the distance between the grid terminals of the mounting substrate of the BGA semiconductor device is shortened, and the capacitor has a high frequency insertion. It is possible to provide a capacitor array mounting structure that can maintain loss characteristics and that can efficiently mount capacitors on the power supply terminal and the ground terminal of the BGA semiconductor device.

  Hereinafter, the present invention will be described based on the embodiment shown in FIGS.

First Embodiment A capacitor array mounting structure 10 according to the present embodiment is planar with respect to the arrangement direction of grid terminals 11A formed on one main surface of a mounting substrate 11, for example, as shown in FIGS. A chip-type capacitor array (hereinafter simply referred to as “capacitor array”) 12 having a rectangular shape is mounted in an oblique manner. As shown in the figure, when the horizontal arrangement direction of the grid terminals 11A is a and the major axis direction of the capacitor array 12 is b, the angle θ formed by the grid arrangement direction a and the major axis direction b of the capacitor array 12 is 45 °.

  Further, on the other main surface (the upper surface in the figure) of the mounting substrate 11, grid terminals 11B corresponding to the grid terminals 11A on the lower surface are formed as shown in FIG. These grid terminals 11 </ b> A and 11 </ b> B are formed in a pattern corresponding to the arrangement pattern of grid terminals (not shown) of the BGA semiconductor device 20 mounted on the upper surface of the mounting substrate 11. The grid terminals 11A and 11B on the upper and lower surfaces of the mounting substrate 11 are electrically connected via a conductor portion 11C filled in a through hole or a via hole (hereinafter referred to as “through hole”) as shown in FIG. It is connected to the. Further, wiring conductors (not shown) are formed in a predetermined pattern on both surfaces of the mounting substrate 11, and land portions 11D and 11E of these wiring conductors are connected to the upper and lower ends of the conductor portion 11C, respectively. Each of the grid terminals 11A and 11B is formed by a solder ball formed on the conductor portion 11C. A conductor film (not shown) is formed on the inner peripheral surface of the through hole by means such as plating.

  As shown in FIGS. 1 and 3, the capacitor array 12 used in the present embodiment extends in parallel with each other in the short axis direction in the ceramic body portion in which a plurality of ceramic layers 12A are laminated. In addition, a ceramic is formed between the first internal electrodes 12B and 12B formed in a plurality of stages between the upper and lower ceramic layers 12A and 12A and the first internal electrodes 12B and 12B extending in the long axis direction in the ceramic body. The second internal electrode 12C formed over a plurality of upper and lower stages across the layer 12A, and the side surfaces in the major axis direction and the upper and lower surfaces of the ceramic body portion connected to both end surfaces of the first internal electrodes 12B and 12B, respectively. Two pairs of first external terminal electrodes 12D and 12E covering the end portions and both end surfaces of the second internal electrode 12C and the side surfaces in the end axial direction of the ceramic body portion and both upper and lower surfaces A pair of second external terminal electrodes 12F covering the part, and 12G, the lower capacitor array residual inductance including the equivalent series inductance (hereinafter, referred to as "low ESL capacitor array") is constructed as a. Further, as shown in FIG. 1, the first external terminal electrodes 12D and 12E are connected to the grid terminals 11A and 11A on the power supply side facing each other in the oblique direction, and the second external terminal electrodes 12F and 12G are grounded in the oblique direction. Are connected to the grid terminals 11A and 11A on the side. An unused grid terminal 11A (shown by a broken line in FIG. 1) is interposed between the grid terminals 11A and 11A to which the second external terminal electrodes 12F and 12G are connected.

  In the mounting structure of this embodiment, the low ESL capacitor array 12 is disposed obliquely with respect to the grid terminal 11A as shown in FIGS. 1 and 4, but in the conventional mounting structure, as shown in FIG. The capacitor array 12 ′ is arranged so as to coincide with the arrangement direction of the grid terminals 11A. Thus, the distance d (see FIG. 4) between the land portions 11C and 11C to which the first external terminal electrodes 12D and 12E in the mounting structure of the present embodiment are connected, and the first external terminal electrode 12 in the conventional mounting structure. Comparing the distance d1 (see FIG. 5) between the lands 11′C and 11′C to which “D, 12” E is connected, the distance d in this embodiment is longer than the conventional inter-electrode distance d1. The length is 1.4 times the conventional inter-electrode distance d1.

  Here, the distance d between the land portions 11C and 11C is the distance between the first external terminal electrodes 12D and 12E, and the distance d1 between the land portions 11′C and 11′C is the first external terminal electrode 12′D, Assuming that the distance between the electrodes is 12′E, when the number of pins of the BGA semiconductor device 20 is increased and the grid terminals are narrowed, the distance between the electrodes d1 is shortened in the conventional mounting structure and the low ESL capacitor array 12 ′ is mounted. However, since the inter-electrode distance d is increased to 1.4 times the inter-electrode distance d1 in the mounting structure of this embodiment, there is a distance in mounting the low ESL capacitor array 12, The difficulty of the mounting operation is reduced, and the low ESL capacitor array 12 can be reliably mounted, and mounting defects can be prevented. Further, in the mounting structure of the present embodiment, since the inter-electrode distance d is longer than the conventional inter-electrode distance d1, a short circuit between the first external terminal electrodes 12D and 12E adjacent on the same side surface can be prevented. Furthermore, in the mounting structure of the present embodiment, since the low ESL capacitor array 12 is disposed obliquely, the inter-electrode distance d can be afforded, so that the low ESL capacitor array 12 is matched to the pitch (d1) of the grid terminals 11A. There is no need to downsize.

  In the present embodiment, the low ESL capacitor array 12 is mounted obliquely to reduce the residual inductance of the entire ground line to which the second external terminal electrodes 12F and 12G are connected, and the high ESL capacitor array 12 has a high high frequency. Insertion loss can be maintained. Moreover, as shown in FIGS. 4 and 5, in the conventional mounting structure, there are two unused grid terminals 11C and 11C directly below the low ESL capacitor array 12, but in the mounting structure of this embodiment, the low ESL capacitor array is used. Since there is only one unused grid terminal 11C directly under 12, in this embodiment, unused grid terminals 11C can be reduced.

  As described above, according to the present embodiment, the low ESL capacitor array 12 is disposed obliquely with respect to the arrangement direction of the grid terminals 11A of the mounting substrate 11 on which the BGA semiconductor device 20 is mounted via the grid terminals 11C. Since it is mounted on the mounting substrate 11, even if the number of pins of the BGA semiconductor device 20 is increased, the low ESL capacitor array 12 can be reliably mounted by reducing the difficulty of mounting the low ESL capacitor array 12. Defects can be prevented. In addition, the distance between the electrodes of the adjacent first external terminal electrodes 12D and 12E of the low ESL capacitor array 12 is increased, and a short circuit between the first external terminal electrodes 12D and 12E can be prevented.

  Further, since the second external terminal electrodes 12G and 12H of the low ESL capacitor array 12 are connected to the grid terminal 11C on the ground side, the residual inductance of the entire ground line is lowered, and the high frequency insertion loss characteristic of the low ESL capacitor array 12 is improved. It is possible to reduce unused grid terminals 11C while maintaining them. Further, the low ESL capacitor array 12 can be efficiently mounted on the power supply and ground of the BGA semiconductor device 20 via the two pairs of first external terminal electrodes 12E and 12F and the second external terminal electrodes 12G and 12H.

Second Embodiment The capacitor array mounting structure of the present embodiment is configured in accordance with the first embodiment except that a capacitor array that is not a low ESL type is used, and is the same as that of the first embodiment. The present embodiment will be described with the same reference numerals assigned to portions or corresponding portions.

  The capacitor array mounting structure 10A of the present embodiment has a mounting structure in which a capacitor array 12 having a rectangular planar shape is arranged obliquely with respect to a grid terminal 11A formed on the lower surface of the mounting substrate 11, as shown in FIG. It has a structure. As shown in the figure, the angle θ formed by the arrangement direction of the grid terminals 11A and the arrangement direction of the capacitor array 12 is 45 °.

  As shown in FIGS. 6 and 7, the capacitor array 12 includes a ceramic body portion in which a plurality of ceramic layers 12A are laminated, and parallel to each other in the minor axis direction within the ceramic body portion, and upper and lower ceramic layers 12A. The inner electrodes 12B and 12B formed in a plurality of stages between 12A and 12A are connected to both end faces of the inner electrodes 12B and 12B, respectively, and the side surfaces in the major axis direction and the upper and lower ends of the ceramic body are covered. And two pairs of first external terminal electrodes 12D and 12E. The external terminal electrodes 12D and 12E are connected to the grid terminal 11A on the power supply side and the grid terminal 11A on the ground side that face each other in an oblique direction. An unused grid terminal 11A is interposed directly above the center of the capacitor array 12 as shown in FIG.

  According to the present embodiment, the same operational effects as those of the first embodiment can be expected except that the capacitor array 12 is not low ESL.

  The present invention is not limited to the above-described embodiments. In short, the capacitor array is arranged with respect to the arrangement direction of the grid terminals formed on the opposite surface of the mounting substrate on which the BGA semiconductor device is mounted. Any mounting structure that is arranged obliquely is included in the present invention.

  The present invention can be suitably used for a mounting structure of a capacitor array used in an electronic device or the like.

It is a top view which shows one Embodiment of the mounting structure of the capacitor | condenser array of this invention. It is sectional drawing which cut | disconnected the mounting structure of the capacitor | condenser array shown in FIG. 1 along the II-II line. FIG. 3 is an exploded perspective view showing a ceramic body part of the low ESL capacitor array shown in FIG. 2. It is explanatory drawing for demonstrating the distance between the electrodes of the 1st external terminal electrode of the mounting structure of the capacitor | condenser array shown in FIG. It is explanatory drawing for demonstrating the distance between the electrodes of the 1st external terminal electrode of the low ESL capacitor array in the conventional mounting structure. It is a top view which shows other embodiment of the mounting structure of the capacitor | condenser array of this invention. It is a perspective view which decomposes | disassembles and shows the ceramic body part of the capacitor | condenser array shown in FIG.

Explanation of symbols

10, 10A Capacitor Array Mounting Structure 11 Mounting Board 11A Grid Terminal 12 Capacitor Array (Chip Type Capacitor Array)

Claims (2)

  A capacitor array mounting structure in which a capacitor array is mounted by soldering on a grid terminal of a substrate on which a ball grid array type semiconductor device is mounted, wherein the capacitor array is inclined with respect to the arrangement direction of the grid terminals. A capacitor array mounting structure characterized by the arrangement.   2. The capacitor array mounting structure according to claim 1, wherein the capacitor array is a low ESL chip type capacitor array.

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