WO2021084750A1 - Interposer mounted substrate - Google Patents
Interposer mounted substrate Download PDFInfo
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- WO2021084750A1 WO2021084750A1 PCT/JP2019/043115 JP2019043115W WO2021084750A1 WO 2021084750 A1 WO2021084750 A1 WO 2021084750A1 JP 2019043115 W JP2019043115 W JP 2019043115W WO 2021084750 A1 WO2021084750 A1 WO 2021084750A1
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- WIPO (PCT)
- Prior art keywords
- interposer
- capacitor
- wiring path
- wiring
- connection terminal
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/12—Mountings, e.g. non-detachable insulating substrates
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/32—Holders for supporting the complete device in operation, i.e. detachable fixtures
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/46—Manufacturing multilayer circuits
Definitions
- the present invention relates to an interposer mounting board on which an interposer, which is a printed wiring board for rewiring between a semiconductor chip such as an electronic component and a motherboard, is mounted.
- a bypass capacitor or a capacitor called a decap is used. This capacitor plays the role of lowering the impedance with respect to the ground of the power supply line and the role of filtering to absorb noise.
- Patent Document 1 since the wiring path from the IC once passes through the capacitor in the interposer, it is possible to reduce the power supply noise and the power supply impedance, but after that, the wiring path returns to the surface on the IC side and a through hole is formed. Proceed toward the motherboard via. Since such a wiring path has a long wiring length, it causes an increase in wiring inductance.
- the present invention takes into consideration the above-mentioned prior art, and an object of the present invention is to provide an interposer mounting board capable of preventing not only power supply noise and power supply impedance but also an increase in wiring inductance.
- the motherboard the interposer electrically connected to the motherboard via the plurality of first connection terminals, and the interposer via the plurality of second connection terminals.
- a plurality of wiring paths that connect an electrically connected IC and the first connection terminal and the corresponding second connection terminal through the interposer, and on the wiring path.
- the interposer includes a capacitor arranged and built in the interposer, the interposer has a multilayer plate structure composed of a plurality of insulating layers and a plurality of conductive layers, and the wiring path penetrates the insulating layer.
- An interposer that is formed of an interlayer connection portion that electrically connects conductive layers and the conductive layer, and that the wiring path has only one interlayer connection portion per insulating layer.
- a mounting board is provided.
- the signal line transmitted from the IC to the motherboard passes through the wiring path, and the signal line does not pass through the insulating layer that has passed through the interlayer connection portion again.
- only one capacitor is arranged for each of the two wiring paths.
- each wiring path since each wiring path has only one interlayer connection portion for each insulating layer, the wiring path does not return to this insulating layer once it has passed through the insulating layer. Therefore, as a wiring path, for example, when viewed from the first connection terminal, it always goes in the direction of the second connection terminal except when passing through the conductive layer, and the first connection terminal is in the middle of the wiring path. Do not turn in the direction of. Therefore, the wiring path can be shortened and the wiring inductance can be reduced. The same effect can be obtained when the signal line emitted from the IC is transmitted from the second connection terminal toward the first connection terminal. Further, by arranging the capacitor in the interposer, the distance from the first and second connection terminals can be shortened.
- ESR equivalent series resistance
- the interposer mounting board 1 includes a motherboard 2.
- An interposer 4 is electrically connected to the motherboard 2 via a first connection terminal 3.
- the first connection terminal 3 is arranged on the plurality of motherboards 2.
- An IC 6 is electrically connected to the interposer 4 via a second connection terminal 5.
- a plurality of second connection terminals 5 are also arranged.
- ICs include electronic components and semiconductor chips.
- the first and second connection terminals 3 and 5 may be any terminals for electrical connection such as BGA and wire bonding.
- what is supposed to be used in the present invention is one in which about 100 to 1000 first terminals 3 are arranged.
- the interposer 4 is arranged directly under the IC 6, and the motherboard 2 is arranged directly under the interposer 4.
- a wiring path 7 is formed in the interposer 4.
- the wiring path 7 connects the first connection terminal 3 and the corresponding second connection terminal 5 (in the meantime, the wiring path 7 always passes through the capacitor 8 described later).
- the first connection terminal 3 is always provided with the corresponding second connection terminal 5. That is, each of the first and second connection terminals 3 and 5 forms a pair. Therefore, a plurality of wiring paths 7 are also formed according to the number of the corresponding first and second connection terminals 3, 5.
- a capacitor 8 is arranged on the wiring path 7. Specifically, the capacitor 8 is built in the interposer and functions as a part of the wiring path 7.
- the power supply from the motherboard 2 or the signal line from the IC 6 is supplied to each other through each wiring path 7 and from each through the capacitor 8 in the interposer 4.
- the capacitor 8 By passing through the capacitor 8 in this way, noise and impedance are reduced.
- the interposer 4 has a multilayer plate structure composed of a plurality of insulating layers 9 and a plurality of conductive layers 10.
- FIG. 2 shows a so-called six-sided multilayer plate structure, which is composed of six conductive layers 10 and five insulating layers 9.
- an interlayer connection portion 11 that penetrates the insulating layer 9 and electrically connects the conductive layers 10 formed on both sides thereof is used as a part thereof.
- the conductive layer 10 is also used as a part thereof.
- a filled via as shown may be used, or a through hole may be used.
- each wiring path 7 has only one interlayer connection portion 11 for one insulating layer 9.
- the wiring path 7 does not return to the insulating layer 9 once it has passed through the insulating layer 9. (There is no choice but to proceed through the conductive layer 10 and pass through the next insulating layer 9). Therefore, the wiring path 7 always goes in the direction of the second connection terminal 5 except when passing through the conductive layer 10, when viewed from the first connection terminal 3, for example, in the middle of the wiring path 7. It does not face the direction of the first connection terminal 3. Therefore, the wiring path 7 can be shortened, and the wiring inductance can be reduced.
- the capacitor 8 Since the capacitor 8 is built in the interposer 4 as described above, it contributes to shortening the wiring path 7.
- the portion of the motherboard 2 directly under the IC 6 is a portion where wiring is dense as a high-density wiring area 13. If the capacitor 8 is built in the motherboard 2, a space for burying the capacitor 8 must be provided in the motherboard 2, so that the design of such a high-density wiring area 13 is also restricted. In this respect as well, there is an effect that the capacitor 8 is built in the interposer 4.
- the interposer 4 has more space inside than the motherboard 2, and by arranging one capacitor 8 for every two wiring paths 7 using this space, many capacitors 8 can be used as the interposer 4. It can be built into the capacitor, and the equivalent series resistance (ESR) can be sufficiently reduced.
- ESR equivalent series resistance
- the signal line emitted from the IC 6 passes through the second connection terminal 5 and proceeds from the first layer conductive layer 10 to the third layer conductive layer 10. Then, it passes through the electrode 12 of the capacitor 8 through the interlayer connection portion 11 above the capacitor 8 formed in the insulating layer 9 of the third layer from the conductive layer 10 of the third layer. Then, it passes through the interlayer connection portion 11 under the electrode 12 of the capacitor 8 arranged in the insulating layer 9 of the third layer and passes through the conductive layer 10 of the fourth layer. Then, it passes through the interlayer connection portions 11 of the 4th and 5th layers as it is, passes through the conductive layer 10 of the 6th layer, and is transmitted to the first connection terminal 3.
- the electrode 12 of the capacitor 8 is the first connection terminal 3 and the second connection terminal 5. It is preferable that they are arranged on a straight line connecting the above.
- FIG. 2 shows an interposer 4 having a conductive layer 10 from the first layer to the sixth layer counting from the top, and also having an insulating layer 9 from the first layer to the fifth layer counting from the top. ..
Abstract
An interposer mounted substrate (1) is provided with: a mother board (2); an interposer (4) electrically connected to the mother board (2) via a plurality of first connection terminals (3); an IC (6) electrically connected to the interposer (4) via a plurality of second connection terminals (5); a plurality of wire paths (7) passing through the inside of the interposer (4); and a capacitor (8) incorporated in the interposer (4). The interposer (4) has a multi-layer plate structure comprising a plurality of conductive layers (10) and a plurality of insulation layers (9) having inter-layer connection parts (11). In each of the insulation layers (9), the number of the inter-layer connection parts (11) included in one of the wire paths (7) is only one.
Description
本発明は、電子部品等の半導体のチップとマザーボードとの間の再配線を行うプリント配線板であるインターポーザが実装されたインターポーザ実装基板に関する。
The present invention relates to an interposer mounting board on which an interposer, which is a printed wiring board for rewiring between a semiconductor chip such as an electronic component and a motherboard, is mounted.
近年、基板における高密度配線化が進み、電源ノイズや電源インピーダンスの増加が問題となっている。これらを防止するため、バイパスコンデンサあるいはパスコンと称されるコンデンサが使用されている。このコンデンサは、電源ラインのグラウンドに対してインピーダンスを下げる役割や、ノイズを吸収するフィルタリングの役割を果たす。
In recent years, high-density wiring on the board has progressed, and power supply noise and an increase in power supply impedance have become problems. In order to prevent these, a bypass capacitor or a capacitor called a decap is used. This capacitor plays the role of lowering the impedance with respect to the ground of the power supply line and the role of filtering to absorb noise.
このようなノイズ除去等を目的としたコンデンサを、電子部品（ＩＣ）とマザーボードとの間に配されるインターポーザに内蔵する技術も知られている（例えば特許文献１参照）。
There is also known a technique of incorporating a capacitor for the purpose of removing such noise in an interposer arranged between an electronic component (IC) and a motherboard (see, for example, Patent Document 1).
しかしながら、特許文献１では、ＩＣからの配線経路は一旦インターポーザ内のコンデンサを通過するため電源ノイズや電源インピーダンスの低減は可能であるが、その後配線経路はＩＣ側の表面に戻り、そしてスルーホールを介してマザーボード方向に進む。このような配線経路はその配線長さが長いため、配線インダクタンスの増加を招く。
However, in Patent Document 1, since the wiring path from the IC once passes through the capacitor in the interposer, it is possible to reduce the power supply noise and the power supply impedance, but after that, the wiring path returns to the surface on the IC side and a through hole is formed. Proceed toward the motherboard via. Since such a wiring path has a long wiring length, it causes an increase in wiring inductance.
本発明は、上記従来技術を考慮したものであり、電源ノイズや電源インピーダンスだけでなく、配線インダクタンスの増加をも防止することができるインターポーザ実装基板を提供することを目的とする。
The present invention takes into consideration the above-mentioned prior art, and an object of the present invention is to provide an interposer mounting board capable of preventing not only power supply noise and power supply impedance but also an increase in wiring inductance.
前記目的を達成するため、本発明では、マザーボードと、該マザーボードと複数の第１の接続端子を介して電気的に接続されているインターポーザと、該インターポーザと複数の第２の接続端子を介して電気的に接続されているＩＣと、前記インターポーザ内を通って前記第１の接続端子とこれに対応する前記第２の接続端子との間をつなぐ複数本の配線経路と、該配線経路上に配されて前記インターポーザに内蔵されているコンデンサとを備え、前記インターポーザは、複数の絶縁層及び複数の導電層からなる多層板構造を有し、前記配線経路は、前記絶縁層を貫通して前記導電層間を電気的に接続させる層間接続部及び前記導電層で形成されていて、１本当たりの前記配線経路が有する前記層間接続部は各前記絶縁層当たり一のみであることを特徴とするインターポーザ実装基板を提供する。
In order to achieve the above object, in the present invention, the motherboard, the interposer electrically connected to the motherboard via the plurality of first connection terminals, and the interposer via the plurality of second connection terminals. A plurality of wiring paths that connect an electrically connected IC and the first connection terminal and the corresponding second connection terminal through the interposer, and on the wiring path. The interposer includes a capacitor arranged and built in the interposer, the interposer has a multilayer plate structure composed of a plurality of insulating layers and a plurality of conductive layers, and the wiring path penetrates the insulating layer. An interposer that is formed of an interlayer connection portion that electrically connects conductive layers and the conductive layer, and that the wiring path has only one interlayer connection portion per insulating layer. A mounting board is provided.
好ましくは、前記ＩＣから前記マザーボードに向けて送信される信号線は前記配線経路を通り、前記信号線は前記層間接続部を通って通過した前記絶縁層を再び通らない。
Preferably, the signal line transmitted from the IC to the motherboard passes through the wiring path, and the signal line does not pass through the insulating layer that has passed through the interlayer connection portion again.
好ましくは、前記コンデンサは、２本当たりの前記配線経路につき１つのみが配されている。
Preferably, only one capacitor is arranged for each of the two wiring paths.
本発明によれば、１本当たりの配線経路が有する層間接続部は各絶縁層当たり一のみであるため、配線経路は一度絶縁層を通ったら二度とこの絶縁層を戻ることはない。したがって、配線経路としては、例えば第１の接続端子から見れば、導電層を通る場合を除いて、必ず第２の接続端子の方向に向かうことになり、配線経路の途中で第１の接続端子の方向を向くことはない。このため、配線経路を短くすることができ、配線インダクタンスを低減させることができる。ＩＣから発せられる信号線が第２の接続端子から第１の接続端子に向かって送信されるときも同様の効果を得ることができる。また、コンデンサをインターポーザ内に配することで、第１及び第２の接続端子との距離を短くすることができる。
According to the present invention, since each wiring path has only one interlayer connection portion for each insulating layer, the wiring path does not return to this insulating layer once it has passed through the insulating layer. Therefore, as a wiring path, for example, when viewed from the first connection terminal, it always goes in the direction of the second connection terminal except when passing through the conductive layer, and the first connection terminal is in the middle of the wiring path. Do not turn in the direction of. Therefore, the wiring path can be shortened and the wiring inductance can be reduced. The same effect can be obtained when the signal line emitted from the IC is transmitted from the second connection terminal toward the first connection terminal. Further, by arranging the capacitor in the interposer, the distance from the first and second connection terminals can be shortened.
また、配線経路２本につき１つのコンデンサを配することで、多くのコンデンサをインターポーザに内蔵することができ、等価直列抵抗（ＥＳＲ）を十分に低減させることができる。
Further, by arranging one capacitor for every two wiring paths, many capacitors can be built in the interposer, and the equivalent series resistance (ESR) can be sufficiently reduced.
図１を参照すれば明らかなように、本発明に係るインターポーザ実装基板１は、マザーボード２を備えている。このマザーボード２には、第１の接続端子３を介してインターポーザ４が電気的に接続されている。第１の接続端子３は複数マザーボード２上に配設されている。インターポーザ４には、第２の接続端子５を介してＩＣ６が電気的に接続されている。第２の接続端子５も複数配されている。ＩＣは電子部品や半導体チップを含む。第１及び第２の接続端子３、５はＢＧＡやワイヤボンディング等、電気的に接続するための端子であればどのようなものを用いてもよい。なお、本願発明が使用されるのに想定されているものは、第１の端子３がおよそ１００～１０００個配されているものである。なお、インターポーザ４はＩＣ６の真下に、マザーボード２はインターポーザ４の真下に配されている。
As is clear from FIG. 1, the interposer mounting board 1 according to the present invention includes a motherboard 2. An interposer 4 is electrically connected to the motherboard 2 via a first connection terminal 3. The first connection terminal 3 is arranged on the plurality of motherboards 2. An IC 6 is electrically connected to the interposer 4 via a second connection terminal 5. A plurality of second connection terminals 5 are also arranged. ICs include electronic components and semiconductor chips. The first and second connection terminals 3 and 5 may be any terminals for electrical connection such as BGA and wire bonding. In addition, what is supposed to be used in the present invention is one in which about 100 to 1000 first terminals 3 are arranged. The interposer 4 is arranged directly under the IC 6, and the motherboard 2 is arranged directly under the interposer 4.
インターポーザ４内には、配線経路７が形成されている。この配線経路７は、第１の接続端子３とこれに対応する第２の接続端子５との間をつなぐものである（その間、配線経路７は必ず後述するコンデンサ８を通る）。第１の接続端子３には必ず対応する第２の接続端子５が配されている。すなわち、ひとつずつの第１及び第２の接続端子３、５にて一対となっている。したがって、これら対応する第１及び第２の接続端子３、５の数に応じて配線経路７も複数本形成されている。そして、この配線経路７上にはコンデンサ８が配されている。具体的には、コンデンサ８はインターポーザに内蔵され、配線経路７の一部として機能している。
A wiring path 7 is formed in the interposer 4. The wiring path 7 connects the first connection terminal 3 and the corresponding second connection terminal 5 (in the meantime, the wiring path 7 always passes through the capacitor 8 described later). The first connection terminal 3 is always provided with the corresponding second connection terminal 5. That is, each of the first and second connection terminals 3 and 5 forms a pair. Therefore, a plurality of wiring paths 7 are also formed according to the number of the corresponding first and second connection terminals 3, 5. A capacitor 8 is arranged on the wiring path 7. Specifically, the capacitor 8 is built in the interposer and functions as a part of the wiring path 7.
以上のような構成により、マザーボード２からの電源、あるいはＩＣ６からの信号線は、各配線経路７を通ってそれぞれからインターポーザ４内のコンデンサ８を通って互いに供給される。このようにコンデンサ８を通ることで、ノイズやインピーダンスは低減される。
With the above configuration, the power supply from the motherboard 2 or the signal line from the IC 6 is supplied to each other through each wiring path 7 and from each through the capacitor 8 in the interposer 4. By passing through the capacitor 8 in this way, noise and impedance are reduced.
ここで、図２を参照すれば明らかなように、インターポーザ４は、複数の絶縁層９及び複数の導電層１０からなる多層板構造を有している。例えば図２ではいわゆる６面の多層板構造を示し、６層の導電層１０及び５層の絶縁層９から構成されている。インターポーザ４内を通過する配線経路７は、絶縁層９を貫通してその両面に形成されている導電層１０間を電気的に接続させる層間接続部１１がその一部として使用されていて、さらに導電層１０もその一部として使用されている。層間接続部１１としては図示したようなフィルドビアを用いてもよいし、スルーホールを利用してもよい。
Here, as is clear from FIG. 2, the interposer 4 has a multilayer plate structure composed of a plurality of insulating layers 9 and a plurality of conductive layers 10. For example, FIG. 2 shows a so-called six-sided multilayer plate structure, which is composed of six conductive layers 10 and five insulating layers 9. In the wiring path 7 passing through the interposer 4, an interlayer connection portion 11 that penetrates the insulating layer 9 and electrically connects the conductive layers 10 formed on both sides thereof is used as a part thereof. The conductive layer 10 is also used as a part thereof. As the interlayer connection portion 11, a filled via as shown may be used, or a through hole may be used.
ここで、１本当たりの配線経路７が有する層間接続部１１は、各絶縁層９当たり一のみである。すなわち、１本の配線経路７は一の絶縁層９に対して層間接続部１１を一つしか有しない。このように、１本当たりの配線経路７が有する層間接続部１１は各絶縁層９当たり一のみであるため、配線経路７は一度絶縁層９を通ったら二度とこの絶縁層９を戻ることはない（導電層１０を進み、次なる絶縁層９を通過するしかない）。したがって、配線経路７としては、例えば第１の接続端子３から見れば、導電層１０を通る場合を除いて、必ず第２の接続端子５の方向に向かうことになり、配線経路７の途中で第１の接続端子３の方向を向くことはない。このため、配線経路７を短くすることができ、配線インダクタンスを低減させることができる。
Here, there is only one interlayer connection portion 11 per wiring path 7 for each insulating layer 9. That is, one wiring path 7 has only one interlayer connection portion 11 for one insulating layer 9. In this way, since the interlayer connection portion 11 of each wiring path 7 is only one for each insulating layer 9, the wiring path 7 does not return to the insulating layer 9 once it has passed through the insulating layer 9. (There is no choice but to proceed through the conductive layer 10 and pass through the next insulating layer 9). Therefore, the wiring path 7 always goes in the direction of the second connection terminal 5 except when passing through the conductive layer 10, when viewed from the first connection terminal 3, for example, in the middle of the wiring path 7. It does not face the direction of the first connection terminal 3. Therefore, the wiring path 7 can be shortened, and the wiring inductance can be reduced.
このことは、別の観点からすれば以下のようにも説明できる。ＩＣ６からマザーボード２に向けて信号線が送信された場合、この信号線は第２の接続端子５から配線経路７を通ってコンデンサ８及び第１の接続端子３へと進む。このとき、信号線は層間接続部１１を通って通過した絶縁層９を再び通らないということになる。すなわち、一度通過した絶縁層９を再び通過することはない。このことは、やはり配線インダクタンスの低減に寄与する。
This can be explained as follows from another point of view. When a signal line is transmitted from the IC 6 to the motherboard 2, the signal line proceeds from the second connection terminal 5 to the capacitor 8 and the first connection terminal 3 through the wiring path 7. At this time, the signal line does not pass through the insulating layer 9 that has passed through the interlayer connection portion 11 again. That is, it does not pass through the insulating layer 9 once passed through again. This also contributes to the reduction of the wiring inductance.
コンデンサ８は、上述したようにインターポーザ４に内蔵されているので、配線経路７を短くすることについて寄与している。特に、ＩＣ６直下のマザーボード２の部分は高密度配線エリア１３として配線が密集している部分である。マザーボード２にコンデンサ８を内蔵してしまうと、マザーボード２にコンデンサ８を埋設するスペースも設けなければならないので、このような高密度配線エリア１３の設計にも制約が出てしまう。この点でも、コンデンサ８をインターポーザ４に内蔵した効果がある。
Since the capacitor 8 is built in the interposer 4 as described above, it contributes to shortening the wiring path 7. In particular, the portion of the motherboard 2 directly under the IC 6 is a portion where wiring is dense as a high-density wiring area 13. If the capacitor 8 is built in the motherboard 2, a space for burying the capacitor 8 must be provided in the motherboard 2, so that the design of such a high-density wiring area 13 is also restricted. In this respect as well, there is an effect that the capacitor 8 is built in the interposer 4.
また、図２を参照すれば明らかなように、コンデンサ８は、２本当たりの配線経路７につき１つのみが配されている。コンデンサ８は電極１２を２つ有し、この各電極に１本ずつ配線経路７が接続されている。このように、マザーボード２に比べてインターポーザ４は内部のスペースに余裕があり、このスペースを利用して配線経路７を２本につき１つのコンデンサ８を配することで、多くのコンデンサ８をインターポーザ４に内蔵することができ、等価直列抵抗（ＥＳＲ）を十分に低減させることができる。
Further, as is clear from FIG. 2, only one capacitor 8 is arranged for every two wiring paths 7. The capacitor 8 has two electrodes 12, and one wiring path 7 is connected to each of these electrodes. In this way, the interposer 4 has more space inside than the motherboard 2, and by arranging one capacitor 8 for every two wiring paths 7 using this space, many capacitors 8 can be used as the interposer 4. It can be built into the capacitor, and the equivalent series resistance (ESR) can be sufficiently reduced.
例えば、図２に示すように、ＩＣ６から発せられた信号線は、第２の接続端子５を通り、１層目の導電層１０から３層目の導電層１０まで進む。そして３層目の導電層１０から３層目の絶縁層９に形成されたコンデンサ８の上側の層間接続部１１を通ってコンデンサ８の電極１２を通る。そして３層目の絶縁層９に配されたコンデンサ８の電極１２の下側の層間接続部１１を通って４層目の導電層１０を通る。そしてそのまま４層目及び５層目の層間接続部１１を通り、６層目の導電層１０を通過して第１の接続端子３へと伝わっていく。配線経路７としては、３層目及び４層目の導電層１０以外は全て第１の接続端子３の方向に向かっている。このような配線経路７でも十分に配線インダクタンスの低減を実現できるが、さらなる配線インダクタンスの低減を得たいのであれば、コンデンサ８の電極１２は第１の接続端子３と第２の接続端子５とを結ぶ直線上に配されていることが好ましい。なお、図２では上から数えて１層目から６層目までの導電層１０を有し、同じく上から数えて１層目から５層目までの絶縁層９を有するインターポーザ４を示している。
For example, as shown in FIG. 2, the signal line emitted from the IC 6 passes through the second connection terminal 5 and proceeds from the first layer conductive layer 10 to the third layer conductive layer 10. Then, it passes through the electrode 12 of the capacitor 8 through the interlayer connection portion 11 above the capacitor 8 formed in the insulating layer 9 of the third layer from the conductive layer 10 of the third layer. Then, it passes through the interlayer connection portion 11 under the electrode 12 of the capacitor 8 arranged in the insulating layer 9 of the third layer and passes through the conductive layer 10 of the fourth layer. Then, it passes through the interlayer connection portions 11 of the 4th and 5th layers as it is, passes through the conductive layer 10 of the 6th layer, and is transmitted to the first connection terminal 3. As the wiring path 7, all except the conductive layers 10 of the third layer and the fourth layer are directed toward the first connection terminal 3. Although such a wiring path 7 can sufficiently reduce the wiring inductance, if it is desired to further reduce the wiring inductance, the electrode 12 of the capacitor 8 is the first connection terminal 3 and the second connection terminal 5. It is preferable that they are arranged on a straight line connecting the above. Note that FIG. 2 shows an interposer 4 having a conductive layer 10 from the first layer to the sixth layer counting from the top, and also having an insulating layer 9 from the first layer to the fifth layer counting from the top. ..
１：インターポーザ実装基板、２：マザーボード、３：第１の接続端子、４：インターポーザ、５：第２の接続端子、６：ＩＣ、７：配線経路、８：コンデンサ、９：絶縁層、１０：導電層、１１：層間接続部、１２：電極、１３：高密度配線エリア
1: Interposer mounting board, 2: Motherboard, 3: First connection terminal, 4: Interposer, 5: Second connection terminal, 6: IC, 7: Wiring path, 8: Capacitor, 9: Insulation layer, 10: Conductive layer, 11: interlayer connection, 12: electrode, 13: high-density wiring area
Claims (3)
- マザーボードと、
該マザーボードと複数の第１の接続端子を介して電気的に接続されているインターポーザと、
該インターポーザと複数の第２の接続端子を介して電気的に接続されているＩＣと、
前記インターポーザ内を通って前記第１の接続端子とこれに対応する前記第２の接続端子との間をつなぐ複数本の配線経路と、
該配線経路上に配されて前記インターポーザに内蔵されているコンデンサとを備え、
前記インターポーザは、複数の絶縁層及び複数の導電層からなる多層板構造を有し、
前記配線経路は、前記絶縁層を貫通して前記導電層間を電気的に接続させる層間接続部及び前記導電層で形成されていて、
１本当たりの前記配線経路が有する前記層間接続部は各前記絶縁層当たり一のみであることを特徴とするインターポーザ実装基板。 Motherboard and
An interposer that is electrically connected to the motherboard via a plurality of first connection terminals,
An IC that is electrically connected to the interposer via a plurality of second connection terminals,
A plurality of wiring paths that pass through the interposer and connect between the first connection terminal and the corresponding second connection terminal.
It is provided with a capacitor arranged on the wiring path and built in the interposer.
The interposer has a multilayer structure composed of a plurality of insulating layers and a plurality of conductive layers.
The wiring path is formed of an interlayer connection portion that penetrates the insulating layer and electrically connects the conductive layers, and the conductive layer.
An interposer mounting substrate, characterized in that the wiring path has only one interlayer connection portion per insulating layer. - 前記ＩＣから前記マザーボードに向けて送信される信号線は前記配線経路を通り、前記信号線は前記層間接続部を通って通過した前記絶縁層を再び通らないことを特徴とする請求項１に記載のインターポーザ実装基板。 The first aspect of claim 1, wherein the signal line transmitted from the IC to the motherboard passes through the wiring path, and the signal line does not pass through the insulating layer that has passed through the interlayer connection portion again. Interposer mounting board.
- 前記コンデンサは、２本当たりの前記配線経路につき１つのみが配されていることを特徴とする請求項１に記載のインターポーザ実装基板。 The interposer mounting board according to claim 1, wherein only one capacitor is arranged for each of the two wiring paths.
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| PCT/JP2019/043115 WO2021084750A1 (en) | 2019-11-01 | 2019-11-01 | Interposer mounted substrate |
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| PCT/JP2019/043115 WO2021084750A1 (en) | 2019-11-01 | 2019-11-01 | Interposer mounted substrate |
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Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2012033949A (en) * | 2000-04-05 | 2012-02-16 | Ibiden Co Ltd | Printed wiring board and method of manufacturing the same |
| JP2015035496A (en) * | 2013-08-09 | 2015-02-19 | イビデン株式会社 | Method of manufacturing electronic component built-in wiring board |
| JP2015109346A (en) * | 2013-12-04 | 2015-06-11 | 日本特殊陶業株式会社 | Component incorporated wiring board and manufacturing method thereof |
| JP2016171118A (en) * | 2015-03-11 | 2016-09-23 | イビデン株式会社 | Circuit board and method of manufacturing the same |
| WO2017064791A1 (en) * | 2015-10-15 | 2017-04-20 | ルネサスエレクトロニクス株式会社 | Semiconductor device |
-
2019
- 2019-11-01 WO PCT/JP2019/043115 patent/WO2021084750A1/en active Application Filing
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2012033949A (en) * | 2000-04-05 | 2012-02-16 | Ibiden Co Ltd | Printed wiring board and method of manufacturing the same |
| JP2015035496A (en) * | 2013-08-09 | 2015-02-19 | イビデン株式会社 | Method of manufacturing electronic component built-in wiring board |
| JP2015109346A (en) * | 2013-12-04 | 2015-06-11 | 日本特殊陶業株式会社 | Component incorporated wiring board and manufacturing method thereof |
| JP2016171118A (en) * | 2015-03-11 | 2016-09-23 | イビデン株式会社 | Circuit board and method of manufacturing the same |
| WO2017064791A1 (en) * | 2015-10-15 | 2017-04-20 | ルネサスエレクトロニクス株式会社 | Semiconductor device |
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