JPH06338571A - Semiconductor device - Google Patents

Abstract

PURPOSE:To make conductors uniform in effective inductance to lessen the maximum DELTAI noise in a multilayered ceramic package wherein planar conductors are used for supplying a power and a grounding to a semiconductor chip. CONSTITUTION:A metal 21b formed on an insulating layer 21a by screen printing is split into eight conductors. Power supply conductors 22a and grounding conductors 22b are alternately disposed in the same power supply conductor 21 so as to make the adjacent conductors different from each other in potential. The power supply conductors 21 are so laminated in layers in a vertical direction as to enable the power supply conductors 22a and the grounding conductors 22b to be alternately disposed.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device using planar conductors as a power source and a ground in a package or a substrate, for example.

[0002]

2. Description of the Related Art FIG. 4 shows, for example, PGA (Pin Gr).
FIG. 3 shows a form of power supply / ground in a ceramic package of id Array type. That is, the power supply conductor 1 and the ground conductor 2 of this ceramic package have a structure in which a conductive material 4 such as tungsten (W) is screen-printed and laminated on an insulator 3 such as alumina (Al ₂ O ₃ ). Has been done.

In this case, the power supply conductor 1 and the ground conductor 2 are each constituted by one conductor (planar conductor) formed in one plane in the same plane (layer).

However, in the conventional case, when a current is evenly applied to the plane conductor, the effective inductance is larger toward the central portion of the conductor, so that the simultaneous switching noise (ΔI noise) becomes larger accordingly. there were.

That is, when a plurality of output buffers (not shown) in one chip are simultaneously switched, a potential fluctuation called ΔI noise occurs in the power supply conductor 1 and the ground conductor 2. This ΔI noise is non-uniformly distributed in the same plane, and malfunction may occur depending on the maximum value.

[0006]

As described above, in the related art, there is a problem that the ΔI noise becomes large because the effective inductance becomes larger toward the central portion of the plane conductor. Therefore, an object of the present invention is to provide a semiconductor device capable of uniformizing an effective inductance in a plane conductor and reducing the maximum value of simultaneous switching noise.

[0007]

To achieve the above object, in a semiconductor device of the present invention, a semiconductor element, a first conductor portion for supplying power to the semiconductor element, and a ground are provided. The second conductor portion that supplies power is composed of a multilayer wiring structure that is alternately arranged in the same layer.

Further, in the semiconductor device of the present invention,
Multilayer wiring structure in which a semiconductor element and a first conductor portion for supplying power and a second conductor portion for supplying ground power to the semiconductor element are alternately arranged in the same layer or in upper and lower layers. It is composed of the body and.

[0009]

According to the present invention, since the mutual coupling between the first and second conductor portions for supplying power to the semiconductor element can be increased by the means described above, the variation in the noise distribution in the same plane is smoothed. It is possible to do.

[0010]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 shows a PGA (Pi according to the present invention.
1 shows a schematic structure of a multi-layer ceramic package of n Grid Array type.

That is, this package includes, for example, a conductor layer portion 11, a wiring layer portion 12, and a large number of lead pins 1.
4 is arranged, is constituted by an upper layer portion 15 as a top layer on which the semiconductor chip 13 is mounted, and is formed by baking each layer portion in a laminated state.

The conductor layer portion 11 is composed of a plurality of power supply system conductors 21 for supplying power and ground power to the semiconductor chip 13, and these power supply system conductors 21 are laminated in multiple layers (for example, about 5 to 15 layers). It has been configured.

The power supply conductor 21 is formed by screen-printing a metal 21b such as tungsten (W) on an insulating layer 21a such as alumina (Al ₂ O ₃ ).
The metal 21b constitutes a power supply conductor 22a or a ground conductor 22b, which will be described later.

The wiring layer portion 12 is an insulating layer 1 such as alumina.
2a and a wiring layer 12b made of tungsten or the like are laminated in multiple layers. In this case, the upper layer 15
Each lead pin 14, each wiring layer 12b of the wiring layer portion 12,
The power supply conductor 22a and the ground conductor 22b, which are configured by the respective metals 21b of the conductor layer portion 11, are appropriately connected by through holes (not shown).

After packaging, the semiconductor chip 13 is mounted on the chip mounting position of the upper layer portion 15, and the pads of the chip 13 and the lead pins 14 are connected to each other by bonding wires (not shown). A PGA type multilayer ceramic package will be formed.

FIG. 2 shows an example of the structure of the power supply system conductor 21 in the conductor layer portion 11 described above. Power system conductor 2
Each of 1 is an insulating layer 2 in the same plane (layer).
A position of the metal 21b on 1a corresponding to, for example, a mounting position of the semiconductor chip 13 (a portion surrounded by a broken line in the drawing)
The portion excluding 13a is divided into eight by a groove or the like, and each conductive portion is alternately provided with the power supply conductor 22a and the ground conductor 22.
b and b.

In each of the upper and lower layers of the power supply system conductor 21, the power supply conductors 22a and the ground conductors 22b are arranged alternately. That is, the metal 21b of each power supply system conductor 21 is uniformly divided, and the power supply conductor 22a and the ground conductor 22b are regularly arranged so as to be adjacent to each other.

According to such a configuration, the power supply conductor 22a
Also, mutual coupling between the ground conductors 22b can be increased, and the noise distribution can be smoothed. Therefore, it is possible to reduce the ΔI noise during normal operation and easily prevent the noise generated in a certain output buffer in the semiconductor chip 13 from propagating to another buffer.

Next, another embodiment of the present invention will be described. FIG. 3 shows an example of the power supply system conductor 21 divided into 16 parts. Also in this case, similarly to the above-described embodiment, each of the power supply system conductors 21 has, for example, the semiconductor chip 13.
The portion of the metal 21b excluding the position (the portion surrounded by the broken line in the drawing) 13a corresponding to the mounting position of
It is divided.

In the same layer and in each of the upper and lower layers, the divided conductive portions are arranged so as to be alternately assigned to the power supply conductor 22a and the ground conductor 22b.

As described above, the mutual coupling between the power supply conductor for supplying power to the semiconductor chip and the ground conductor can be increased. That is, the power supply system conductors are divided, and different power supply systems are alternately arranged so that the potentials of the adjacent conductor portions are different. As a result, the effective inductance can be made small and can be equalized, so that it is possible to smooth the variation in the noise distribution in the same plane. Therefore, it becomes possible to reduce the ΔI noise during the normal operation and prevent the occurrence of malfunction.

Further, it is possible to easily prevent the propagation of noise between the output buffers in the semiconductor chip.
In the above embodiment, the case where the number of conductor divisions is 8 and 16 has been described, but the present invention is not limited to this, and the conductors may be divided into multiples of 2 that allow regular arrangement.

However, in order to increase the mutual coupling and reduce the inductance, it is preferable to divide into 8 to 64 in the same plane. Also,
The package is not limited to the multilayer ceramic package, but can be applied to, for example, a multilayer plastic package. Of course, various modifications can be made without departing from the scope of the invention.

[0024]

As described above in detail, according to the present invention, it is possible to provide a semiconductor device in which the effective inductance in the plane conductor can be made uniform and the maximum value of simultaneous switching noise can be reduced. .

[Brief description of drawings]

FIG. 1 is a sectional view showing a schematic configuration of a PGA type multilayer ceramic package according to an embodiment of the present invention.

FIG. 2 is a perspective view showing a configuration example of a power supply system conductor.

FIG. 3 is a perspective view showing a configuration example of a power supply system conductor according to another embodiment of the present invention.

FIG. 4 is a perspective view of a power supply system conductor shown for explaining the related art and its problems.

[Explanation of symbols]

11 ... Conductor layer part, 12 ... Wiring layer part, 13 ... Semiconductor chip, 14 ... Lead pin, 15 ... Upper layer part, 21 ... Power supply system conductor, 22a ... Power supply conductor, 22b ... Ground conductor.

Claims (2)

[Claims] 1. A multilayer wiring in which a semiconductor element and a first conductor portion for supplying power to the semiconductor element and a second conductor portion for supplying ground power are alternately arranged in the same layer. A semiconductor device comprising: a structure. 2. A semiconductor element, and a first conductor portion for supplying power and a second conductor portion for supplying ground power to the semiconductor element are alternately arranged in the same layer or in upper and lower layers. A semiconductor device comprising: