JP2976357B2 - Semiconductor integrated circuit device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION The present invention relates to a semiconductor integrated circuit device,
In particular, the present invention relates to a semiconductor integrated circuit device characterized by the arrangement of power supply bumps and signal bumps.

[0002]

2. Description of the Related Art In order to realize high integration of a semiconductor integrated circuit, instead of a method of forming a power supply bump and a signal bump around a semiconductor integrated circuit chip surrounding a cell area which has been widely used in the past, a semiconductor integrated circuit is used. A so-called area bump, which is not limited to the periphery of the circuit chip but forms a bump inside the circuit chip, has begun to be widely used in conjunction with a multi-pin package of a semiconductor integrated circuit device, high-density mounting, and the like. .

[0003]

However, a semiconductor integrated circuit device employing this area bump has not been designed with particular consideration given to the relationship between the arrangement of the area bumps and the size of the cells constituting the semiconductor integrated circuit. Because
The layout on the plane becomes irregular, and the total area required for arranging the power supply bumps and the signal bumps increases.
The distance between the power supply bump and the cell to which power is supplied from the bump becomes uneven and long, resulting in a large and non-uniform voltage drop in the wiring layer and a large power loss. Power supply was not efficient.

According to the present invention, cells such as gates are arranged in a matrix, and the relationship between the cell size and the pitch of power supply bumps and signal bumps, and the allocation of signal bumps and power supply bumps are optimized. It is an object of the present invention to provide a semiconductor integrated circuit device that efficiently supplies a semiconductor device.

[0005]

In a semiconductor integrated circuit device according to the present invention, power supply bumps and signal bumps are arranged in a matrix on an integrated circuit chip, and the pitch of these bumps is a cell constituting an integrated circuit. Is an integral multiple of the size in that direction, or (integer + 0.5).

In this case, a dual power supply system including a first power supply and a second power supply is employed, and a configuration is employed in which the first power supply bumps and the second power supply bumps are alternately arranged.

In this case, a dual power supply system consisting of a first power supply and a second power supply is employed, and the first power supply bumps are alternately arranged so that the second power supply bumps surround the cell region of the integrated circuit chip. The configuration of the arrangement is adopted.

Further, in this case, a three power supply system including a first power supply, a second power supply, and a third power supply is adopted, the first power supply bumps and the second power supply bumps are alternately arranged, and the third power supply is provided. A configuration in which the cell region of the integrated circuit chip is disposed so as to surround the cell region is employed.

Further, the first power supply bumps and the second power supply bumps are alternately arranged, and the first power supply upper wiring layer connected to the first power supply bumps and the second power supply bumps connected to the second power supply bumps. Each of the power supply upper wiring layers has a comb shape, and the teeth are alternately arranged so as to mesh with each other.

[0010]

According to the present invention, the pitch between the power supply bump and the signal bump is set on the basis of the cell size, and in one direction (vertical) of the integrated circuit chip, the bump pitch is set to the vertical size of the cell. (Integer + 0.5) times, and in the other direction (horizontal), the pitch of the bumps is set to an integral multiple of the horizontal size of the cell, and they are alternately arranged in a matrix on the integrated circuit chip. The total area required for bump formation can be minimized.

In one direction (longitudinal direction) of the integrated circuit chip, the bump pitch is set to be (integer + integer) of the vertical size of the cell.
0.5) times, a plurality of upper wiring layers connected to adjacent power supply bumps and extending in the horizontal direction with a cell size interval can be shifted from each other by 0.5 of the cell size. Both upper wiring layers can be arranged with a margin without causing a short circuit between them.

In another direction (lateral),
Since the pitch of the bumps is set to an integral multiple of the horizontal size of the cell, only a maximum of one cell of current can flow through each lower wiring layer, and the voltage drop due to the resistance of the lower wiring layer can be reduced. Can be evenly distributed, so that the wiring layer can be made thinner and the degree of integration can be improved. In addition, the bump pitch is made an integral multiple of the horizontal size of the cell to form a discontinuous portion that is vertically continuous with the lower wiring. Thereby, a region for forming the third power supply wiring layer and the wiring layer connected to the signal bump can be secured.

[0013]

FIG. 1 is a view for explaining the relationship between the arrangement of bumps and the cell size according to the first embodiment. In this figure, 1 is an integrated circuit chip, 2 is a cell, 3 is a first power supply bump, 4 is a second power supply bump, and 5 is a signal bump.

In this embodiment, the vertical pitch of the bumps is 1.5 of the cell size, and the horizontal pitch is 2 cells. In this embodiment, a first power supply bump (●) 3, a second power supply bump (×) 4, and a signal power supply are formed on an integrated circuit chip 1 on which cells 2 of a size subjected to cross hunting are integrated over the entire surface. Bump (◎) 5, the vertical pitch is 1.5 times the vertical size of the cell 2,
They are arranged in a matrix such that the horizontal pitch is twice the horizontal size of the cell 2.

In FIG. 1, the first power supply bumps 3 and the signal bumps 5 or the second power supply bumps 3 and the signal bumps 5 are alternately arranged in every other row and every other column. This arrangement is effective for connecting the shortest distance between each bump and each cell in the vicinity thereof.

FIG. 2 is a diagram showing the arrangement of the bumps and the upper wiring layer according to the first embodiment. In this figure, in addition to the above,
Reference numeral 6 denotes a first power supply upper wiring layer, and reference numeral 7 denotes a second power supply upper wiring layer.

In this embodiment, the first power supply upper wiring layer 6 is 1.5 か ら vertically from the first power supply bump.
It extends by a cell size, and extends 1.5 cell sizes from the center and both ends in the horizontal direction.

The second power supply upper wiring layer 7 similarly extends vertically 1.5 cell sizes from the second power supply bumps, and 1.5 cell size each horizontally from the center and both ends thereof. Extending. Then, from the tip of each upper wiring layer, it is connected to a lower wiring layer via a VIA formed in the interlayer insulating film.

FIG. 3 is a diagram showing the arrangement of the bumps and the lower wiring layers according to the first embodiment. In this figure, other than the above, 8 is a first power supply lower wiring layer, 9 is a second power supply lower wiring layer, and 10 is a VIA.

Each lower wiring layer 8 is connected to the end of the upper wiring layer via a central via (interlayer connection) 9. Then, from the tip of each lower wiring layer 8, it goes to the cell via the via of the interlayer insulating film.

FIG. 4 is an explanatory diagram of power supply to each cell of the first embodiment. The reference numerals used in this figure are as described above.

This figure is a combination of FIGS. 1 to 3, in which one first power supply bump 3 is used to supply all the power supplies of the nine cells 2 in the vicinity thereof and １ ／ of the six cells 2. And a path for supplying the second power in the same manner through another path.

As shown in this figure, the first power supply upper wiring layer 6 extends from the first power supply bump 3 by one cell length in the vertical and vertical directions, and extends in the horizontal direction from the center and the front end thereof. Each cell extends for the length of one cell.

The first power supply upper wiring layer 6 is connected to the first power supply lower wiring layer 8 through the VIA of the interlayer insulating film from each end of the first power supply upper wiring layer 6. From left to right and left and right by a half cell size.

Further, from each end of the first power supply lower wiring layer 8, the VIA of the interlayer insulating film is passed, and at this portion, power is supplied to an adjacent cell by 部分 of the required power of each cell. Therefore, the current supplied through the lower wiring layer does not exceed the current of one cell.

The width or cross-sectional area of the first power supply upper wiring layer 6 depends on the amount of current flowing.
It is set larger. According to the present embodiment, the power is supplied from the first power supply upper wiring layer 6 connected to the first power supply bump 3 to the first power supply lower wiring layer 8 and from the first power supply lower wiring layer 8 to each of the adjacent cells. Are sequentially branched and supplied, the voltage drop in each power supply wiring layer can be reduced and made uniform, and the power loss can be minimized.

The second power supply is configured in exactly the same manner as the first power supply. The second power supply is also configured so that the power supply is equally branched from the second power supply bump and flows to each cell. I have.

As described above, since the horizontal pitch of the first power supply bump, the second power supply bump, and the signal bump is set to twice the horizontal size of the cell, a wiring layer for supplying power to each cell is provided. Can be regularly arranged in relation to the cell size, the area required for forming these bumps can be minimized, and the first power supply lower wiring Since a space in which neither the layer 8 nor the second power supply lower wiring layer 9 exists can be left, when the three power supply system including the first power supply, the second power supply, and the third power supply is adopted, the third power supply bump is formed in the cell region. , And a third power supply can be supplied to each cell from the bump through the above-mentioned space.

Further, under the signal bump 5, a part for receiving the lower part is required, but an area therefor can be secured. Further, since the vertical bump pitch is set to 1.5 times the cell size, the first power supply upper wiring layer 6 and the second power supply upper wiring layer 7 for supplying power to each cell, and the first power supply A difference of 0.5 in the cell size occurs between the lower wiring layer 8 and the second power supply lower wiring layer 9, which is effective for preventing short circuit between the lower wiring layers and the manufacturing accuracy.

In this embodiment, the power supply bumps 3 and 4 which are alternately arranged are described as the first power supply bump and the second power supply bump. However, both are used as the first power supply bump and the second power supply bump. The bumps can also be arranged to surround the cell area of the integrated circuit chip.

(Second Embodiment) FIG. 5 is a diagram for explaining the relationship between the arrangement of bumps and the cell size in the second embodiment. In this figure, 11 is an integrated circuit chip, 12 is a cell, 13
Denotes a first power supply bump, 14 denotes a second power supply bump, and 15 denotes a signal bump.

In this embodiment, the vertical pitch of the bumps is
Is 2.5 times the vertical size and the horizontal pitch is 3 times the horizontal size of the cell 12. In the present embodiment, the first power supply bump, the second power supply bump 14, and the signal bump 15 are formed on the integrated circuit chip 11 on which the cell 12 is integrated, and the vertical pitch is 2.5 times the vertical size of the cell 12. The cells are arranged so that the horizontal pitch is three times the horizontal size of the cell 12.

FIG. 6 is a diagram showing the arrangement of bumps and upper wiring layers according to the second embodiment. In this figure, in addition to the above,
Reference numeral 16 denotes a first power supply upper wiring layer, and reference numeral 17 denotes a second power supply upper wiring layer.

In the present embodiment, the first power supply upper wiring layer 16 is
It extends by a cell size, and extends by 1.5 cell sizes in the lateral direction from the center and a point having a distance of one cell size from the center.

Similarly, the second power supply upper wiring layer 17 extends from the second power supply bump 14 up and down by two cell sizes, respectively, from the center thereof and from the point having an interval of one cell size from this center. Each cell extends 1.5 cell size in the horizontal direction. Then, from the tip of each upper wiring layer,
It is connected to a lower wiring layer via a VIA formed in the interlayer insulating film.

FIG. 7 is a diagram showing the arrangement of bumps and lower wiring layers according to the second embodiment. In this figure, in addition to the above,
Reference numeral 18 denotes a first power supply lower wiring layer, 19 denotes a second power supply lower wiring layer, and 20 denotes a via.

Each of the lower wiring layers 18 and 19 has a central V
It is connected to the tip of the upper wiring layer via IA20. The cells are connected to the cells from the tips of the lower wiring layers 18 and 19 via the vias of the interlayer insulating film.

FIG. 8 is an explanatory diagram of power supply to each cell of the second embodiment. The reference numerals used in this figure are as described above. This figure is a combination of FIG. 5 to FIG. 7, in which a single first power supply bump 13 supplies all power supplies of 25 cells 12 in the vicinity thereof, and 1/10 of 10 cells 12.
2 is a diagram for describing a path for supplying the second power and supplying the second power in the same manner via another path.

As shown in this figure, the first power supply upper wiring layer 16 extends from the first power supply bump 13 by two cell lengths in the vertical and vertical directions, and has a center and one cell size from the center. Each cell extends in the horizontal direction from left to right by a length of 1.5 cell sizes.

Then, the first power supply upper wiring layer 16 is connected to the first power supply lower wiring layer 18 through the VIA of the interlayer insulating film from each end of the first power supply upper wiring layer 16, and the first power supply lower wiring layer 8 is moved right and left from the connection point. In the direction of each cell.

Further, the first power supply lower wiring layer 18
Through the VIA of the interlayer insulating film from the center and each end, and supplies half of the required power of each cell to adjacent cells at this portion.

Further, the second power supply is configured in exactly the same manner as the first power supply. As described above, since the horizontal pitch of the first power supply bump, the second power supply bump, and the signal bump is set to be three times the horizontal size of the cell, the bumps are formed as described in the first embodiment. Since the area required for formation can be minimized and a space in which the lower wiring layer does not exist can be left in the vertical region where the signal bump 5 exists, the third power supply A third power supply can be supplied to each cell through the area that has become the above space from the bump, and a region for receiving the signal bump 15 is secured. be able to.

Also, since the vertical bump pitch is set to 2.5 times the cell size, between the first power supply upper wiring layer 16 and the second power supply upper wiring layer 17 for supplying power to each cell, and A difference of セ ル of the cell size is generated between the first power supply lower wiring layer 18 and the second power supply wiring layer 19, which is effective in preventing a short circuit between the first power supply wiring layer 18 and the manufacturing power supply. .

In this embodiment, the number of the first power supply bumps 18 and the second power supply bumps 19 per cell can be reduced as compared with the first embodiment, but the density of the signal pads 15 also increases. Since the number of bumps is reduced, the number of times the bump pitch is made to be larger than the cell size is appropriately selected depending on the configuration of the integrated circuit.

(Third Embodiment) FIG. 9 is a view for explaining the arrangement of bumps and upper wiring layers according to a third embodiment. In this figure, 21 is a first power supply bump, 22 is a second power supply bump, 23 is a signal bump, 24 is a first power supply upper wiring layer,
Reference numeral 25 denotes a second power supply upper wiring layer, and reference numeral 26 denotes a cell.

In this embodiment, the vertical pitch of the bumps is 2.5 times the cell size, and the horizontal pitch is 3 times the cell size. The first power supply upper wiring layer 24 has a comb-like shape in which the second power supply upper wiring layer 25 has a tooth pitch of 0.5 times the cell size, and is arranged so that the teeth alternately mesh with each other. .

FIG. 10 is a diagram for explaining the arrangement of the upper wiring layer and the lower wiring layer in the third embodiment. In this figure, in addition to the above, 27 is a first power supply lower wiring layer, 28 is a second power supply lower wiring layer, 29 is a signal VIA, and 30 is a third power supply wiring layer.

The first power supply upper wiring layer 24 and the second power supply upper wiring layer 24 shown in FIG.
As is evident from the portion where the part of the power supply upper wiring layer 25 (see FIG. 9) is overlapped, the first power supply lower wiring layer 27 and the second power supply lower wiring layer 28 Since the upper wiring layer 24 and the second power supply upper wiring layer 25 face each other via an interlayer insulating film over a wide area, a wide VIA or a plurality of VIs are formed in a region where both of them face each other.
By forming A, it is possible to obtain a low-resistance connection therebetween. It goes without saying that this embodiment has the effects described in the first embodiment and the second embodiment.

[0049]

As described above, according to the present invention,
By setting the pitch size of the power supply bump or signal bump based on the cell size and the shape of the wiring layer connected to the power supply bump, the voltage drop due to the resistance of the wiring layer can be minimized. In addition, since it is possible to supply a stable power supply to each cell even if the width of the wiring layer is reduced as a result of uniformity, it greatly contributes to the technical field related to a high-density integrated circuit device.

[Brief description of the drawings]

FIG. 1 is a diagram illustrating the relationship between the arrangement of bumps and the cell size according to a first embodiment.

FIG. 2 is a diagram illustrating an arrangement of bumps and an upper wiring layer according to the first embodiment.

FIG. 3 is a diagram showing an arrangement of bumps and lower wiring layers according to the first embodiment.

FIG. 4 is an explanatory diagram of power supply to each cell of the first embodiment.

FIG. 5 is a diagram illustrating the relationship between the arrangement of bumps and the cell size according to the second embodiment.

FIG. 6 is a diagram showing an arrangement of bumps and upper wiring layers according to a second embodiment.

FIG. 7 is a diagram showing the arrangement of bumps and lower wiring layers according to a second embodiment.

FIG. 8 is an explanatory diagram of power supply to each cell of the second embodiment.

FIG. 9 is a diagram illustrating the arrangement of bumps and upper wiring layers according to a third embodiment.

FIG. 10 is a diagram illustrating an arrangement of an upper wiring layer and a lower wiring layer according to a third embodiment;

[Explanation of symbols]

 1,11 Integrated circuit chip 2,12,26 Cell 3,13,21 First power supply bump 4,14,22 Second power supply bump 5,15,23 Signal bump 6,16,24 First power supply upper layer wiring Layers 7, 17, 25 Second power supply upper wiring layer 8, 18, 27 First power supply lower wiring layer 9, 19, 28 Second power supply lower wiring layer 10, 20 VIA 29 Signal VIA 30 Third power supply wiring layer

Claims (6)

(57) [Claims] The power supply bumps are arranged in a matrix on an integrated circuit chip, and the power supply bumps are arranged beside the arranged power supply bumps.
The horizontal or vertical spacing is the side of the cell that constitutes the integrated circuit
A semiconductor integrated circuit device which is an integral multiple of a vertical size or a vertical size . 2. The power supply bumps are arranged in a matrix on an integrated circuit chip, and the power supply bumps are arranged beside the arranged power supply bumps.
The horizontal or vertical spacing is the side of the cell that constitutes the integrated circuit
In the direction size or (integer + 0.5) times the size in the vertical direction
The semiconductor integrated circuit device, characterized in that there. 3. A dual power supply employed including the first and second power supplies, according to claim 1 or a first power source bump and a second power supply bumps is characterized in that it is arranged alternately The semiconductor integrated circuit device according to claim 2. 4. A dual power supply system comprising a first power supply and a second power supply, wherein the first power supply bump is a cell of an integrated circuit chip.
3. The semiconductor integrated circuit device according to claim 1 , wherein the second power supply bumps are arranged in a matrix on the region, and the second power supply bumps are arranged to surround a cell region of the integrated circuit chip. 5. A three power source system comprising a first power source, a second power source, and a third power source, wherein the first power source bumps and the second power source bumps are alternately arranged on the cell region of the integrated circuit chip. And a third power supply bump is arranged so as to surround a cell region of the integrated circuit chip.
Or a semiconductor integrated circuit device according to claim 2. 6. A first power supply bump and a second power supply bump are alternately arranged, and a first power supply upper wiring layer connected to the first power supply bump and a second power supply connected to the second power supply bump. 3. The semiconductor integrated circuit device according to claim 1, wherein each of the upper wiring layers has a comb shape, and the teeth are alternately meshed with each other.