JP4280179B2 - Multilayer semiconductor device - Google Patents

Description

  The present invention relates to a semiconductor device, and more particularly to a stacked semiconductor device formed by stacking a plurality of semiconductor chips.

  In recent years, with the improvement in performance of semiconductor devices, stacked semiconductor devices in which a plurality of semiconductor chips are stacked have become widespread.

  FIG. 1 is a cross-sectional view schematically showing a conventional stacked semiconductor device. Referring to FIG. 1, a stacked semiconductor device 100 is installed on a mother substrate M0 through electrical connection via bumps B0, and a plurality of semiconductor chips 101 held by a plurality of carriers 102 are provided. It has a laminated structure.

  The plurality of carriers 102 are provided with a signal line S0, a power supply line P0, and a ground line G0, and are connected to terminals of a semiconductor chip held by each carrier.

  In such a stacked semiconductor device, the stacked semiconductor chips have been increased in speed and power consumption, and when the load impedance of the semiconductor device changes rapidly, the fluctuation of the power supply voltage is suppressed and the switching noise is reduced. It is necessary to reduce the frequency and stabilize the operation in the high frequency region.

In conventional high-speed semiconductor chips, a decoupling capacitor (sometimes called a decoupling capacitor or bypass capacitor) is installed near the semiconductor chip for the purpose of reducing power supply noise such as fluctuations in power supply voltage. In some cases, a method of reducing high-frequency power supply noise such as switching noise is employed.
JP-A-8-236694 JP-A-11-251515 JP 11-260999 A

  However, in the case of the stacked semiconductor device as described above, there is a problem that it is difficult to secure a space for installing a decoupling capacitor (hereinafter referred to as a capacitor in the text) near the semiconductor chip. For example, when a capacitor is installed on the mother board, the wiring to the semiconductor chip becomes long, and thus the effect of reducing power supply noise by the capacitor may be reduced due to the influence of inductance generated by the wiring.

  In addition, when a capacitor is installed on the mother board, there is a problem that it is difficult to eliminate the influence of noise caused by the semiconductor chip formed in the lower layer of the stacked semiconductor device on the upper semiconductor chip. In particular, when a digital chip with a large amount of switching noise is installed in the lower layer, there is a problem that the influence of the switching noise on the analog chip in the upper layer becomes large and the operation becomes unstable.

  Accordingly, an object of the present invention is to provide a new and useful stacked semiconductor device that solves the above problems.

  A specific object of the present invention is to provide a stacked semiconductor device that is stable in operation with reduced influence of power supply noise.

  The present invention provides a stacked semiconductor device having the above-described problems, comprising a plurality of stacked semiconductor chips and a capacitor formed so as to be sandwiched between the plurality of semiconductor chips, wherein the capacitor is formed into a film shape. This is solved by a stacked semiconductor device that is formed and inserted between the plurality of semiconductor chips.

  According to the present invention, the multilayer semiconductor device has a stable operation with reduced influence of power supply noise by forming a capacitor so as to be stretched in a film shape so as to be sandwiched between a plurality of semiconductor chips. A semiconductor device can be provided.

  Further, the capacitor is a parallel plate type capacitor having a first electrode and a second electrode, and being held so that a dielectric layer is sandwiched between the first electrode and the second electrode. A capacitor can be formed in a space-saving manner, which is preferable.

  In addition, when the first electrode is connected to the power line of the semiconductor chip and the second electrode is connected to the ground line of the semiconductor chip, it is possible to reduce power noise entering the semiconductor chip, Is preferred.

  In addition, when the via plug wiring penetrating from the first electrode side to the second electrode side is provided in the dielectric layer, the wiring structure of the stacked semiconductor device penetrating the capacitor is provided. It can be formed and is preferable.

  The capacitor includes a center conductor, a dielectric layer formed around the center conductor, and a grounded outer conductor formed around the dielectric layer. When the power supply line of the semiconductor chip is connected, it is possible to reduce the inductance of the capacitor and effectively reduce the power supply noise in the high frequency region.

  Of the plurality of semiconductor chips, when the capacitor is formed in the power supply line between the first semiconductor chip and the second semiconductor chip so that the central conductor is connected in series, the first semiconductor chip It is possible to reduce the influence of the noise caused on the second semiconductor chip, which is preferable.

  In addition, it is preferable that a plurality of capacitors be alternately inserted between the plurality of semiconductor chips, because it is possible to reduce power supply noise of the plurality of semiconductor chips.

  The plurality of semiconductor chips may be held by a plurality of carriers, and the capacitor may be formed so as to be sandwiched between the plurality of carriers.

  According to the present invention, it is possible to provide a stacked semiconductor device with stable operation with reduced influence of power supply noise.

  Next, embodiments of the present invention will be described with reference to the drawings.

  FIG. 2 is a cross-sectional view schematically showing the stacked semiconductor device 10 according to the first embodiment of the present invention.

  Referring to FIG. 2, the stacked semiconductor device 10 is schematically shown in which a semiconductor structure 13b made of a semiconductor chip 11b held by a carrier 12b is stacked on a semiconductor structure 13a made of a semiconductor chip 11a held by a carrier 12a. Further, a semiconductor structure 13c composed of the semiconductor chip 11c held by the carrier 12c is laminated on the semiconductor structure 13b.

  In the semiconductor structures 13a, 13b and 13c, a signal line S1, a power supply line P1 and a ground line G1 are formed so as to pass through the carriers 12a, 12b and 12c.

  The stacked semiconductor 10 is installed on the mother substrate M1, and the wiring on the mother substrate M1 is electrically connected to the signal line S1, the power supply line P1, and the ground line G1 through bumps B1, respectively. Has been. Further, the terminals of the semiconductor chips 11a, 11b and 11c are electrically connected to the signal line S1, the power supply line P1 and the ground line G1 formed in the carriers 12a, 12b and 12c, respectively. In the figure, only the wiring from the ground line G1 to the semiconductor chip is shown, and the wiring from the power supply line and the signal line to the semiconductor chip is not shown.

  In the stacked semiconductor device 10 according to the present embodiment, a capacitor 17 for removing power supply noise is formed and inserted between stacked semiconductor chips so as to be sandwiched between the semiconductor chips.

  Therefore, in the stacked semiconductor device according to the present embodiment, the influence of power supply noise can be reduced, and the stacked semiconductor device is stable in operation.

  For example, when noise reduction is performed using a chip capacitor as in the past, the thickness of the chip capacitor is inevitable, so that it is inevitable that the stacked semiconductor device will be enlarged when inserted between semiconductor chips. Therefore, it has been difficult to mount the chip capacitor on the stacked semiconductor device.

  On the other hand, in the case of the present embodiment, by inserting a film-like capacitor so as to be sandwiched between semiconductor chips, it becomes possible to install the capacitor in a space-saving manner, and the size of the stacked semiconductor device equipped with the capacitor can be reduced. There is an effect that can be made thinner and thinner.

  Further, the semiconductor chip is not limited to the case shown in this embodiment, and may have various shapes and structures, and may have an insulator structure around the semiconductor chip. The semiconductor structure is sometimes called a semiconductor chip.

  As such a thin capacitor, for example, as shown in the present embodiment, it is preferable to use a parallel plate type capacitor 17 in which a dielectric layer 16 is held between a lower electrode 14 and an upper electrode 15. By forming the lower electrode 14, the upper electrode 15 and the dielectric layer 16 in a thin film shape, the entire capacitor can be formed thin, and a capacitor that can be installed in a space-saving space between semiconductor chips is formed. can do.

  The capacitor 17 is inserted between the semiconductor structures 13a and 13b and between the semiconductor structures 13b and 13c. The lower electrode 14 of the capacitor 17 is connected to the power supply line P1. The upper electrode 15 is connected to the ground line G1.

  Next, FIG. 3 schematically shows a circuit of the stacked semiconductor device 10 in which the capacitor 17 is installed. Referring to FIG. 3, the power supply line P1 between the semiconductor chips 11a and 11b is connected to the ground line G1 between the semiconductor chips 11a and 11b via the capacitor 17. Therefore, for example, noise components such as switching noise generated in the semiconductor chip 11a are discharged from the power supply line P1 to the ground line G1 via the capacitor 17, thereby reducing the influence of power supply noise on the semiconductor chip 11b. It becomes possible to do.

  Similarly, the power supply line P1 between the semiconductor chips 11b and 11c is connected to the ground line G1 between the semiconductor chips 11b and 11c via the capacitor 17. Therefore, for example, noise components such as switching noise generated in the semiconductor chip 11b are discharged from the power supply line P1 to the ground line G1 through the capacitor 17, thereby reducing the influence of power supply noise on the semiconductor chip 11c. It becomes possible to do.

  As described above, it is preferable that a plurality of the capacitors 17 are alternately inserted between the plurality of semiconductor chips because the power source noise of the plurality of semiconductor chips can be reduced.

  In addition, in the case of such a stacked semiconductor device, a large amount of noise is generated. For example, if a digital chip is installed in a higher layer, the number of chips that may be affected by the digital chip is reduced. Is preferable.

  Next, details of the capacitor 17 will be described with reference to FIGS. 4 to 5A and 5B.

  4 is a diagram schematically showing details of the cross section of the capacitor 17, FIG. 5 (A) is a plan view seen from the X direction of FIG. 4, and FIG. 5 (B) is a plan view seen from the Y direction of FIG. The figure is shown schematically. However, in the figure, the same reference numerals are given to the parts described above, and the description will be omitted. 5A and 5B are views in a state where a solder resist described later is removed.

  4 and FIGS. 5A and 5B, the lower electrode 14 and the upper electrode 15 of the capacitor 17 are covered with a solder resist 18 to be insulated and protected. ing.

  The capacitor 17 is configured by forming an upper electrode and a lower electrode on the dielectric layer 16 made of a resin film in which a high dielectric filler such as barium titanate is contained in a resin such as polyimide or epoxy. .

  The dielectric layer 16 has via plug wirings 19a, 19b and 19c penetrating the dielectric layer 16 from the first side where the lower electrode is formed to the second side where the upper electrode is formed. On the dielectric layer 16, connection electrodes that are electrically connected to the via plug wirings 19 a, 19 b, and 19 c are formed. Moreover, the hole part for exposing a connection electrode is formed in the part corresponding to each connection electrode of the said soldering resist 18. As shown in FIG.

  A connection electrode 20a is formed on the first side of the via plug wiring 19a, and a connection electrode 21a is formed on the second side facing the connection electrode 20a with the dielectric layer 16 in between. The ground electrode G1 is connected to the connection electrode 20a, and the upper electrode 15 is electrically connected to the connection electrode 21a. The connection electrode 21a is connected to a ground line of a semiconductor structure formed in an upper layer of the connection electrode 21a.

  Further, a connection electrode 20b is formed on the first side of the via plug wiring 19b, and a connection electrode 21b is formed on the second side opposite to the connection electrode 20b with the dielectric layer 16 in between. Yes. The lower electrode 14 is electrically connected to the connection electrode 20b, and a power supply line of a semiconductor structure formed in an upper layer of the connection electrode 21b is connected to the connection electrode 21b.

  Further, a connection electrode 20c is formed on the first side of the via plug wiring 19c, and a connection electrode 21c is formed on the second side opposite to the connection electrode 20c with the dielectric layer 16 in between. Yes. A signal line is electrically connected to the connection electrodes 20c and 21c, and an upper layer and a lower layer signal line are connected via the via plug wiring 19c.

  As described above, by forming via plug wiring in the dielectric layer 16, it is possible to form a wiring structure of a stacked semiconductor device having a structure in which a capacitor and a semiconductor chip are stacked.

  Further, the capacitor according to this embodiment can be applied, for example, when the semiconductor structure or the semiconductor chip is one layer, and can be inserted between the mother substrate and the semiconductor structure or the semiconductor chip.

  Further, for example, the lower electrode 14 and the upper electrode 15 are made of copper, aluminum, or nickel, and the dielectric layer 16 is made of any of high dielectric constant resin, tantalum oxide, aluminum oxide, or barium titanate. Although it is possible to form more, it is not specifically limited to these materials.

  Further, for example, the lower electrode 14 and the upper electrode 15 are preferably formed to a thickness of about 10 μm to 30 μm, and the dielectric layer 16 is preferably formed to a thickness of about 10 nm to 20 μm. It is not a thing.

  As the carriers 12a, 12b and 12c used in this embodiment, various packages such as T-BGA (tape ball grid array) and P-BGA (plastic ball grid array) are used. Is possible.

  Further, for example, in order to reduce the parasitic capacitance between the via plug wirings, capacitors and via plug wirings may be formed as shown in FIG.

  FIG. 6 shows a modification of the capacitor 17. However, in the figure, the same reference numerals are given to the parts described above, and the description will be omitted.

  Referring to FIG. 6, in the case shown in FIG. 6, a capacitor 17A including an upper electrode 14, an upper electrode 15, and a dielectric layer 16 is formed on a base film 16A that supports the capacitor 17A.

  In this case, most of the via plug wirings 19a to 19c have a structure penetrating through the base film 16A, and the base film 16A is made of a material having a low dielectric constant (for example, polyimide film, film thickness of about 30 μm). Is used, it is possible to reduce the parasitic capacitance between the via plug lines and to suppress the occurrence of crosstalk between the via plug lines.

  The capacitor connected to the semiconductor chip is not limited to the capacitor 17 described in the present embodiment, and can be variously modified and changed as shown below, for example.

  FIG. 7 is a cross-sectional view schematically showing a stacked semiconductor device 30 according to the second embodiment of the present invention. However, in the figure, the same reference numerals are given to the parts described above, and the description will be omitted. The present embodiment is different from the first embodiment in the following points, and has the effects described below in addition to the same effects as those described in the first embodiment.

  Referring to FIG. 7, in the stacked semiconductor device 30 shown in FIG. 7, a capacitor inserted between semiconductor chips includes a center conductor 32, a dielectric layer 33 formed around the center conductor 32, and An outer conductor 31 formed around the dielectric layer 33 and connected to the ground line G1; the central conductor 32 is connected to the power supply line P1 of the semiconductor chip, and the power supply voltage of the semiconductor chip Is applied through the center conductor P1, and a so-called transmission path type capacitor is used as the capacitor 34 for noise reduction.

  Therefore, there is an effect that the inductance of the capacitor can be reduced to effectively reduce the power supply noise in the high frequency region.

  For example, in a semiconductor chip that operates at high speed, the generated noise has a high frequency, and the inductance component of the formed capacitor may be a problem for such a high-frequency noise. That is, with respect to a noise component having a high frequency equal to or higher than the resonance frequency of the capacitor, the conventional capacitor may have a high impedance at the high frequency, and the effect of reducing the high frequency noise may be insufficient.

  In the present embodiment, as described above, by using the transmission path type capacitor 34, the inductance of the capacitor 34 is reduced, and the noise reduction effect particularly for high frequency noise is increased.

  Further, since the central conductor 32, the dielectric layer 33, and the outer conductor 32 are formed in a substantially thin film shape, it is possible to insert a film-like capacitor so that the capacitor is sandwiched between the semiconductor chips, thereby saving the space. As in the case of the first embodiment, there is an effect that the stacked semiconductor device on which the capacitor is mounted can be reduced in size and thickness.

  Further, the first end portion side of the center conductor 32 is connected to a power supply line P1 supplied from a semiconductor structure disposed below the center conductor 32, and is opposite to the first end portion side. The second end of the central conductor is connected to the power supply line P1 supplied to the semiconductor structure disposed in the upper layer of the central conductor 32. Thus, the transmission path is For this purpose, the inductance of the capacitor is reduced to increase the high-frequency noise reduction effect.

  FIG. 8 is a diagram schematically showing a circuit of the stacked semiconductor device 30 in which the capacitor 34 is installed. However, in the figure, the same reference numerals are given to the parts described above, and the description will be omitted.

  Referring to FIG. 8, a center conductor 32 of the capacitor 34 is connected to be connected in series to a power supply line between a plurality of semiconductor chips, and the outer conductor 31 is connected to a ground line. Yes. For example, the central conductor 32 is connected to the power supply line P1 between the semiconductor chips 11a and 11b so as to be inserted in series, and the outer conductor 31 is a ground line between the semiconductor chips 11a and 11b. Connected to G1. Therefore, for example, noise components such as switching noise generated in the semiconductor chip 11a are discharged from the power supply line P1 to the ground line G1 through the capacitor 34, thereby reducing the influence of power supply noise on the semiconductor chip 11b. It becomes possible to do.

  Similarly, the central conductor 32 is connected to the power supply line P1 between the semiconductor chips 11b and 11c so as to be inserted in series, and the outer conductor 31 is grounded between the semiconductor chips 11b and 11c. Connected to line G1. Therefore, for example, noise components such as switching noise generated in the semiconductor chip 11b are discharged from the power supply line P1 to the ground line G1 through the capacitor 34, thereby reducing the influence of power supply noise on the semiconductor chip 11c. It becomes possible to do.

  Thus, when a plurality of capacitors 34 are inserted between a plurality of semiconductor chips, it is possible to reduce power source noise of the plurality of semiconductor chips, respectively. It is the same.

  Next, details of the capacitor 34 will be described with reference to FIGS.

  FIG. 9A is a diagram schematically showing details of the cross section of the capacitor 34, and FIG. 8B is a cross-sectional view taken along line AA of FIG. 9A. However, in the figure, the same reference numerals are given to the parts described above, and the description will be omitted.

  Referring to FIGS. 9A and 9B, the capacitor 34 has a structure in which the whole is covered with a solder resist 35 and insulated and protected.

  The capacitor 34 can be formed as follows, for example.

  First, a copper foil or a copper plate serving as the central conductor 32 is prepared, a tantalum layer is formed on the surface of the copper foil or copper plate by sputtering, and the tantalum layer is anodized to form the dielectric layer 33. Next, the surface of the dielectric layer 33 is covered with copper plating, the outer conductor 31 is formed, and the capacitor 34 can be formed.

  In the above case, an aluminum foil or an aluminum plate may be used as the central conductor, and the dielectric layer may be formed by anodizing the aluminum foil or the aluminum plate.

  The solder resist 35 on the first end side of the center conductor 32 is connected to the power supply line P1 supplied from the semiconductor structure disposed below the center conductor 32. A hole 36a is formed for this purpose. The solder resist 35 on the second end side of the center conductor 32 is connected to the power supply line P1 that supplies the center conductor 32 to the semiconductor structure disposed in the upper layer of the center conductor 32. For this purpose, a hole 37b is formed.

  Similarly, holes 36b and 37a for connecting the outer conductor 31 to the ground line G1 are formed on the first end side and the second end side of the solder resist, respectively. Yes.

  As described above, by forming the transmission path type capacitor 34 in a film shape, it is possible to mount the transmission path type capacitor 34 on the stacked semiconductor device, and the influence of the high frequency noise generated from the semiconductor chip on other semiconductor chips is reduced. Thus, the effect of stabilizing the operation of the stacked semiconductor device operating at a high speed is exhibited.

  Further, for example, the center conductor 32 and the outer conductor 31 are made of copper, aluminum, or nickel, and the dielectric layer 33 is made of any of high dielectric constant resin, tantalum oxide, aluminum oxide, or barium titanate. However, it is not particularly limited to these materials.

  For example, the central conductor 32 is preferably formed to a thickness of about 10 μm to 30 μm, the outer conductor 31 is preferably formed to a thickness of about 10 μm to 30 μm, and the dielectric layer 33 is preferably formed to a thickness of about 10 nm to 20 μm. It is not limited to the numerical value of.

  Although the present invention has been described with reference to the preferred embodiments, the present invention is not limited to the specific embodiments described above, and various modifications and changes can be made within the scope described in the claims.

  According to the present invention, it is possible to provide a stacked semiconductor device with stable operation with reduced influence of power supply noise.

It is sectional drawing which showed the conventional laminated semiconductor device typically. 1 is a cross-sectional view schematically showing a stacked semiconductor device according to Example 1. FIG. FIG. 3 is a diagram schematically showing a circuit of the stacked semiconductor device of FIG. 2. It is the figure which showed typically the cross section of the capacitor used for the laminated semiconductor device of FIG. (A), (B) is a top view of the capacitor of FIG. It is the figure which showed the modification of the capacitor of FIG. 6 is a cross-sectional view schematically showing a stacked semiconductor device according to Example 2. FIG. FIG. 7 is a diagram schematically showing a circuit of the stacked semiconductor device of FIG. 6. (A), (B) is the figure which showed typically the cross section of the capacitor used for the laminated semiconductor device of FIG.

Explanation of symbols

10, 30, 100 Stacked semiconductor device 11a, 11b, 11c, 101 Semiconductor chip 12a, 12b, 12c, 102 Carrier 13a, 13b, 13c Semiconductor structure 14 Lower electrode 15 Upper electrode 16 Dielectric layer 16A Base film 17 Capacitor 18 Solder Resist 19a, 19b, 19c Via plug wiring 20a, 20b, 20c, 21a, 21b, 21c Connection electrode 31 Outer conductor 32 Center conductor 33 Dielectric layer 34 Capacitor 35 Solder resist 36a, 36b, 37a, 37b Hole M0, M1 Mother board S0, S1 Signal wiring P0, P1 Power supply wiring G0, G1 Ground wiring B0, B1 Bump

Claims (3)

A stacked semiconductor device having a plurality of stacked semiconductor chips and a capacitor formed so as to be sandwiched between the plurality of semiconductor chips,
The capacitor is inserted between the plurality of semiconductor chips are formed into a film,
The capacitor is formed on a surface of the dielectric layer located opposite to the surface of the dielectric layer formed on the center conductor, the dielectric layer formed on both surfaces of the center conductor, and the surface of the dielectric layer in contact with the center conductor. And a grounded outer conductor, and
The outer conductor is electrically connected to a ground line of the semiconductor chip facing the outer conductor;
The central conductor protrudes from the end face of the dielectric layer in a direction orthogonal to the thickness direction of the dielectric layer, faces the power line of the semiconductor chip, and sandwiches the capacitor A stacked semiconductor device characterized by being connected in series with a power supply line of a chip. 2. The stacked semiconductor device according to claim 1 , wherein a plurality of the capacitors are alternately inserted between the plurality of semiconductor chips. Wherein the plurality of semiconductor chips are held by the plurality of carriers, the capacitor, the plurality of formed so as to be sandwiched between the carrier and wherein the has claim 1 or 2 SL placing the stacked semiconductor device.

Images