JP5153364B2 - Stacked semiconductor package and electronic device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a stacked semiconductor package, in which the power bounce caused by inductance is reduced without increasing the mounting area. <P>SOLUTION: In a stacked semiconductor package 1 consisting of multiple stacked semiconductor package elements, power wires and grounding wires of adjacent semiconductor package elements are respectively connected together by connection conductors 4, and connection conductors 4 for connecting power wires and those for connecting grounding wires are alternately arranged. The capacitance between a connection conductor 4 for connecting power wires and that for connecting grounding wires acts as decoupling capacitance that prevents the power bounce. <P>COPYRIGHT: (C)2009,JPO&amp;INPIT

Description

  The present invention relates to a stacked semiconductor package in which at least two semiconductor packages on which semiconductor elements are mounted are stacked, and an electronic device using the stacked semiconductor package.

  2. Description of the Related Art In recent years, development of a semiconductor package in which electronic components such as semiconductor elements are mounted at high density has been actively carried out in response to high integration due to miniaturization and high functionality of electronic devices. For example, a BGA (Ball Grid Array) package or CSP (Chip Scale Package) having lands in a grid shape is employed. In order to cope with higher density, a stacked type semiconductor package called POP (Package On Package) in which a plurality of semiconductor packages are stacked one above the other and integrated is increasingly used.

  However, in the POP structure, the semiconductor package on which the semiconductor element is mounted is three-dimensionally connected, so that the semiconductor element mounted on the package existing in the upper layer is connected via the lower-layer semiconductor package. The number of connection points increases and the connection distance also increases. Therefore, the fluctuation of the inductance of the power supply path becomes large, the power bounce occurs, and the stable signal quality cannot be maintained.

Here, the power bounce means that a back electromotive voltage is generated by the inductance component and the voltage of the power supply line fluctuates. As a solution to this, as shown in FIG. 5, the power supply path to the semiconductor element 105b existing above the second-stage semiconductor package 102b is directly connected to the printed circuit board 108 via the solder balls 104a and 104b. A method for reducing the number of connection points has been proposed (for example, Patent Document 1).
JP 2006-295136 A

  However, the conventional method has a problem that the size of the second-stage semiconductor package 102b is larger than that of the first-stage semiconductor package 102a, and the entire mounting area of the stacked semiconductor package 101 is increased. Furthermore, in the stacked semiconductor package 101, since the distance between the semiconductor elements 105a and 105b is short, heat stays in the space between the semiconductor elements 105a and 105b, and if the heat stays significantly, the semiconductor elements 105a and 105b There is a problem of causing malfunction.

  The present invention has been devised to solve the above-described problems, and an object of the present invention is to provide a package that reduces power bounce and supplies stable signal quality without increasing the mounting area. It is in.

The stacked semiconductor package according to the present invention is a stacked semiconductor package in which a plurality of semiconductor packages are stacked, and power supply wirings and ground wirings of adjacent semiconductor packages are connected by a connection conductor, A plurality of connection conductors for ground wiring connection are arranged alternately, the connection conductors are strip-shaped, and are arranged so that the long sides of the strip-shaped connection conductors are positioned vertically and face each other vertically . A plurality of the long sides are connected to the power supply wirings or the grounding wirings of the semiconductor package adjacent to each other , and a plurality of the connection conductors for connecting the power supply wirings and the surfaces of the connection conductors for connecting the grounding wirings face each other. It is characterized by being.

  Preferably, in the stacked semiconductor package of the present invention, the connection conductor is formed by welding a low melting point solder around a metal bump.

  Preferably, in the stacked semiconductor package of the present invention, the connection conductor is surrounded by a resin having a high dielectric constant.

  Preferably, in the stacked semiconductor package of the present invention, the connection conductor has a strip shape, and the power supply wirings or the grounding wirings of the semiconductor packages adjacent to each other are connected by the long sides facing each other and for connecting the power supply wirings. A plurality of the connection conductors and the surface of the connection conductor for ground wiring connection are arranged so as to face each other.

  Preferably, in the stacked semiconductor package of the present invention, two metal plates are arranged in parallel between the surfaces of the semiconductor packages between the adjacent semiconductor packages, and the metal plates are connected to the power supply wiring. It is connected to the connection conductor for connection and the connection conductor for ground wiring connection, respectively.

  Preferably, in the stacked semiconductor package of the present invention, a resin having a high dielectric constant is disposed between the metal plates.

  The electronic device of the present invention is formed by mounting an electronic component including a semiconductor element on the stacked semiconductor package of the present invention.

  According to the stacked semiconductor package of the present invention, the power supply wirings and the grounding wirings of adjacent semiconductor packages are connected by the connection conductors, and a plurality of connection conductors for power supply wiring connection and ground wiring connection are arranged alternately. As a result, a capacitance can be provided between the connection conductor for connecting the power supply wiring and the connection conductor for connecting the ground wiring, and charge can be supplied from this capacitance to the semiconductor element. The route becomes shorter. As a result, the voltage fluctuation due to the inductance accompanying the power supply path, that is, the power bounce can be reduced.

  In the stacked semiconductor package of the present invention, when the connection conductor is formed by welding a low melting point solder around the metal bump, the low melting point solder liquefied when reflowing is passed around the metal bump. Surrounding, cylindrical connection conductors are formed, and the columnar shape has the same height as the metal bump diameter, so the capacitance between the connection conductors is constant while keeping the distance between the semiconductor packages constant. It can be.

  Further, in the stacked semiconductor package of the present invention, when the connection conductor is surrounded by a resin having a high dielectric constant, the resin has a relative dielectric constant larger than that of air. It can be enlarged. Therefore, power bounce can be reduced.

  In the stacked semiconductor package of the present invention, the connection conductor has a strip shape, and the power supply wirings or grounding wirings of adjacent semiconductor packages are connected by the long sides facing each other, and the connection conductor and grounding wiring for connecting the power supply wirings When a plurality of connecting conductors for connection are arranged so that the surfaces of the connecting conductors face each other, the surface area of the connecting conductors facing each other can be increased, and a large capacity can be formed. Therefore, power bounce can be more effectively suppressed.

  Further, in the stacked semiconductor package of the present invention, two metal plates are arranged between the adjacent semiconductor packages so as to face each other in parallel with the surface of the semiconductor package, and the metal plates are connection conductors for connecting power supply wirings. When connected to the connection conductor for ground wiring connection, a capacitor is formed between the power supply metal plate connected to the connection conductor for power supply wiring connection and the ground metal plate connected to the ground conductor for ground wiring connection. It becomes possible to do. In addition to forming the capacitance between the connecting conductors, it is possible to further form a capacitance using a metal plate, so that power bounce can be more effectively suppressed.

  In the stacked semiconductor package of the present invention, when a resin having a high dielectric constant is disposed between the metal plates, the power supply metal plate connected to the ground conductor for connecting the power supply wiring and the ground connected to the ground conductor for connecting the ground wiring Since the capacity formed between the metal plates can be increased, the power bounce can be further suppressed.

  In addition, since the electronic device of the present invention includes the electronic component including the semiconductor element mounted on the stacked package of the present invention, the power supply bounce of the power supplied to the electronic component is suppressed, and the electronic component is operated. An electronic device with excellent performance can be obtained.

  The stacked semiconductor package of the present invention will be described in detail below.

  FIG. 1 is a cross-sectional view showing an example of an embodiment of a stacked semiconductor package 1 of the present invention, and FIG. 2 is a plan view of FIG. FIG. 3 is a plan view showing another example of the embodiment of the stacked semiconductor package of the present invention. 1 to 3, the same parts are denoted by the same reference numerals. FIG. 1 shows a cross section A-AA of FIG. Further, in FIG. 2 and FIG. 3, the specific conductor portion is hatched for easy understanding. Therefore, this hatching does not indicate a cross section.

  1 to 3, reference numeral 1 denotes a stacked semiconductor package of the present invention. Reference numeral 2 denotes a substrate of the semiconductor package, 2a denotes a substrate of the first semiconductor package as viewed from the mounting substrate 8, and 2b denotes a substrate of the second semiconductor package as viewed from the mounting substrate 8. Reference numeral 3 denotes two metal plates, 3a is a metal plate (hereinafter also referred to as a power supply potential metal plate) connected to the connection conductor 4a for connecting the power supply wiring, and 3b is connected to the connection conductor 4b for connecting the ground wiring. A metal plate (hereinafter also referred to as a ground potential metal plate) is shown. Reference numeral 4 denotes a connection conductor for connecting adjacent semiconductor packages, 4a is a connection conductor for connecting power supply lines for connecting power supply wirings of adjacent semiconductor packages (hereinafter also referred to as a power supply connection conductor), and 4b is adjacent to each other. A connection conductor for ground wiring connection (hereinafter also referred to as a ground connection conductor) for connecting the ground wirings of the semiconductor package (hereinafter also referred to as a ground connection conductor), 4c is a connection conductor for signal wiring connection (hereinafter referred to as a connection conductor for signal wiring of adjacent semiconductor packages) Also referred to as a signal connection conductor). Reference numeral 5 denotes a semiconductor element as an example of an electronic component. Reference numeral 6 denotes a resin having a high dielectric constant surrounding the connecting conductor 4 and a resin having a high dielectric constant disposed between the two metal plates 3.

  In the stacked semiconductor package 1 of the present invention, the substrate 2a and the substrate 2b are made of an aluminum oxide sintered body, an aluminum nitride sintered body, a silicon carbide sintered body, a silicon nitride sintered body, and a mullite sintered body. Alternatively, it mainly comprises an inorganic insulating material such as glass ceramics and metal wiring for connecting the semiconductor element 5 and the mounting substrate 8.

  The metal wiring is, for example, metal powder metallization such as tungsten (W), molybdenum (Mo), molybdenum-manganese (Mo-Mn), copper (Cu), silver (Ag) or silver-palladium (Ag-Pd), or It is formed of copper (Cu), silver (Ag), nickel (Ni), chromium (Cr), titanium (Ti), gold (Au), niobium (Nb), or an alloy thereof. The metal wiring is deposited and formed in a predetermined pattern on an insulator such as ceramics by a metal layer forming means such as a thick film method or a thin film method.

  For example, when a metal wiring is formed by a thick film method, a metal paste obtained by adding and mixing an appropriate organic binder or solvent to W powder is printed and applied in a predetermined pattern on a ceramic green sheet. It can be formed by stacking to form a laminate and firing.

  Moreover, the inorganic insulating material of the board | substrate 2a and the board | substrate 2b is formed by board | substrate formation means, such as a ceramic green sheet lamination method and an extrusion molding method, for example.

  These inorganic insulating materials are produced as follows. When the inorganic insulating material is made of, for example, an aluminum oxide sintered body, first, a suitable organic binder or solvent is added to and mixed with the raw material powder such as aluminum oxide, silicon oxide, calcium oxide or magnesium oxide to form a slurry. A ceramic green sheet is obtained by making this into a sheet by a doctor blade method or the like. A ceramic green sheet is printed with a metal paste that forms each conductor layer in a predetermined pattern, and these are laminated one above the other. Finally, the laminate is fired at a temperature of about 1600 ° C. in a reducing atmosphere. Produced.

  Further, the inorganic insulating material of the substrate 2a and the substrate 2b is an organic insulating material such as polyimide, epoxy resin, fluororesin, polynorbornene or benzocyclobutene, or an inorganic insulating powder such as ceramic powder, which is thermosetting such as epoxy resin. You may consist of electrically insulating materials, such as a composite insulating material couple | bonded with resin.

  For example, in the case of a composite insulating material, first, a thermosetting epoxy resin mixed with ceramics made of an aluminum oxide sintered body, or a glass epoxy resin made by impregnating a glass fiber woven cloth with an epoxy resin, etc. An organic resin precursor is deposited on the upper surface of the insulating layer by a spin coating method or a curtain coating method, and the insulating layer is formed by thermosetting the organic resin precursor. This insulating layer and a thin film wiring conductor layer formed by adopting a copper layer by employing a thin film forming technique such as an electroless plating method or a vapor deposition method and a photolithography technique are alternately laminated, and a temperature of about 170 ° C. It is manufactured by heating and curing. The thickness of these laminated inorganic insulating materials is set so as to satisfy the conditions such as mechanical strength and electrical characteristics corresponding to the required specifications in accordance with the characteristics of the materials used.

  Further, in the stacked semiconductor package 1 of the present invention, on the surfaces of the substrate 2a and the substrate 2b, a semiconductor element 5 such as an IC or LSI operating at high speed, or an optical semiconductor such as a semiconductor laser (LD) or a photodiode (PD). Element 5 is mounted. This semiconductor element 5 has signal, power supply, and ground terminals (not shown) formed on the back side, and each terminal is connected to a flip chip electrode pad formed on the surface of the substrate 2a and the substrate 2b. -Electrically connected and mounted via a flip-chip connecting conductor bump made of solder such as lead (Sn-Pb) alloy, tin-silver-copper (Sn-Ag-Cu), or gold (Au). .

  Each flip chip electrode pad is desired via a metal wiring formed inside the substrate 2a and the substrate 2b and a through conductor such as a via conductor formed from the surface of the substrate 2a and the substrate 2b to the inside. Each terminal of the semiconductor element 5 is electrically connected to a corresponding circuit wiring.

  The through conductors (not shown) formed in the substrate 2a and the substrate 2b are formed by forming a through hole in a ceramic green sheet by a punching method using a die or punching or a processing method such as laser processing. It can be formed by applying a metal paste obtained by adding and mixing a suitable organic binder, solvent or the like to a predetermined region on the inner side surface of the through hole and firing it together with a laminate of ceramic green sheets.

  In the stacked semiconductor package 1 of the present invention, the line conductors (not shown) formed in the substrate 2a and the substrate 2b for transmitting signal waveforms are formed in the wiring width of each line conductor and in the substrate 2a and the substrate 2b. By setting the thickness of the insulating layer, the characteristic impedance of the line conductor can be set to an arbitrary value. Therefore, for example, a line conductor having good transmission characteristics can be formed by a plurality of line conductors. The characteristic impedance of each line conductor is generally set to 50Ω. The plurality of line conductors may transmit different electrical signals.

  The stacked semiconductor package 1 of the present invention is formed by stacking a plurality of semiconductor packages including a semiconductor package substrate 2 and a semiconductor element 5. The power supply wirings and the ground wirings of the adjacent semiconductor package substrates 2 are connected by the connection conductor 4. A plurality of power supply connection conductors 4 a and ground connection conductors 4 b are alternately arranged along the surface of the substrate 2 between adjacent semiconductor package substrates 2.

  In the case of the substrate 2a, the charge necessary for the switching operation of the semiconductor element 5 is supplied via the external connection conductor bumps 7 connected to the external electric circuit and the metal wiring in the substrate 2a. In the case of the substrate 2b, the mounting substrate 8 The external connection conductor bumps 7 connected to the external electric circuit formed above, the metal wiring in the substrate 2a, the power supply connection conductor 4a, the power supply potential metal plate 3a, and the metal wiring in the substrate 2b are supplied. . The ground potential is supplied via the external connection conductor bump 7, the metal wiring in the substrate 2a, the ground connection conductor 4b, the ground potential metal plate 3b, and the metal wiring in the substrate 2b.

  In the stacked semiconductor package 1 of the present invention, the decoupling capacitance formed between the power connection conductor 4 a and the ground connection conductor 4 b and between the power supply potential metal plate 3 a and the ground potential metal plate 3 b is supplied to the semiconductor element 5. It serves to compensate for the electric charge. As a result, the signal waveform obtained by the switching operation of the semiconductor element 5 propagates through the wiring formed in the stacked semiconductor package 1, and the external electric current formed on the mounting substrate 8 via the external connection conductor bump 7. Transmitted to the circuit.

  In this way, charges necessary for the operation of the semiconductor element 5 are supplied from the decoupling capacitance between the power connection conductor 4a and the ground connection conductor 4b and between the power supply potential metal plate 3a and the ground potential metal plate 3b. The Since the decoupling capacitance is arranged in the vicinity of the semiconductor element 5, the charge supply path from the decoupling capacitance to the semiconductor element 5 is shortened. As a result, the voltage fluctuation caused by the inductance associated with the power supply path, that is, the power bounce of the power supply circuit supplied to the semiconductor element 5 is reduced.

  In the stacked semiconductor package 1 of the present invention, the power supply connection conductor 4a and the ground connection conductor 4b are the center on which the semiconductor element 5 of the substrate 2 is mounted, as shown in FIG. And the signal connection conductor 4c for transmitting the signal waveform obtained by the switching operation of the semiconductor element 5 is preferably arranged. For example, the signal connection conductor 4c is arranged around the semiconductor element 5, and the power connection conductor 4a and the ground connection conductor 4b are arranged in a staggered manner on the outer periphery thereof. Is preferred. That is, as shown in FIG. 2, the connection conductors 4 a and 4 b are arranged in a plurality of rows at intersections of vertical and horizontal grids, and in the second row 42 adjacent to the first row 41, the first row 41. Next to the power connection conductor 4a (the connection conductor with the right-up hatching), the ground connection conductor 4b (connection conductor with the right-down hatching) in the second row 42 is positioned for the power supply. A connection conductor 4a and a ground connection conductor 4b are arranged.

  Further, from the viewpoint of reliable charge supply to the semiconductor element 5, the connection conductor 4a for connecting the power supply wiring, the connection conductor 4b for connecting the ground wiring, and the connection conductor 4c for connecting the signal wiring are arranged closely so as not to contact each other. It is good to be done.

  A resin 6 having a high dielectric constant is preferably disposed between the power connection conductor 4a and the ground connection conductor 4b. As a result, the capacitance value between the power connection conductor 4a and the ground connection conductor 4b can be increased.

  The power connection conductor 4a and the ground connection conductor 4b are, for example, formed in a column shape so as to connect the adjacent semiconductor packages by melting the low melting point solder bumps welded to the outer periphery of the high melting point solder bumps. Alternatively, a low melting point solder is welded around the metal bumps so as to connect adjacent semiconductor packages. Here, the low melting point solder bump is a eutectic solder having a tin ratio of 63% and a melting point of 184 ° C., or a metal having a lower melting point than eutectic solder, such as zinc and indium. Solder with a low is preferred.

  The power connection conductor 4a and the ground connection conductor 4b may be rectangular, square, or cylindrical. In the case of a cylindrical shape, it is preferable that the conductor thickness is equal to the skin depth of the maximum frequency component when a signal is transmitted. That is, when the cylindrical shape is viewed from above, it is preferable that the cylindrical shape is a portion where the conductor exists from the outer periphery to the inner periphery and deep in the skin. The inside may be a non-conductor.

  Further, in the stacked semiconductor package 1 of the present invention, as shown in FIG. 1, two metal plates 3 (power supply) are provided between the semiconductor package substrates 2 adjacent in the layer direction in parallel with the surface of the semiconductor package substrate 2. The wide surfaces of the potential metal plate 3a and the ground potential metal plate 3b) are arranged to face each other, and the two metal plates 3 are connected to the power connection conductor 4a and the ground connection conductor 4b, respectively, The connection conductor 4c for use is not connected.

  Such two metal plates are, for example, tungsten (W), molybdenum (Mo), molybdenum-manganese (Mo-Mn), copper (Cu), silver (Ag), or silver-palladium (Ag-Pd). It is made of metal powder metallization, or copper (Cu), silver (Ag), nickel (Ni), chromium (Cr), titanium (Ti), gold (Au), niobium (Nb), or an alloy thereof.

  The metal plate 3 also shields electromagnetic interference (EMI noise) between adjacent semiconductor packages. Furthermore, it also has a function to dissipate the heat retained between the semiconductor packages by conducting heat through the metal plate 3.

  Further, the distance between the power supply potential metal plate 3a and the ground potential metal plate 3b is preferably as short as possible. Further, the shape of the two metal plates 3 in plan view may be a rhombus shape, a polygon, or a circle in addition to a square and a rectangle.

  Further, a resin having a high dielectric constant is preferably used between the two metal plates 3 or between the power connection conductor 4a and the ground connection conductor 4b. For example, an epoxy resin or a polyimide resin is used. . For example, you may comprise by arrange | positioning resin obtained by mixing materials with high dielectric constant, such as an acrylic resin, a phenol resin, and a silicon resin.

  Further, in the stacked semiconductor package 1 of the present invention, the connection conductor 4 that connects adjacent semiconductor packages may have a strip shape using an elongated metal plate as shown in FIG. In this case, the strips are arranged so that the long sides are positioned vertically, and the long sides facing each other are connected to the power supply wirings or the grounding wirings of the adjacent semiconductor package substrate 2, and the plate A plurality of power supply connection conductors 4a and ground connection conductors 4b are alternately arranged so that the wide surfaces of the electrodes face the wide surfaces of adjacent plates.

  Here, the signal connection conductor 4 c for transmitting the signal waveform obtained by the switching operation of the semiconductor element 5 is preferably disposed around the semiconductor element 5. The power supply connection conductor 4a and the ground connection conductor 4b are arranged outside thereof, and are arranged so as to be inclined to the left or right at an angle of 45 ° with respect to the side of the semiconductor package substrate 2. The power connection conductor 4a and the ground connection conductor 4b are alternately arranged so that the wide surfaces face each other. The thickness of the power connection conductor 4a and the ground connection conductor 4b is the same as that of the signal connection conductor 4c. It is desirable to have a thickness approximately equal to the diameter value.

  The electronic component mounted on the stacked semiconductor package 1 of the present invention is not limited to the semiconductor element 5, but an electronic circuit using a chip resistor, a thin film resistor, a coil inductor, a cross inductor, a chip capacitor, an electrolytic capacitor, or the like. A module or the like may be configured.

  Further, the shape of the stacked semiconductor package 1 in plan view may be a rhombus shape, a hexagonal shape, an octagonal shape, a circular shape or the like in addition to a square shape or a rectangular shape.

  The stacked semiconductor package 1 according to the present invention includes an electronic component storage package such as a semiconductor element storage package, an electronic component mounting substrate, a so-called multichip module or multichip on which a large number of semiconductor elements 5 are mounted. Used as a package or motherboard.

  FIG. 4 is a diagram showing a part of the manufacturing process for forming the space between the semiconductor package substrates 2 of the stacked semiconductor package 1 according to the embodiment of the present invention.

  (A) First, as shown in FIG. 4A, the semiconductor element 5 is mounted on the central portions of the main surfaces of the substrate 2a and the substrate 2b.

  (B) Next, as shown in FIG. 4B, the high melting point solder ball 4aa for connecting the power supply wiring is applied to the power supply potential metal plate 3a by using the low melting point solder paste 4ab for connecting the power supply wiring. It connects to the predetermined location of the metal plate 3a.

  Further, a ground wiring connecting high melting point solder ball 4ba is connected to a predetermined portion of the ground potential metal plate 3b by using a ground wiring connecting low melting point solder paste 4bb to the ground potential metal plate 3b.

  A through hole having a diameter larger than that of the solder balls 4aa, 4ba, 4ca is provided at a position where the solder balls 4aa, 4ba, 4ca are not connected to the power supply potential metal plate 3a or the ground potential metal plate 3b.

  Two high melting point solder balls 4aa for connecting power lines are connected by a low melting point solder paste 4ab for connecting power lines. Two high melting point solder balls 4ba for connecting ground lines are connected by low melting point solder paste 4bb for connecting ground lines. Two connected high melting point solder balls 4ca for signal wiring connection are connected by a low melting point solder paste 4cb for signal wiring connection. Then, using a metal mask or the like supporting a solder ball, the ground wiring high melting point solder ball 4ba to which the two are connected and the signal wiring high melting point solder ball 4ca to the two are connected to the power supply potential metal plate 3a. The high melting point solder ball 4aa for connecting the power supply wiring to which the two are connected and the high melting point solder ball 4ca for the signal wiring to which the two are connected are respectively inserted into the through hole of the ground potential metal plate 3b. It arrange | positions so that the metal plate 3 may not be contacted.

  (C) Next, as shown in FIG. 4C, the power supply potential metal fabricated in (b) is mounted on the substrate 2a and the substrate 2b on which the semiconductor element 5 fabricated in (a) is mounted. The plate 3a and the ground potential metal plate 3b are mounted.

  (D) Next, as shown in FIG. 4D, the substrate 2b is inverted and laminated so that the semiconductor element 5 faces the substrate 2a produced in (c). .

  (E) Finally, as shown in FIG. 4 (e), the substrate 2a and the substrate 2b prepared by stacking in (d) are joined by reflow, and then sealed between adjacent semiconductor package substrates 2. Stop resin 6 is disposed.

  In this way, a structure to be mounted on the external connection conductor bump 7 of the stacked semiconductor package 1 is produced.

  The present invention is not limited to the above-described embodiments and examples, and various modifications can be made without departing from the scope of the present invention.

  In the description of the above embodiment, the terms “upper, lower, left and right” are merely used to describe the positional relationship in the drawings, and do not mean the positional relationship in actual use.

It is sectional drawing which shows an example of embodiment of the laminated semiconductor package of this invention. FIG. 2 is a plan view of the stacked semiconductor package shown in FIG. 1. It is a top view which shows the other example of embodiment of the laminated semiconductor package of this invention. FIG. 7 is a cross-sectional view showing a part of the method for manufacturing the stacked semiconductor package shown in FIG. 1. It is sectional drawing which shows the example of the conventional laminated semiconductor package.

Explanation of symbols

1: Stacked semiconductor package 2a: substrate 2b (for semiconductor package): substrate 3a (for semiconductor package): metal plate connected to connection conductor for power supply wiring (power supply potential metal plate)
3b: Metal plate (ground potential metal plate) connected to the connection conductor for ground wiring connection
4a: Connection conductor for connecting power supply wirings of adjacent semiconductor packages (connection conductor for power supply)
4b: Connection conductor for connecting ground wirings of adjacent semiconductor packages (connection conductor for grounding)
4c: Connection conductor (signal connection conductor) for connecting signal wirings of adjacent semiconductor packages
4aa: High melting point solder ball 4ab for power wiring connection Low melting point solder paste 4ba for power wiring connection High melting point solder ball 4bb for ground wiring connection Low melting solder paste 4ca for ground wiring connection High melting point solder ball for signal wiring connection 4cb: Low melting point solder paste for signal wiring connection 5: Semiconductor element 6: Resin 7: Conductor bump for external connection
8: Mounting board

Claims (6)

In a stacked semiconductor package formed by stacking a plurality of semiconductor packages, the power supply wirings and grounding wirings of adjacent semiconductor packages are connected by a connection conductor, and the connection conductors for power supply wiring connection and ground wiring connection The connecting conductors are strip-shaped, and the strip-shaped connecting conductors are arranged so that the long sides thereof are positioned vertically, and the long sides facing each other are adjacent to each other. The semiconductor package is connected to power supply wirings or grounding wirings , and a plurality of the connection conductors for connecting the power supply wirings and the surface of the connection conductors for connecting the grounding wirings are arranged to face each other. Laminated semiconductor package.   2. The stacked semiconductor package according to claim 1, wherein the connection conductor is formed by welding a low melting point solder around a metal bump.   3. The stacked semiconductor package according to claim 1, wherein the connection conductor is surrounded by a resin having a high dielectric constant.   Two metal plates are arranged between the adjacent semiconductor packages so as to face each other in parallel with the surface of the semiconductor package, and the metal plates are connected to the connection conductor for connecting the power supply wiring and the connection for connecting the ground wiring. 4. The stacked semiconductor package according to claim 1, wherein the stacked semiconductor package is connected to a conductor.   5. The stacked semiconductor package according to claim 4, wherein a resin having a high dielectric constant is disposed between the metal plates.   An electronic device comprising an electronic component including a semiconductor element mounted on the stacked semiconductor package according to claim 1.

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