JP2007200971A

JP2007200971A - Multilayer wiring substrate

Info

Publication number: JP2007200971A
Application number: JP2006014935A
Authority: JP
Inventors: Koki Kawabata; 幸喜川畑
Original assignee: Kyocera Corp
Current assignee: Kyocera Corp
Priority date: 2006-01-24
Filing date: 2006-01-24
Publication date: 2007-08-09

Abstract

<P>PROBLEM TO BE SOLVED: To further improve operation capability of a semiconductor element by remarkably suppressing power supply ground noise generated during the switching operation of the semiconductor element. <P>SOLUTION: The wiring substrate 1 comprises an insulating substrate formed by laminating a plurality of insulating layers; a power supply wiring and a ground wiring laid between insulating layers; a power supply electrode and a ground electrode formed adjacently; an area projected to the external side from each external circumferential surface of the power supply electrode and grounding electrode; and a power supply penetrating conductor and a ground penetrating conductor which are formed toward the power supply wiring and ground wiring from each projected area of the power supply electrode and ground electrode, and respectively connect the power supply electrode and the ground electrode to the power supply wiring and the ground wiring. In the structure explained above, the projected area of the power supply electrode and the projected area of the ground electrode are arranged with the side surfaces thereof oppositely arranged each other, and the power supply penetrating conductor and the ground penetrating conductor are arranged adjacently. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

本発明は、動作速度が高速度化した半導体素子をはじめとする電子部品が搭載される多層配線基板に関するものである。 The present invention relates to a multilayer wiring board on which electronic components such as a semiconductor element having an increased operating speed are mounted.

近年、半導体素子の動作速度の高速化が進む中で、半導体素子をはじめとする電子部品が搭載される多層配線基板においては、半導体素子のスイッチング動作が同時に複数起きた場合に半導体素子の基準電位が変動し、半導体素子の誤動作を引き起こす同時スイッチングノイズやＥＭＩノイズが引き起こされるといった問題が発生している。 In recent years, as the operating speed of semiconductor elements has been increased, in a multilayer wiring board on which electronic components such as semiconductor elements are mounted, the reference potential of the semiconductor element is detected when multiple switching operations of the semiconductor element occur simultaneously. Has fluctuated, causing problems such as simultaneous switching noise and EMI noise causing malfunction of the semiconductor element.

この問題を解決するためには、電荷が供給される経路に付随する抵抗成分やインダクタンス成分を抑制し基準電位を安定化させることが有効である。方法としては、半導体素子と、多層配線基板に設けられた外部電気回路への実装に用いられる
接地用や電源用の外部電極（いわゆるＢＧＡパッド等）との間の抵抗成分やインダクタンス成分を低減することである。具体的には、図４および図５に示すように電源配線層４４と電源電極４１１あるいは接地配線層４５と接地電極４１２を複数の電源貫通導体４９あるいは接地貫通導体４１０で並列に接続する方法などがある。 In order to solve this problem, it is effective to stabilize the reference potential by suppressing the resistance component and the inductance component associated with the path through which the charge is supplied. As a method, a resistance component and an inductance component between a semiconductor element and a grounding or power supply external electrode (so-called BGA pad or the like) used for mounting on an external electric circuit provided on the multilayer wiring board are reduced. That is. Specifically, as shown in FIGS. 4 and 5, a method in which the power supply wiring layer 44 and the power supply electrode 411 or the ground wiring layer 45 and the ground electrode 412 are connected in parallel by a plurality of power supply through conductors 49 or ground through conductors 410. There is.

なお、図４は従来の多層配線基板の一例を示す断面図であり、図５は、電源電極４１１や接地電極４１２の部分を拡大して示す平面部分拡大図である。図４および図５において同じ部位には同じ符号を付している。 4 is a cross-sectional view showing an example of a conventional multilayer wiring board, and FIG. 5 is an enlarged partial plan view showing the power electrode 411 and the ground electrode 412 in an enlarged manner. 4 and 5, the same parts are denoted by the same reference numerals.

これらの手法により半導体素子に近い位置からの電荷供給や単位面積当たりの電荷供給量を増加できるため、電荷の供給経路に付随する抵抗による電圧降下やインダクタンスによる基準電位変動が抑制され、半導体素子に十分な電荷を供給することができるため、同時スイッチングノイズを抑制することが可能となる。
特開２００３−３０３９１３ These methods can increase the amount of charge supplied from a position close to the semiconductor element and the amount of charge supplied per unit area, so that voltage drop due to resistance associated with the charge supply path and fluctuations in the reference potential due to inductance are suppressed. Since sufficient charge can be supplied, simultaneous switching noise can be suppressed.
JP2003-303913

しかしながら、上記従来の技術における半導体素子と外部電源回路に接続される外部電極間の抵抗成分やインダクタンス成分を抑制する手法は、近年の半導体素子等の電子部品の小型化，高集積化に応じたいわゆる高密度化に起因して、次のような問題点が生じるようになってきている。 However, the technique for suppressing the resistance component and the inductance component between the semiconductor element and the external electrode connected to the external power supply circuit in the above-described conventional technology is in response to the recent miniaturization and high integration of electronic components such as semiconductor elements. Due to so-called densification, the following problems have arisen.

すなわち、図５に示すように高密度化に応じて多層配線基板４１と外部電気回路とを接続するために用いられる電源電極４１１および接地電極４１２等の外部電極の小径化および狭ピッチ化が進んでいる。このため、外部電極の面積が小さくなり、外部電極に複数が並列に接続される電源貫通導体４９および接地貫通導体４１０等の貫通導体同士の間隔が狭くなってきている。 That is, as shown in FIG. 5, the diameter and pitch of the external electrodes such as the power supply electrode 411 and the ground electrode 412 used for connecting the multilayer wiring board 41 and the external electric circuit are reduced as the density is increased. It is out. For this reason, the area of the external electrode is reduced, and the interval between the through conductors such as the power supply through conductor 49 and the ground through conductor 410 connected in parallel to the external electrode is becoming narrower.

このとき、電源貫通導体４９を例にとると、貫通導体の自己インダクタンスをＬ（Ｈ）、並列に接続された隣接貫通導体との相互インダクタンスＭ（Ｈ）とした場合、貫通導体一本当りのインダクタンスは、同一方向に電流が流れる場合、Ｌ＋Ｍ（Ｈ）で表される。相互インダクタンスは、貫通導体間の間隔に反比例するため、外部電極の小径化に伴って外部電極に複数が並列に接続される貫通導体同士の間隔が狭くなることによってその値は大きくなる。このため、貫通導体の並列接続により抵抗成分は減少するものの、インダクタンス成分においては相互インダクタンスの影響によりインダクタンスの低減効果を十分に得にくい。接地貫通導体４１０についても同様である。 At this time, taking the power supply through conductor 49 as an example, if the self-inductance of the through conductor is L (H) and the mutual inductance M (H) with the adjacent through conductors connected in parallel, the per through conductor The inductance is expressed as L + M (H) when current flows in the same direction. Since the mutual inductance is inversely proportional to the distance between the through conductors, the value increases as the distance between the plurality of through conductors connected in parallel to the external electrode is reduced as the diameter of the external electrode is reduced. For this reason, although the resistance component is reduced by the parallel connection of the through conductors, it is difficult to sufficiently obtain the inductance reduction effect due to the mutual inductance in the inductance component. The same applies to the ground through conductor 410.

このため、半導体素子の小型化，高集積化に応じた多層配線基板の高密度化に起因するインダクタンス成分と半導体素子からの電流によって電源配線と接地配線間に同時スイッチングノイズが引き起こされるため、半導体素子を安定して動作させることが難しくなってきている。 For this reason, simultaneous switching noise is caused between the power supply wiring and the ground wiring due to the inductance component and the current from the semiconductor element due to the high density of the multilayer wiring board corresponding to the miniaturization and high integration of the semiconductor element. It has become difficult to operate the element stably.

本発明は、上記問題点を解決するために案出されたものであり、その目的は、複数の絶縁層を積層して成る絶縁基板内に、電源配線と接地配線を有する多層配線基板において、搭載される半導体素子などの電子部品のスイッチング動作時に発生する同時スイッチングノイズを大幅に抑制して半導体素子の動作を良好なものとすることにある。 The present invention has been devised in order to solve the above-mentioned problems, and its purpose is to provide a multilayer wiring board having a power supply wiring and a ground wiring in an insulating substrate formed by laminating a plurality of insulating layers. An object of the present invention is to improve the operation of the semiconductor element by largely suppressing the simultaneous switching noise generated during the switching operation of the electronic component such as the mounted semiconductor element.

本発明の多層配線基板は、複数の絶縁層が積層されてなる絶縁基板と、前記絶縁層の層間に配設された電源配線および接地配線と、前記絶縁基板の主面に、互いに隣り合うように形成された電源電極および接地電極と、該電源電極および接地電極の各外周面から外側へ突出する突出部分と、前記電源電極および接地電極の各突出部分から前記電源配線および接地配線にかけて形成され、前記電源電極および接地電極を前記電源配線および接地配線にそれぞれ接続する電源貫通導体および接地貫通導体とを備え、前記電源電極の突出部と前記接地電極の突出部とが互いに側面を対向させて配置されるとともに、前記電源貫通導体と前記接地貫通導体とが互いに隣り合って配置されていることを特徴とするものである。 The multilayer wiring board of the present invention is adjacent to the insulating substrate in which a plurality of insulating layers are laminated, the power supply wiring and the ground wiring arranged between the insulating layers, and the main surface of the insulating substrate. The power supply electrode and the ground electrode formed on the power supply electrode and the ground electrode, projecting portions projecting outward from the respective outer peripheral surfaces of the power supply electrode and the ground electrode, and extending from the projecting portions of the power supply electrode and the ground electrode to the power supply wiring and the ground wiring. A power supply through conductor and a ground through conductor for connecting the power supply electrode and the ground electrode to the power supply wiring and the ground wiring, respectively, and the protruding portion of the power supply electrode and the protruding portion of the ground electrode face each other. In addition, the power supply through conductor and the ground through conductor are arranged adjacent to each other.

また、本発明の多層配線基板は、上記構成において、前記突出部分が、前記電源電極および接地電極の各外周面に複数個ずつ形成されていることを特徴とするものである。 The multilayer wiring board according to the present invention is characterized in that, in the above-described configuration, a plurality of the protruding portions are formed on each outer peripheral surface of the power supply electrode and the ground electrode.

また、本発明の多層配線基板は、上記構成において、前記突出部分の主面から前記絶縁基板の表面にかけて一体的に覆うように絶縁体が形成されていることを特徴とするものである。 The multilayer wiring board of the present invention is characterized in that, in the above configuration, an insulator is formed so as to be integrally covered from the main surface of the protruding portion to the surface of the insulating substrate.

また、本発明の多層配線基板は、上記構成において、前記絶縁体は、前記突出部分の表面から隣り合う前記絶縁基板の表面にかけて一体的に覆うように形成されていることを特徴とするものである。 The multilayer wiring board of the present invention is characterized in that, in the above configuration, the insulator is formed so as to be integrally covered from the surface of the protruding portion to the surface of the adjacent insulating substrate. is there.

本発明の多層配線基板によれば、電源電極の突出部と接地電極の突出部とが互いに側面を対向させて配置されるとともに、電源貫通導体と接地貫通導体とが互いに隣り合って配置されていることから、搭載される半導体素子のスイッチング動作時に発生する同時スイッチングノイズを大幅に抑制して、半導体素子の動作速度が高速化した場合でも、半導体素子の動作を良好なものとすることができる。 According to the multilayer wiring board of the present invention, the projecting portion of the power electrode and the projecting portion of the ground electrode are arranged with the side surfaces facing each other, and the power supply through conductor and the ground through conductor are arranged adjacent to each other. Therefore, it is possible to greatly suppress the simultaneous switching noise generated during the switching operation of the mounted semiconductor element, and to improve the operation of the semiconductor element even when the operation speed of the semiconductor element is increased. .

つまり、電源貫通導体と接地貫通導体とは互いに隣接して位置することになるため、電源貫通導体と接地貫通導体間の相互インダクタンスの影響を強めることができる。この場合、電源貫通導体の電流の方向（電源電極から電源配線に向かう給電）と、接地貫通導体の電流の方向（接地配線から接地電極に向かう接地）とは逆向きなので、電源貫通導体（接地貫通導体）に、隣り合う接地貫通導体（電源貫通導体）との間で生じる相互インダクタンスが抑制され、自己インダクタンスと相互インダクタンスを合わせたインダクタンス成分の低減に有効である。 That is, since the power supply through conductor and the ground through conductor are positioned adjacent to each other, the influence of mutual inductance between the power supply through conductor and the ground through conductor can be increased. In this case, since the direction of the current of the power supply through conductor (power feeding from the power supply electrode to the power supply wiring) is opposite to the direction of the current of the grounding through conductor (grounding from the ground wiring to the ground electrode), the power supply through conductor (grounding) The mutual inductance generated between the grounding through conductor and the adjacent grounding through conductor (power supply through conductor) is suppressed, which is effective in reducing the inductance component that combines the self-inductance and the mutual inductance.

また同時に、電源貫通導体同士、および接地貫通導体同士は、それぞれ、面積の狭い電源電極や接地電極の範囲を越えて突出部分に形成して、隣接距離を従来よりも大きくすることができるため、電源貫通導体同士あるいは接地貫通導体同士の相互インダクタンスの影響を弱めることができる。そのため、電源配線と電源電極とを接続する電源貫通導体、および接地配線と接地電極とを接続する接地貫通導体に付随するインダクタンス成分を低減することが可能になる。 At the same time, the power supply through conductors and the ground through conductors can be formed in the protruding portion beyond the range of the power supply electrode and the ground electrode having a small area, respectively, so that the adjacent distance can be made larger than before. The influence of mutual inductance between power supply through conductors or between ground through conductors can be reduced. Therefore, it is possible to reduce the inductance component associated with the power supply through conductor connecting the power supply wiring and the power supply electrode and the ground through conductor connecting the ground wiring and the ground electrode.

すなわち電源貫通導体を例にとると、電源貫通導体の自己インダクタンスをＬｐ（Ｈ）、隣接する接地貫通導体との相互インダクタンスＭｇ（Ｈ）とした場合、貫通導体一本当りのインダクタンスは、Ｌｐ-Ｍｇ（Ｈ）で表されるため、貫通導体のインダクタンスの削減効果を得ることが可能である。また、電源貫通導体同士においては、隣接する貫通導体との相互インダクタンスをＭｐ（Ｈ）とした場合、Ｌｐ＋Ｍｐ（Ｈ）で表されるが、貫通導体同士の隣接距離を従来よりも大きくすることによってＭｐ（Ｈ）を小さくすることができるため従来に対してインダクタンスの上昇を抑制することが可能となる。 That is, taking the power supply through conductor as an example, when the self-inductance of the power supply through conductor is Lp (H) and the mutual inductance Mg (H) with the adjacent ground through conductor is, the inductance per through conductor is Lp−. Since it is represented by Mg (H), it is possible to obtain an effect of reducing the inductance of the through conductor. In addition, in the power supply through conductors, when the mutual inductance with the adjacent through conductor is Mp (H), it is represented by Lp + Mp (H). By making the adjacent distance between the through conductors larger than before, Since Mp (H) can be reduced, an increase in inductance can be suppressed as compared with the prior art.

したがって、半導体素子に電荷が供給される際にインダクタンス成分による電圧変動が抑制されることとなり、半導体素子に安定して電荷が供給され同時スイッチングノイズの発生を抑制することができる。 Therefore, voltage fluctuation due to the inductance component is suppressed when charge is supplied to the semiconductor element, and the charge is stably supplied to the semiconductor element, and the occurrence of simultaneous switching noise can be suppressed.

また、本発明の多層配線基板によれば、上記構成において、突出部分が、電源電極および接地電極の各外周面に複数個ずつ形成されている場合には、各突出部分のインダクタンスに起因して電荷が供給される経路のインダクタンスが増加することを防止し、半導体素子の動作をより良好にすることができる。すなわち、突出部分の持つインダクタンス成分が電源電極の突出部分と接地電極間の突出部分の相互インダクタンスによって相殺されて低減することができる。そのため、突出部分のインダクタンスに起因して基準電位の変動が誘発されることは防止される。また、突出部分が複数個形成されることによって並列接続になるため、突出部分のインダクタンスはより削減される。また、抵抗成分（直流抵抗）もさらに低減される。したがって、インダクタンス成分の削減によって同時スイッチングノイズがさらに抑制されるため、より一層、搭載される電子部品の動作について、誤動作が抑制された良好な多層配線基板とすることができる。 Further, according to the multilayer wiring board of the present invention, in the above configuration, when a plurality of protruding portions are formed on each outer peripheral surface of the power supply electrode and the ground electrode, it is caused by the inductance of each protruding portion. It is possible to prevent the inductance of the path through which the charge is supplied from increasing, and to improve the operation of the semiconductor element. That is, the inductance component of the protruding portion is offset by the mutual inductance of the protruding portion between the power electrode and the ground electrode, and can be reduced. Therefore, it is possible to prevent the reference potential from being changed due to the inductance of the protruding portion. In addition, since the plurality of protruding portions are formed in parallel connection, the inductance of the protruding portion is further reduced. Further, the resistance component (DC resistance) is further reduced. Therefore, since the simultaneous switching noise is further suppressed by reducing the inductance component, it is possible to obtain a good multilayer wiring board in which malfunctions are further suppressed in the operation of the mounted electronic component.

また、本発明の多層配線基板によれば、上記構成において、突出部分の主面から絶縁基板の表面にかけて一体的に覆うように絶縁体が形成されている場合には、突出部分がアンカーの役割を果たし、絶縁基板に対する電源電極および接地電極の接合強度を向上することができるため電源電極と接地電極のはがれ等による実装信頼性の低下を効果的に抑止できる。 According to the multilayer wiring board of the present invention, in the above configuration, when the insulator is formed so as to cover the main surface of the protruding portion to the surface of the insulating substrate, the protruding portion serves as an anchor. Thus, since the bonding strength of the power supply electrode and the ground electrode to the insulating substrate can be improved, it is possible to effectively suppress a decrease in mounting reliability due to peeling of the power supply electrode and the ground electrode.

また、本発明の多層配線基板によれば、上記構成において、絶縁体が、突出部分の表面から隣り合う絶縁基板の表面にかけて一体的に覆うように形成されている場合には、絶縁体により、突出部分をより強固に絶縁基板に接合させておくことができるので、絶縁基板に対する電源電極および接地電極の接合強度をさらに向上することができる。そのため、電源電極と接地電極のはがれ等による実装信頼性の低下をより効果的に抑止できる。 Further, according to the multilayer wiring board of the present invention, in the above configuration, when the insulator is formed so as to integrally cover from the surface of the protruding portion to the surface of the adjacent insulating substrate, the insulator Since the protruding portion can be bonded to the insulating substrate more firmly, the bonding strength of the power supply electrode and the ground electrode to the insulating substrate can be further improved. For this reason, it is possible to more effectively suppress a decrease in mounting reliability due to peeling of the power supply electrode and the ground electrode.

これらの結果、半導体素子のスイッチング動作時に発生する同時スイッチングノイズをより効果的に抑制し半導体素子の高速動作時における作動性を非常に良好なものとすることができる。 As a result, the simultaneous switching noise generated during the switching operation of the semiconductor element can be more effectively suppressed, and the operability during the high-speed operation of the semiconductor element can be made very good.

本発明の多層配線基板について以下に詳細に説明する。図１は本発明の多層配線基板の実施の形態の一例を示す断面図であり、図２は図１の多層配線基板における電源電極および接地電極の周辺部の要部拡大平面図である。また、図３は図１の多層配線基板における電源電極および接地電極の周辺部の要部拡大断面図（裏面側）である。図１乃至図３において同じ部位には同じ符号を付している。 The multilayer wiring board of the present invention will be described in detail below. FIG. 1 is a cross-sectional view showing an example of an embodiment of a multilayer wiring board according to the present invention, and FIG. 2 is an enlarged plan view of an essential part of the periphery of a power supply electrode and a ground electrode in the multilayer wiring board of FIG. 3 is an enlarged cross-sectional view (back side) of the main part of the periphery of the power supply electrode and the ground electrode in the multilayer wiring board of FIG. 1 to 3, the same parts are denoted by the same reference numerals.

本発明の多層配線基板１において、図１に示す例では、絶縁基板２を構成する絶縁層２ａ〜２ｆは基本的には同じ比誘電率を有する絶縁材料で形成されている。絶縁層２ｃと絶縁層２ｄとの層間には信号配線群３が形成され、信号配線群３を挟む上下の絶縁層２ａ〜２ｃ，２ｄ〜２ｆの層間には、信号配線群３を間に挟むようにして広面積の電源配線４および接地配線５が形成されており、信号配線群３の各信号配線はストリップ線路構造を有している。この例では、信号配線３は複数が設けられ、その全部がストリップ線路構造である。 In the multilayer wiring substrate 1 of the present invention, in the example shown in FIG. 1, the insulating layers 2a to 2f constituting the insulating substrate 2 are basically formed of an insulating material having the same relative dielectric constant. A signal wiring group 3 is formed between the insulating layers 2c and 2d, and the signal wiring group 3 is interposed between the upper and lower insulating layers 2a to 2c and 2d to 2f that sandwich the signal wiring group 3. Thus, a wide area power supply wiring 4 and ground wiring 5 are formed, and each signal wiring of the signal wiring group 3 has a strip line structure. In this example, a plurality of signal wires 3 are provided, and all of them have a stripline structure.

なお、信号波形を伝送する信号配線群３は、各信号配線の配線幅および信号配線群３と電源配線４や接地配線５との間に介在する絶縁層２ｂ，２ｃの厚みを設定することにより、信号配線群３その特性インピーダンスを任意の値に設定することができる。そのため、例えば複数の信号配線３により、良好な伝送特性を有する信号配線群３を形成することが可能となる。各信号配線群３の特性インピーダンスは一般的には５０Ωに設定される。なお、信号配線群３に含まれる複数の信号配線３は、それぞれ異なる電気信号を伝送するものとしてもよい。 In the signal wiring group 3 for transmitting the signal waveform, the wiring width of each signal wiring and the thickness of the insulating layers 2b and 2c interposed between the signal wiring group 3 and the power supply wiring 4 and the ground wiring 5 are set. The characteristic impedance of the signal wiring group 3 can be set to an arbitrary value. Therefore, for example, the signal wiring group 3 having good transmission characteristics can be formed by the plurality of signal wirings 3. The characteristic impedance of each signal wiring group 3 is generally set to 50Ω. The plurality of signal wirings 3 included in the signal wiring group 3 may transmit different electrical signals.

本発明の多層配線基板１において、絶縁層２ａ〜２ｆは、例えばセラミックグリーンシート積層法によって形成される。この場合、絶縁層２ａ〜２ｆは、酸化アルミニウム質焼結体，窒化アルミニウム質焼結体，炭化珪素質焼結体，窒化珪素質焼結体，ムライト質焼結体またはガラスセラミックス等の無機絶縁材料から成る。また、絶縁層２ａ〜２ｆは、ポリイミド，エポキシ樹脂，フッ素樹脂，ポリノルボルネンまたはベンゾシクロブテン等の有機絶縁材料、あるいはセラミック粉末等の無機絶縁物粉末をエポキシ樹脂等の熱硬化性樹脂で結合して成る複合絶縁材料等の電気的な絶縁材料から成っていてもよい。 In the multilayer wiring board 1 of the present invention, the insulating layers 2a to 2f are formed by, for example, a ceramic green sheet lamination method. In this case, the insulating layers 2a to 2f are made of an inorganic insulating material such as an aluminum oxide sintered body, an aluminum nitride sintered body, a silicon carbide sintered body, a silicon nitride sintered body, a mullite sintered body, or a glass ceramic. Made of material. The insulating layers 2a to 2f are formed by bonding an organic insulating material such as polyimide, epoxy resin, fluororesin, polynorbornene or benzocyclobutene, or inorganic insulating powder such as ceramic powder with a thermosetting resin such as epoxy resin. It may be made of an electrically insulating material such as a composite insulating material.

絶縁層２ａ〜２ｆは、例えばセラミックグリーンシート積層法や、アディティブ法等の基板形成手段によって形成される。 The insulating layers 2a to 2f are formed by a substrate forming means such as a ceramic green sheet lamination method or an additive method.

これらの絶縁層２ａ〜２ｆは以下のようにして作製される。絶縁層２ａ〜２ｆが例えば酸化アルミニウム質焼結体から成る場合、まず、酸化アルミニウム，酸化珪素，酸化カルシウムまたは酸化マグネシウム等の原料粉末に適当な有機バインダや溶剤等を添加混合して泥漿状となし、これをドクターブレード法等を採用してシート状となすことによってセラミックグリーンシートを得る。そして、セラミックグリーンシートに信号配線群３および各導体層と成る金属ペーストを所定のパターンに印刷塗布して、これらを上下に積層し、最後にこの積層体を還元雰囲気中で約１６００℃の温度で焼成することによって製作される。 These insulating layers 2a to 2f are manufactured as follows. When the insulating layers 2a to 2f are made of, for example, an aluminum oxide sintered body, first, an appropriate organic binder or solvent is added to and mixed with raw material powders such as aluminum oxide, silicon oxide, calcium oxide or magnesium oxide to form a slurry. None, by adopting a doctor blade method or the like to form a sheet, a ceramic green sheet is obtained. Then, the signal paste group 3 and the metal paste which becomes each conductor layer are printed and applied in a predetermined pattern on the ceramic green sheet, and these are laminated up and down, and finally the laminated body is heated to a temperature of about 1600 ° C. in a reducing atmosphere. It is manufactured by firing at

また、絶縁層２ａ〜２ｆがエポキシ樹脂から成る場合、まず酸化アルミニウム質焼結体から成るセラミックスを混合した熱硬化性のエポキシ樹脂、あるいはガラス繊維を織り込んだ布にエポキシ樹脂を含浸させて成るガラスエポキシ樹脂等から成る絶縁層の上面に、有機樹脂前駆体をスピンコート法もしくはカーテンコート法等により被着させ、これを熱硬化処理することによって絶縁層を形成する。この絶縁層と、銅層を無電解めっき法や蒸着法等の薄膜形成技術およびフォトリソグラフィ技術を採用することによって形成して成る薄膜配線導体層とを交互に積層し、約１７０℃程度の温度で加熱硬化することによって製作される。 When the insulating layers 2a to 2f are made of an epoxy resin, first, a glass made by impregnating an epoxy resin into a thermosetting epoxy resin mixed with ceramics made of an aluminum oxide sintered body or a cloth woven with glass fibers. An organic resin precursor is deposited on the upper surface of an insulating layer made of an epoxy resin or the like by a spin coating method or a curtain coating method, and the insulating layer is formed by heat-curing the organic resin precursor. This insulating layer and a thin film wiring conductor layer formed by adopting a copper layer by employing a thin film forming technique such as an electroless plating method or a vapor deposition method and a photolithography technique are alternately laminated, and a temperature of about 170 ° C. It is manufactured by heating and curing.

これらの絶縁層２ａ〜２ｆの厚みは、使用する材料の特性に応じて、要求される仕様に対応する機械的強度や電気的特性等の条件を満たすように設定される。 The thicknesses of these insulating layers 2a to 2f are set so as to satisfy the conditions such as mechanical strength and electrical characteristics corresponding to the required specifications according to the characteristics of the materials used.

また、本発明の多層配線基板１において絶縁基板２の主面等の露出面（この実施形態では表面）には、高速で動作するＩＣ，ＬＳＩ等の半導体集積回路素子や半導体レーザ（ＬＤ），フォトダイオード（ＰＤ）等の光半導体素子等の半導体素子６が搭載される。この半導体素子６は、裏面（絶縁基板２に対向する面）側に信号用や電源用、接地用の端子（図示せず）が形成され、各端子が、絶縁基板２の表面に形成された電極パッド８に錫−鉛（Ｓｎ−Ｐｂ）合金等の半田や金（Ａｕ）等から成る半田バンプ７を介して電気的に接続されて実装される。 Further, in the multilayer wiring board 1 of the present invention, the exposed surface (the surface in this embodiment) such as the main surface of the insulating substrate 2 has a semiconductor integrated circuit element such as an IC or LSI operating at high speed, a semiconductor laser (LD), A semiconductor element 6 such as an optical semiconductor element such as a photodiode (PD) is mounted. The semiconductor element 6 has signal, power, and ground terminals (not shown) formed on the back surface (surface facing the insulating substrate 2), and each terminal is formed on the surface of the insulating substrate 2. The electrode pads 8 are mounted by being electrically connected via solder bumps 7 made of solder such as tin-lead (Sn-Pb) alloy or gold (Au).

各電極パッド８は、絶縁基板２の内部に形成されている信号配線３や電源配線４、接地配線５とそれぞれ、絶縁基板２の表面から内部にかけて形成されたビア導体等の内部導体（図示せず）等を介して電気的に接続され、半導体素子６の各端子が、対応する信号配線３、電源配線４および接地配線５と電気的に接続される。 Each electrode pad 8 includes an internal conductor (not shown) such as a via conductor formed from the surface of the insulating substrate 2 to the inside thereof, and the signal wiring 3, the power supply wiring 4, and the ground wiring 5 formed inside the insulating substrate 2. The terminals of the semiconductor element 6 are electrically connected to the corresponding signal wiring 3, power supply wiring 4 and ground wiring 5.

絶縁基板２の主面（この実施形態では裏面）には電源電極１１、接地電極１２、信号電極１６および被覆用の絶縁体１３が形成されている。電源電極１１、接地電極１２および信号電極１６はそれぞれ電源貫通導体９、接地貫通導体１０および信号貫通導体１５を介して多層配線基板１内の電源配線４、接地配線５および信号配線群３と電気的に接続されている。 On the main surface (the back surface in this embodiment) of the insulating substrate 2, a power electrode 11, a ground electrode 12, a signal electrode 16, and a covering insulator 13 are formed. The power supply electrode 11, the ground electrode 12 and the signal electrode 16 are electrically connected to the power supply wiring 4, the ground wiring 5 and the signal wiring group 3 in the multilayer wiring board 1 through the power supply through conductor 9, the ground through conductor 10 and the signal through conductor 15, respectively. Connected.

電源電極１１および接地電極１２を半田ボール等を介して外部電気回路（図示せず）に接続することにより、半導体素子６の電源端子および接地端子が、それぞれ、外部電気回路（電源用や接地用）と電気的に接続される。 By connecting the power supply electrode 11 and the ground electrode 12 to an external electric circuit (not shown) through solder balls or the like, the power supply terminal and the ground terminal of the semiconductor element 6 are respectively connected to the external electric circuit (for power supply and grounding). ) And electrically connected.

外部電気回路と電気的に接続された半導体素子６は、スイッチング動作に必要な電荷が外部電気回路と接続される電源電極１１および接地電極１２から電源配線４および接地配線５を介して供給され、半導体素子６のスイッチング動作によって得られた信号波形は多層配線基板１内に形成された信号配線群３を伝播し信号電極を介して外部電気回路に伝送される。 In the semiconductor element 6 electrically connected to the external electric circuit, charges necessary for the switching operation are supplied from the power supply electrode 11 and the ground electrode 12 connected to the external electric circuit via the power supply wiring 4 and the ground wiring 5. The signal waveform obtained by the switching operation of the semiconductor element 6 propagates through the signal wiring group 3 formed in the multilayer wiring board 1 and is transmitted to the external electric circuit via the signal electrode.

なお、信号配線群３、電源配線４、接地配線５、電源貫通導体９、接地貫通導体１０、信号貫通導体１５、電源電極１１、接地電極１２および信号電極１６は、例えばタングステン（Ｗ），モリブデン（Ｍｏ），モリブデン−マンガン（Ｍｏ−Ｍｎ），銅（Ｃｕ），銀（Ａｇ）または銀−パラジウム（Ａｇ−Ｐｄ）等の金属粉末メタライズ、あるいは銅（Ｃｕ），銀（Ａｇ），ニッケル（Ｎｉ），クロム（Ｃｒ），チタン（Ｔｉ），金（Ａｕ）またはニオブ（Ｎｂ）やそれらの合金等の金属材料により形成されている。 The signal wiring group 3, the power wiring 4, the ground wiring 5, the power through conductor 9, the ground through conductor 10, the signal through conductor 15, the power electrode 11, the ground electrode 12, and the signal electrode 16 are, for example, tungsten (W), molybdenum. (Mo), molybdenum-manganese (Mo-Mn), copper (Cu), silver (Ag) or silver-palladium (Ag-Pd) metal powder metallization, or copper (Cu), silver (Ag), nickel ( It is made of a metal material such as Ni), chromium (Cr), titanium (Ti), gold (Au), niobium (Nb) or an alloy thereof.

このような金属材料は、メタライズ法等の厚膜法や、薄膜法等の金属層形成手段により所定パターンに被着、形成すればよい。 Such a metal material may be deposited and formed in a predetermined pattern by a thick film method such as a metallizing method or a metal layer forming means such as a thin film method.

具体的には、信号配線群３、電源配線４、接地配線５、電源貫通導体９、接地貫通導体１０、電源電極１１、接地電極１２を、Ｗの金属粉末メタライズで形成する場合、Ｗ粉末に適当な有機バインダや溶剤等を添加混合して得た金属ペーストを、絶縁層２ａ〜２ｆと成るセラミックグリーンシートにスクリーン印刷法等の印刷法により所定のパターンで印刷塗布し、これをセラミックグリーンシートの積層体とともに焼成することによって形成することができる。 Specifically, when the signal wiring group 3, the power wiring 4, the ground wiring 5, the power through conductor 9, the ground through conductor 10, the power electrode 11, and the ground electrode 12 are formed of W metal powder metallization, A metal paste obtained by adding and mixing an appropriate organic binder or solvent is printed and applied in a predetermined pattern to a ceramic green sheet to be the insulating layers 2a to 2f by a printing method such as a screen printing method. It can form by baking with the laminated body of.

また、信号配線群３、電源配線４、接地配線５、電源貫通導体９、接地貫通導体１０、信号貫通導体１５、電源電極１１、接地電極１２、信号電極１６を金属薄膜で形成する場合、例えばスパッタリング法，真空蒸着法またはメッキ法により金属薄膜を形成した後、フォトリソグラフィ法により所定の配線パターンに形成することができる。 When the signal wiring group 3, the power supply wiring 4, the ground wiring 5, the power supply through conductor 9, the ground through conductor 10, the signal through conductor 15, the power supply electrode 11, the ground electrode 12, and the signal electrode 16 are formed of a metal thin film, for example, After a metal thin film is formed by sputtering, vacuum deposition or plating, it can be formed into a predetermined wiring pattern by photolithography.

このような、半導体素子６を搭載する多層配線基板１において、半導体素子６の電荷供給経路である電源配線４および接地配線５は抵抗やインダクタンス等の寄生要素を持つため電荷が供給される際に電圧降下や誘導起電力によるノイズ成分が電源配線４と接地配線５間の電位に発生し半導体素子６のスイッチング動作を不安定にするため、寄生要素を極力小さくするように電荷供給経路を物理的に短くする必要がある。 In such a multilayer wiring board 1 on which the semiconductor element 6 is mounted, the power supply wiring 4 and the ground wiring 5 which are the charge supply paths of the semiconductor element 6 have parasitic elements such as resistance and inductance, and therefore when charges are supplied. A noise component due to a voltage drop or induced electromotive force is generated in the potential between the power supply wiring 4 and the ground wiring 5 to make the switching operation of the semiconductor element 6 unstable. Therefore, the charge supply path is physically arranged so as to minimize the parasitic elements. Need to be shorter.

本発明の多層配線基板１において絶縁基板２の主面（裏面）には、電源電極１１および接地電極１２との各外周部に、側面どうしが対向し合うようにして形成された突出部分１４が形成され、突出部分１４は多層配線基板１内部の電源配線４および接地配線５と、互いに隣り合って配置された電源貫通導体９および接地貫通導体１０を介して接続される。この場合、電源貫通導体９の電流の方向（電源電極から電源配線に向かう給電）と、接地貫通導体１０の電流の方向（接地配線から接地電極に向かう接地）とは逆向きなので自己インダクタンスと相互インダクタンスを合わせたインダクタンス成分の低減に有効である。 In the multilayer wiring board 1 of the present invention, the main surface (back surface) of the insulating substrate 2 has protruding portions 14 formed on the outer peripheral portions of the power supply electrode 11 and the ground electrode 12 so that the side surfaces face each other. The formed projecting portion 14 is connected to the power supply wiring 4 and the ground wiring 5 inside the multilayer wiring substrate 1 through the power supply through conductor 9 and the ground through conductor 10 arranged adjacent to each other. In this case, since the direction of current in the power supply through conductor 9 (power feeding from the power supply electrode to the power supply wiring) and the direction of current in the ground through conductor 10 (grounding from the ground wiring to the ground electrode) are opposite, self-inductance and mutual This is effective in reducing the inductance component combined with the inductance.

また同時に、電源貫通導体９同士、および接地貫通導体１０同士は、それぞれ、面積の狭い電源電極１１や接地電極１２の範囲を越えて突出部分１４に形成して、隣接距離を従来よりも大きくすることができるため、電源貫通導体９同士あるいは接地貫通導体１０同士の相互インダクタンスの影響を弱めることができる。そのため、電源配線４と電源電極１１とを接続する電源貫通導体９、および接地配線５と接地電極１２とを接続する接地貫通導体１０に付随するインダクタンス成分を低減することが可能になる。 At the same time, the power supply through conductors 9 and the ground through conductors 10 are formed in the protruding portion 14 beyond the range of the power supply electrode 11 and the ground electrode 12 having a small area, respectively, so that the adjacent distance is larger than that of the conventional case. Therefore, the influence of the mutual inductance between the power supply through conductors 9 or between the ground through conductors 10 can be reduced. Therefore, it is possible to reduce the inductance component associated with the power supply through conductor 9 that connects the power supply wiring 4 and the power supply electrode 11 and the ground through conductor 10 that connects the ground wiring 5 and the ground electrode 12.

つまり、図５に示されるように多層配線基板４１の小型化に伴う外部電極の小径化によって電源電極４４および接地電極４５に複数接続される電源貫通導体４９同士および接地貫通導体４１０同士の間隔が、必然的に狭くなり貫通導体同士の相互インダクタンスの上昇によって自己インダクタンスと相互インダクタンスを合わせたインダクタンス成分の削減ができない場合においても、本発明においては図２に示されるように突出部分１４に貫通導体を配置することによって電源貫通導体４９同士あるいは接地貫通導体４１０同士の間隔を広くすることができ相互インダクタンスの影響を小さくすることができるため自己インダクタンスと相互インダクタンスを合わせたインダクタンス成分の削減が可能となる。 That is, as shown in FIG. 5, the distance between the power supply through conductors 49 and the ground through conductors 410 connected to the power supply electrode 44 and the ground electrode 45 due to the reduction in the diameter of the external electrode accompanying the downsizing of the multilayer wiring board 41 is achieved. Even in the case where it is inevitably narrowed and the inductance component of the self-inductance and the mutual inductance cannot be reduced due to the increase of the mutual inductance between the through conductors, in the present invention, as shown in FIG. Since the distance between the power supply through conductors 49 or the ground through conductors 410 can be widened and the influence of the mutual inductance can be reduced, the inductance component combining the self-inductance and the mutual inductance can be reduced. Become.

したがって、搭載される半導体素子６のスイッチング動作時に発生する同時スイッチングノイズを大幅に抑制して、半導体素子６の動作速度が高速化した場合でも、半導体素子６の動作を良好なものとすることが可能な多層配線基板１を提供することができる。 Therefore, the simultaneous switching noise generated during the switching operation of the mounted semiconductor element 6 is greatly suppressed, and even when the operation speed of the semiconductor element 6 is increased, the operation of the semiconductor element 6 can be improved. A possible multilayer wiring board 1 can be provided.

なお、突出部分１４に接続する電源貫通導体９および接地貫通導体１０は、隣り合う突出部分１４の間で互いに最接近するような位置で、それぞれ接続されていることが好ましいが、製造上の精度等に応じて、多少ずれていてもかまわない。 It should be noted that the power supply through conductor 9 and the ground through conductor 10 connected to the protruding portion 14 are preferably connected at positions that are closest to each other between the adjacent protruding portions 14. Depending on the situation, it may be slightly different.

このような突出部分１４は、例えば、電源電極９や接地電極１０と一体的に形成することができる。すなわち、突出部分１４は、タングステン（Ｗ），モリブデン（Ｍｏ），モリブデン−マンガン（Ｍｏ−Ｍｎ），銅（Ｃｕ），銀（Ａｇ）または銀−パラジウム（Ａｇ−Ｐｄ）等の金属粉末メタライズ、あるいは銅（Ｃｕ），銀（Ａｇ），ニッケル（Ｎｉ），クロム（Ｃｒ），チタン（Ｔｉ），金（Ａｕ）またはニオブ（Ｎｂ）やそれらの合金等の金属材料を用い、メタライズ法等の厚膜法や、薄膜法等の金属層形成手段により形成することができる。 Such a protruding portion 14 can be formed integrally with the power electrode 9 and the ground electrode 10, for example. That is, the protruding portion 14 is made of metal powder metallization such as tungsten (W), molybdenum (Mo), molybdenum-manganese (Mo-Mn), copper (Cu), silver (Ag), or silver-palladium (Ag-Pd). Alternatively, a metal material such as copper (Cu), silver (Ag), nickel (Ni), chromium (Cr), titanium (Ti), gold (Au), niobium (Nb) or an alloy thereof is used. It can be formed by a metal layer forming means such as a thick film method or a thin film method.

具体的には、Ｗの金属粉末メタライズで形成する場合であれば、電源電極９や接地電極１０となる金属ペーストを印刷する際に、印刷に用いる製版（版面）に、突出部１４となるようなパターンを形成しておくことにより、突出部１４となる金属ペーストを印刷する。これを焼成することにより、突出部１４を備える電源電極９や接地電極１０を形成することができる。 Specifically, in the case of forming with metal powder metallization of W, when printing the metal paste to be the power electrode 9 or the ground electrode 10, the protruding portion 14 is formed on the plate making (plate surface) used for printing. By forming a simple pattern, the metal paste that becomes the protrusion 14 is printed. By baking this, the power supply electrode 9 and the ground electrode 10 provided with the protrusions 14 can be formed.

この場合、突出部分１４は、電源貫通導体９と接地貫通導体１０とを有効に隣接させるために、電源電極１１に形成されるものと接地電極１２に形成されるものとが、互いに側面どうし、製法上、電気的な絶縁性等の特性が確保される範囲内で極力近接して配置されることが望ましい。 In this case, the protruding portion 14 is formed such that the one formed on the power electrode 11 and the one formed on the ground electrode 12 are adjacent to each other in order to effectively make the power supply through conductor 9 and the ground through conductor 10 adjacent to each other. In terms of the manufacturing method, it is desirable to arrange them as close as possible within a range in which characteristics such as electrical insulation are ensured.

例えば、電源電極１１，接地電極１２およびそれぞれの突出部分１４がＷの金属粉末メタライズで形成される場合であれば、突出部分１４の隣接間隔は（５０〜１００μｍ）程度に設定すればよい。 For example, if the power electrode 11, the ground electrode 12, and each protruding portion 14 are formed of W metal powder metallization, the adjacent interval between the protruding portions 14 may be set to about (50 to 100 μm).

なお、突出部分１４は、電源貫通導体９と接地貫通導体１０とを、極力狭い占有面積で隣接させるために、図示したような長楕円弧状のものや、細長い四角形状（長方形状，台形状等、図示せず）のものが適している。特に、ほぼ全長において幅が一定で、角部のないものが好ましい。 Note that the protruding portion 14 has a long elliptical arc shape as shown in the drawing or an elongated quadrangular shape (rectangular shape, trapezoidal shape, etc.) in order to make the power supply through conductor 9 and the grounding through conductor 10 adjacent to each other with an extremely small occupation area. (Not shown) is suitable. In particular, it is preferable that the width is almost constant over the entire length and there is no corner.

また、本発明において、突出部分１４が、電源電極１１および接地電極１２の各外周面に複数個ずつ形成されているのがよい。この場合には、各突出部分１４のインダクタンスに起因して電荷が供給される経路のインダクタンスが増加することを防止し、半導体素子６の動作をより良好にすることができる。すなわち、突出部分１４の持つインダクタンス成分が電源電極１１の突出部分１４と接地電極１２間の突出部分１４の相互インダクタンスによって相殺されて低減することができる。そのため、突出部分１４のインダクタンスに起因して基準電位の変動が誘発されることは防止される。また、突出部分１４が複数個形成されることによって並列接続になるため、突出部分１４のインダクタンスはより削減される。また、抵抗成分（直流抵抗）もさらに低減される。したがって、インダクタンス成分の削減によって同時スイッチングノイズがさらに抑制されるため、より一層、搭載される半導体素子の動作について、誤動作が抑制された良好な多層配線基板とすることができる。 In the present invention, it is preferable that a plurality of protruding portions 14 are formed on each outer peripheral surface of the power supply electrode 11 and the ground electrode 12. In this case, it is possible to prevent the inductance of the path through which charges are supplied due to the inductance of each protruding portion 14 from increasing, and to improve the operation of the semiconductor element 6. That is, the inductance component of the protruding portion 14 can be reduced by canceling out the mutual inductance of the protruding portion 14 between the protruding portion 14 of the power supply electrode 11 and the ground electrode 12. Therefore, it is possible to prevent the reference potential from being changed due to the inductance of the protruding portion 14. In addition, since the plurality of protruding portions 14 are formed, parallel connection is established, and thus the inductance of the protruding portion 14 is further reduced. Further, the resistance component (DC resistance) is further reduced. Therefore, since the simultaneous switching noise is further suppressed by reducing the inductance component, it is possible to obtain a good multilayer wiring board in which malfunction is further suppressed with respect to the operation of the mounted semiconductor element.

このような電源電極１１および接地電極１２は、例えば、図２のように、縦横に交互に電源電極１１と接地電極１２とが配置されるようにし、各電源電極１１から隣接する接地電極１２へ向かって突出部分１４が延出しているとともに、各接地電極１２から隣接する電源電極１１へ向かって突出部分１４が延出しているのがよい。縦横に配置された電源電極１１と接地電極１２の突出部分１４全てが効率よく対向するため電源配線層４と全ての電源電極１１とを接続する全ての電源貫通導体９および接地配線層５と全ての接地電極１２とを接続する全ての接地貫通導体１０のインダクタンス成分を削減できるため、同時スイッチングノイズの抑制をより有効に行なうことができる。 For example, as shown in FIG. 2, the power supply electrode 11 and the ground electrode 12 are arranged such that the power supply electrode 11 and the ground electrode 12 are alternately arranged in the vertical and horizontal directions, and from each power supply electrode 11 to the adjacent ground electrode 12. It is preferable that the protruding portion 14 extends toward the power source electrode 11 adjacent to each ground electrode 12 and the protruding portion 14 extends toward the adjacent power supply electrode 11. Since all the protruding portions 14 of the power supply electrode 11 and the ground electrode 12 arranged vertically and horizontally are efficiently opposed to each other, all the power supply through conductors 9 and all the ground wiring layers 5 that connect the power supply wiring layer 4 and all the power supply electrodes 11 are used. Since the inductance component of all the ground through conductors 10 connected to the ground electrode 12 can be reduced, simultaneous switching noise can be more effectively suppressed.

また、突出部分１４の厚みは電源電極１１および接地電極１２の厚みと同程度から二倍程度の厚みにすることが好ましい。この場合、突出部分１４の自己インダクタンスを低減できかつ実装信頼性を著しく低下させることがない。 Further, it is preferable that the thickness of the protruding portion 14 is approximately the same as or twice the thickness of the power supply electrode 11 and the ground electrode 12. In this case, the self-inductance of the protruding portion 14 can be reduced and the mounting reliability is not significantly reduced.

また、突出部分１４の側面の形状は垂直であることが好ましい。この場合、電源電極１１および接地電極１２のそれぞれの突出部分１４が対向する実効的な面積が増大し相互インダクタンスを増大でき、かつそれぞれの突出部分１４の自己インダクタンスを低減できるため、同時スイッチングノイズの抑制をより有効に行なうことができる。 Moreover, it is preferable that the shape of the side surface of the protrusion part 14 is vertical. In this case, the effective area where the protruding portions 14 of the power supply electrode 11 and the ground electrode 12 face each other is increased, the mutual inductance can be increased, and the self-inductance of each protruding portion 14 can be reduced. Suppression can be performed more effectively.

また、図３に示されるよう電源電極１１および接地電極１２の突出部分１４は被覆用の絶縁体１３で被覆されていることが好ましい。この場合、突出部分１４がアンカーの役割を果たし、絶縁基板２に対する電源電極１１および接地電極１２の接合強度を向上することができるため電源電極１１と接地電極１２のはがれ等による実装信頼性の低下を効果的に抑止できる。 Further, as shown in FIG. 3, the protruding portions 14 of the power supply electrode 11 and the ground electrode 12 are preferably covered with a covering insulator 13. In this case, the protruding portion 14 serves as an anchor, and the bonding strength of the power supply electrode 11 and the ground electrode 12 to the insulating substrate 2 can be improved. Therefore, the mounting reliability is reduced due to peeling of the power supply electrode 11 and the ground electrode 12. Can be effectively deterred.

また、絶縁体１３は、突出部分１４の表面から隣り合う絶縁基板２の表面にかけて一体的に覆うように形成されていることがより好ましい。この場合、突出部分１４をより強固に絶縁基板２に接合させておくことができるので、絶縁基板２に対する電源電極１１および接地電極１２の接合強度をさらに向上することができる。そのため、電源電極１１と接地電極１２のはがれ等による実装信頼性の低下をより効果的に抑止できる。 Moreover, it is more preferable that the insulator 13 is formed so as to be integrally covered from the surface of the protruding portion 14 to the surface of the adjacent insulating substrate 2. In this case, since the protruding portion 14 can be bonded to the insulating substrate 2 more firmly, the bonding strength of the power supply electrode 11 and the ground electrode 12 to the insulating substrate 2 can be further improved. For this reason, it is possible to more effectively prevent a decrease in mounting reliability due to peeling of the power electrode 11 and the ground electrode 12.

絶縁体１３は、酸化アルミニウム質焼結体や窒化アルミニウム質焼結体，炭化珪素質焼結体，窒化珪素質焼結体，ムライト質焼結体またはガラスセラミックス等の無機絶縁材料、ポリイミド，エポキシ樹脂，フッ素樹脂，ポリノルボルネンまたはベンゾシクロブテン等の有機絶縁材料、あるいはセラミック粉末等の無機絶縁物粉末をエポキシ樹脂等の熱硬化性樹脂で結合して成る複合絶縁材料等により形成される。 The insulator 13 is an inorganic insulating material such as an aluminum oxide sintered body, an aluminum nitride sintered body, a silicon carbide sintered body, a silicon nitride sintered body, a mullite sintered body, or a glass ceramic, polyimide, epoxy. It is made of an organic insulating material such as resin, fluororesin, polynorbornene or benzocyclobutene, or a composite insulating material formed by bonding an inorganic insulating powder such as ceramic powder with a thermosetting resin such as epoxy resin.

絶縁体１３は、例えば酸化アルミニウム質焼結体粉末に適当な有機バインダや溶剤等を添加混合して得たセラミックペーストを、絶縁層２ｅ上の誘電体１５の表面に所定のパターンで印刷塗布し、これをセラミックグリーンシートの積層体とともに焼成することによって形成することができる。 The insulator 13 is formed by, for example, printing and applying a ceramic paste obtained by adding and mixing an appropriate organic binder, solvent, or the like to an aluminum oxide sintered powder in a predetermined pattern on the surface of the dielectric 15 on the insulating layer 2e. It can be formed by firing together with a laminate of ceramic green sheets.

なお、絶縁体１３は、突出部１４の表面から、それに隣接する電源電極１１や接地電極１２の露出面の外縁部にかけて一体的に被覆するようにしてもよい。この場合、接合強度を向上することができ、信頼性をさらに向上させることができる。 The insulator 13 may be integrally covered from the surface of the protruding portion 14 to the outer edge portion of the exposed surface of the power supply electrode 11 and the ground electrode 12 adjacent thereto. In this case, the bonding strength can be improved and the reliability can be further improved.

以上より、半導体素子６のスイッチング動作時に発生する同時スイッチングノイズを効果的に抑制することができ、その結果半導体素子６の作動性を良好なものとすることにある。 As described above, the simultaneous switching noise generated during the switching operation of the semiconductor element 6 can be effectively suppressed, and as a result, the operability of the semiconductor element 6 is improved.

また、多層配線基板１は、半導体素子６のみに限らず、チップ抵抗，薄膜抵抗，コイルインダクタ，クロスインダクタ，チップキャパシターまたは電解キャパシター等を搭載して、電子回路モジュール等を構成してもよい。 In addition, the multilayer wiring board 1 is not limited to the semiconductor element 6 and may be configured as an electronic circuit module by mounting a chip resistor, a thin film resistor, a coil inductor, a cross inductor, a chip capacitor, or an electrolytic capacitor.

また、各絶縁層２ａ〜２ｆの平面視における形状は、正方形状や長方形状の他に、菱形状，六角形状または八角形状等の形状であってもよい。 Further, the shape of each of the insulating layers 2a to 2f in a plan view may be a rhombus shape, a hexagonal shape, an octagonal shape, or the like in addition to a square shape or a rectangular shape.

そして、このような本発明の多層配線基板１は、半導体素子収納用パッケージ等の電子部品収納用パッケージや電子部品搭載用基板、多数の半導体素子６が搭載されるいわゆるマルチチップモジュールやマルチチップパッケージ、あるいはマザーボード等として使用される。 Such a multilayer wiring board 1 of the present invention includes an electronic component storage package such as a semiconductor element storage package, an electronic component mounting substrate, a so-called multichip module or multichip package on which a large number of semiconductor elements 6 are mounted. Or used as a motherboard.

本発明の図１の構成の多層配線基板１を以下のようにして作製した。酸化アルミニウム質焼結体から成る各厚みが０．２ｍｍの絶縁層２ａ〜２ｆを上述したセラミックグリーンシート積層法によって積層し形成することにより、絶縁基板２を作製した。このとき、信号配線群３、電源導体４、接地導体５、電源貫通導体９、接地貫通導体１０、電源電極１１および接地電極１２を、上述の銅粉末メタライズで形成した。 A multilayer wiring board 1 having the configuration shown in FIG. 1 according to the present invention was produced as follows. The insulating substrate 2 was produced by laminating and forming the insulating layers 2a to 2f each made of an aluminum oxide sintered body having a thickness of 0.2 mm by the ceramic green sheet laminating method described above. At this time, the signal wiring group 3, the power supply conductor 4, the ground conductor 5, the power supply through conductor 9, the ground through conductor 10, the power supply electrode 11, and the ground electrode 12 were formed of the above-described copper powder metallization.

そして、この場合、図２に示すように、比誘電率が５．２の絶縁基板２ｅに、直径０．５ｍｍの電源電極１１と接地電極１２が０．８ｍｍ間隔で形成され、電源電極１１と接地電極１２の外周部には、０．２ｍｍの長さを持つ突出部が形成され、突出部には直径０．７５ｍｍの電源貫通導体９と接地貫通導体１０が接続されている。 In this case, as shown in FIG. 2, the power supply electrode 11 and the ground electrode 12 having a diameter of 0.5 mm are formed on the insulating substrate 2 e having a relative dielectric constant of 5.2 at intervals of 0.8 mm. A protrusion having a length of 0.2 mm is formed on the outer periphery of the ground electrode 12, and a power supply through conductor 9 and a grounding through conductor 10 having a diameter of 0.75 mm are connected to the protrusion.

上記構成の多層配線基板１について、電源電極１１と接地電極１２および電源貫通導体９と接地貫通導体１０とによって形成されるインダクタンスは２０ｐＨとなる。 In the multilayer wiring board 1 having the above-described configuration, the inductance formed by the power supply electrode 11 and the ground electrode 12 and the power supply through conductor 9 and the ground through conductor 10 is 20 pH.

また、比較例１として、電源電極１１と電極１２に突出部が形成されない場合、電源電極１１と接地電極１２および電源貫通導体９と接地貫通導体１０とによって形成されるインダクタンスは５０ｐＨとなる。この構成において電源電極１１と接地電極１２で発生する同時スイッチングノイズ動作電圧は、本発明の構成時を１とすると２．５となり増大する。 Further, as Comparative Example 1, when no protrusion is formed on the power supply electrode 11 and the electrode 12, the inductance formed by the power supply electrode 11, the ground electrode 12, the power supply through conductor 9, and the ground through conductor 10 is 50 pH. In this configuration, the simultaneous switching noise operating voltage generated at the power supply electrode 11 and the ground electrode 12 increases to 2.5 when the configuration of the present invention is 1.

なお、本発明は上記の実施の形態の例および実施例に限定されるものではなく、本発明の要旨を逸脱しない範囲で種々の変更を行なうことは何ら差し支えない。例えば、半導体素子６と多層配線基板１を接続するために導体バンプ７が搭載される電極パッド８のうち電源電極１１用のものと接地電極１２用のものとの間で、絶縁基板２の外面（表面側）にも高誘電体１５を配置してもよい。 The present invention is not limited to the above-described embodiments and examples, and various modifications can be made without departing from the scope of the present invention. For example, the outer surface of the insulating substrate 2 between the electrode pads 8 on which the conductor bumps 7 are mounted for connecting the semiconductor element 6 and the multilayer wiring substrate 1 between the power electrode 11 and the ground electrode 12. The high dielectric 15 may also be disposed on the (front side).

本発明の多層配線基板の実施の形態の一例を示す断面図である。It is sectional drawing which shows an example of embodiment of the multilayer wiring board of this invention. 本発明の多層配線基板の実施の形態の一例を示す要部拡大平面図である。It is a principal part enlarged plan view which shows an example of embodiment of the multilayer wiring board of this invention. 本発明の多層配線基板の実施の形態の一例を示す要部拡大断面図である。It is a principal part expanded sectional view which shows an example of embodiment of the multilayer wiring board of this invention. 従来の多層配線基板の一例を示す断面図である。It is sectional drawing which shows an example of the conventional multilayer wiring board. 従来の多層配線基板の一例を示す平面図であるIt is a top view which shows an example of the conventional multilayer wiring board.

Explanation of symbols

１・・・多層配線基板
２・・・絶縁基板
２ａ〜２ｆ・・・絶縁層
３・・・信号配線群
４・・・電源配線層
５・・・接地配線層
６・・・半導体素子
７・・・導体バンプ
８・・・電極パッド
９・・・電源貫通導体
１０・・・接地貫通導体
１１・・・電源電極
１２・・・接地電極
１３・・・絶縁体
１４・・・突出部分
１５・・・信号貫通導体
１６・・・信号電極 DESCRIPTION OF SYMBOLS 1 ... Multilayer wiring board 2 ... Insulating board 2a-2f ... Insulating layer 3 ... Signal wiring group 4 ... Power supply wiring layer 5 ... Ground wiring layer 6 ... Semiconductor element 7- ··· Conductor bump 8 ··· Electrode pad 9 ··· Power supply through conductor 10 ··· Ground through conductor 11 ··· Power supply electrode 12 ··· Ground electrode 13 ··· Insulator 14 ··· Projecting portion 15 ..Signal through conductor 16 ... Signal electrode

Claims

An insulating substrate formed by laminating a plurality of insulating layers;
Power supply wiring and ground wiring disposed between the insulating layers;
A power supply electrode and a ground electrode formed on the main surface of the insulating substrate so as to be adjacent to each other;
Projecting portions projecting outward from the outer peripheral surfaces of the power supply electrode and the ground electrode;
A power supply through conductor and a ground through conductor that are formed from the protruding portions of the power supply electrode and the ground electrode to the power supply wiring and the ground wiring, and connect the power supply electrode and the ground electrode to the power supply wiring and the ground wiring, respectively.
The protruding portion of the power supply electrode and the protruding portion of the ground electrode are arranged with their side surfaces facing each other, and the power supply through conductor and the ground through conductor are arranged adjacent to each other. Multilayer wiring board.

The multilayer wiring board according to claim 1, wherein a plurality of the protruding portions are formed on each outer peripheral surface of the power supply electrode and the ground electrode.

The multilayer wiring board according to claim 1 or 2, wherein an insulator is formed so as to be integrally covered from a main surface of the protruding portion to a surface of the insulating substrate.

4. The multilayer wiring board according to claim 1, wherein the insulator is formed so as to be integrally covered from a surface of the protruding portion to a surface of the adjacent insulating substrate. 5. .