JP5014380B2 - Multilayer substrate and semiconductor device - Google Patents

Description

  The present invention relates to a multilayer substrate on which a semiconductor element is mounted and a semiconductor device using the multilayer substrate.

  In recent years, as the operation speed of semiconductor elements has been increased, a plurality of semiconductor element switching operations have occurred simultaneously in a multilayer wiring board (hereinafter also referred to as a multilayer board) on which semiconductor elements such as LSI and IC are mounted. In this case, the power supply potential and the ground potential of the semiconductor element fluctuate, and as a result, a problem of simultaneous switching noise that causes malfunction of the semiconductor element occurs. In addition, when a plurality of semiconductor element switching operations occur simultaneously, there is a problem of electromagnetic interference (EMI) noise in which electromagnetic waves due to switching noise interfere with other electronic devices.

  Therefore, for these problems, it is possible to suppress resistance and inductance generated in a current path from a multilayer substrate called a motherboard installed in a server device and a personal computer of a communication system such as the Internet, It is effective to provide an electric capacity (capacitor) in the current path to stabilize the power supply potential and the ground potential, and to provide a decoupling capacitor in the current path to attenuate noise such as switching noise. . As a method of forming such a capacitor or decoupling capacitor, specifically, a planar conductor having a power supply potential (commonly referred to as “solid conductor” or “solid plane”) and a planar conductor having a ground potential are used. There is a method in which each counter electrode of a capacitor is formed inside a multilayer substrate.

  In addition, as a multilayer substrate having a decoupling capacitor, a projection is provided on the outer edge of the power supply potential wiring and the ground potential wiring in a plan view of the multilayer substrate in a region other than the corner portion. A configuration in which the potential wiring and the ground potential wiring are connected to a common decoupling capacitor provided on a multilayer substrate is known (for example, see Patent Document 1).

  With this configuration, the cross-sectional area of the current path flowing through the power supply potential wiring and the ground potential wiring can be increased, so that the resistance and inductance generated in the current path can be reduced, and two solid planes facing each other This makes it possible to form a capacitor between the power supply potential wiring and the ground potential wiring, so that the power supply voltage can be supplied from the capacitance forming portion to the semiconductor element, so that the current path is shortened, and the resistance associated with the path and Since the inductance can be suppressed, the influence of simultaneous switching noise can be suppressed. Further, by collecting the noise flowing into the power supply potential wiring and the ground potential wiring in the protruding portion and flowing them through the decoupling capacitor, it is possible to reduce electromagnetic interference noise due to current resonance.

  As another configuration for reducing the resistance and inductance generated in the current path, a multilayer substrate having the following configuration has been proposed. A plurality of insulating layers, a power supply conductor layer formed between the insulation layers, a ground conductor layer formed between different insulation layers from the insulation layer formed with the power supply conductor layer, and a plurality of signal terminals on the outer periphery of the lower surface A base body having a mounting portion on the upper surface for mounting a semiconductor element having a plurality of power supply terminals and a plurality of ground terminals in the central portion, and a power supply conductor layer formed from the central portion of the base mounting portion toward the lower surface side of the base body A plurality of power supply through conductors electrically connected to each other and a plurality of ground through conductors electrically connected to the ground conductor layer, and a plurality of ground through conductors formed from the outer peripheral portion of the base mounting portion toward the lower surface side of the base The plurality of power supply through conductors and the plurality of ground through conductors are multilayer boards that are alternately arranged so as to be adjacent to the mounting portion in plan view.

JP 2008-251805 A

  However, in the above conventional technique, the following problems have arisen due to the recent increase in operating frequency of semiconductor elements.

  By providing a decoupling capacitor in which a planar conductor having a power supply potential and a planar conductor having a ground potential are formed as two opposing electrodes on the power supply potential wiring and the ground potential wiring inside the multilayer substrate on which the semiconductor element is mounted. In the case of the method of suppressing the simultaneous switching noise, when the signal is transmitted through the signal wiring, the signal is supplied to the power supply potential wiring and the ground potential wiring centering on the portion facing the signal wiring of the power supply potential wiring and the ground potential wiring. The return current due to electromagnetic radiation of the signal transmitted through the wiring is superimposed. That is, a signal transmitted through the signal wiring becomes noise and is superimposed on the power supply potential wiring and the ground potential wiring.

  At this time, part of the signal (return current) generated in the power supply potential wiring and the ground potential wiring is widely diffused and flows in the planar conductor of the decoupling capacitor, so the wavelength and surface of the harmonic component of the diffused return current The resonance phenomenon occurs when the electrical length of the conductors approaches. As a result, simultaneous switching noise and EMI noise are generated by the resonance phenomenon generated in the planar conductor, or noise generated by the resonance of the planar conductor interferes with and is superimposed on the signal wiring, thereby degrading the transmission characteristics of the signal wiring. cause. Therefore, there is a problem that it is difficult to operate the semiconductor element stably.

  In the case of the multilayer substrate described in Patent Document 1, even if resonance is suppressed by providing a protrusion, the magnitudes of resistance and inductance generated in the power supply potential wiring and the ground potential wiring do not change. There is a problem that noise cannot be reduced, and as a result, it is difficult to stably operate the semiconductor element.

  Further, in a multilayer substrate in which a plurality of power supply through conductors and a plurality of ground through conductors are alternately arranged so as to be adjacent to each other in a plan view, the power supply through conductor and the ground through conductor are adjacent to each other. Thus, the mutual inductance can be increased, and the total inductance of the current paths can be reduced.

  The total inductance (also referred to as loop inductance) is represented by Lr = Ls + Lgnd−2 × Lm (Lr is loop inductance, Ls is power supply conductor layer inductance, Lgnd is ground conductor layer inductance, and Lm is mutual inductance). The

  However, even if the mutual inductance can be increased, the inductance of the power supply conductor layer and the inductance of the ground conductor layer cannot be reduced, and as a result, the effect of reducing the loop inductance is insufficient.

  When the resistance and inductance to a part of the signal (return current) flowing through the power supply conductor layer and the ground conductor layer are increased, the drive signal attenuation is increased when the drive voltage of the semiconductor element is lowered, and the noise of the drive signal is increased. Since the margin for the noise is reduced and the influence of noise on the drive signal is increased, the semiconductor element is liable to malfunction.

  Accordingly, the present invention has been devised to solve the above problems, and its purpose is to superimpose a return current due to electromagnetic radiation of a signal transmitted through the signal wiring on the power supply potential wiring and the ground potential wiring. Even if the power supply potential wiring and the ground potential wiring are reduced, the simultaneous switching noise can be reduced by reducing the resistance and the inductance generated in the power supply potential wiring and the ground potential wiring. A substrate and a semiconductor device using the same are provided.

  The multilayer substrate of the present invention has a plurality of insulating layers and a power conductor layer formed between the insulating layers, and a ground conductor layer formed between the insulating layers different from the insulating layer on which the power conductor layers are formed, A base body having a mounting portion on the top surface for mounting a semiconductor element having a plurality of signal terminals on the outer peripheral portion of the lower surface and a plurality of power supply terminals and a plurality of ground terminals in the central portion, and from the central portion of the mounting portion to the base body A plurality of power supply through conductors electrically connected to the power supply conductor layer, a plurality of ground through conductors electrically connected to the ground conductor layer, and the mounting of the base body. A plurality of signal through conductors formed from the outer periphery of the unit toward the lower surface side of the base, and the plurality of power supply through conductors and the plurality of ground through conductors of the mounting unit in plan view The power supply conductor layers are arranged in an annular shape alternately from the center toward the outer peripheral side, and the power supply conductor layer includes an annular power supply conductor layer non-forming portion including a portion through which the plurality of grounding through conductors arranged in a ring shape penetrate in a plan view. The grounding conductor layer has an annular grounding conductor layer non-forming portion including a portion through which the plurality of power supply through conductors arranged in a ring shape in a plan view passes. It is.

  In the multilayer substrate of the present invention, in the above configuration, the plurality of power supply through conductors form a group for each of a plurality of types of power supply potentials, and each group includes a plurality of the ground through conductors between the groups. Is arranged in an annular shape from the center of the mounting portion toward the outer periphery in a plan view.

  Further, the multilayer substrate of the present invention is characterized in that, in the above configuration, a plurality of the ground through conductors are arranged in a ring shape on the outermost periphery of the central portion of the mounting portion in plan view.

  A semiconductor device of the present invention includes the multilayer substrate of the present invention and a semiconductor element mounted on the mounting portion of the multilayer substrate.

  According to the multilayer substrate of the present invention, the power supply conductor layer formed between the plurality of insulation layers and the insulation layers, the ground conductor layer formed between the insulation layers different from the insulation layer formed with the power supply conductor layers, A base body having a mounting portion for mounting a semiconductor element having a plurality of signal terminals on the outer peripheral portion and a plurality of power supply terminals and a plurality of ground terminals in the central portion, and from the central portion of the base mounting portion toward the lower surface side of the base body. A plurality of power supply through conductors electrically connected to the power supply conductor layer and a plurality of ground through conductors electrically connected to the ground conductor layer, and a lower surface side of the substrate from the outer periphery of the substrate mounting portion A plurality of signal through conductors and a plurality of power through conductors and a plurality of ground through conductors are alternately arranged in an annular shape from the center of the mounting portion toward the outer periphery in a plan view. Oh The power supply conductor layer has an annular power supply conductor layer non-forming portion including a portion through which a plurality of ground through conductors arranged in a ring shape in plan view penetrates, and the ground conductor layer is arranged in a ring shape in plan view Since there is an annular ground conductor layer non-forming portion including a portion through which a plurality of power supply through conductors penetrated, the current path between the power supply through conductors is short and the current width is large. The resistance and inductance in the layer is reduced. In addition, since the current path between the ground through conductors is short and the current width is large, the resistance and inductance in the ground conductor layer are small. As a result, the simultaneous switching noise is effectively suppressed, so that the malfunction of the semiconductor element is suppressed and the operability of the semiconductor element can be improved.

  In addition, the power supply conductor layer has an annular power supply conductor layer non-forming portion including a portion through which a plurality of ground through conductors arranged in a ring shape in a plan view passes, and the ground conductor layer has a ring shape in a plan view. Since the ring-shaped ground conductor layer non-forming portion including the portion through which the plurality of arranged power supply through conductors penetrates is provided, fluctuations in the voltage level of the power supply voltage and the ground voltage (commonly referred to as bounce) can be reduced. it can.

  In other words, the power supply conductor layer, which is a substantially planar conductor, has a part of the signal flowing from the power supply through conductor repeatedly diffused and reflected in the plane of the power supply conductor layer, and as a result, the voltage level of the power supply voltage fluctuates. However, if the annular power supply conductor layer non-forming portion is formed, the area of the continuous planar portion in the power supply conductor layer is reduced, and the degree of diffusion and reflection of a part of the signal is reduced. Therefore, fluctuations in the voltage level of the power supply voltage can be suppressed. Similarly, fluctuations in the voltage level of the ground voltage can be suppressed.

  In the multilayer substrate of the present invention, the plurality of power supply through conductors form a group for each of a plurality of types of power supply potentials, and each group has a plurality of grounding through conductors sandwiched between the groups in plan view. When arranged in an annular shape from the center of the mounting portion toward the outer peripheral side, simultaneous switching noise can be effectively suppressed for a plurality of types of power supply potentials, and fluctuations in the voltage level of the power supply voltage can be suppressed.

  In the multilayer substrate of the present invention, when a plurality of grounding through conductors are arranged in an annular shape on the outermost periphery of the central portion of the mounting portion in plan view, the plurality of grounding through conductors have the effect of electromagnetic shielding (shielding). Therefore, it is possible to effectively suppress noise of electromagnetic waves entering from the outside, and the operability of the semiconductor element can be improved.

  In addition, since the semiconductor device of the present invention includes the multilayer substrate of the present invention and a semiconductor element mounted on the mounting portion of the multilayer substrate, the mounted semiconductor element has good operating characteristics. .

It is sectional drawing which shows an example of embodiment of the multilayer substrate of this invention. It is a top view of the insulating layer in which the power supply penetration conductor, the grounding penetration conductor, and the signal penetration conductor in the multilayer substrate shown in FIG. 1 were formed. It is a top view of the insulating layer in which the ground conductor layer which has a cyclic | annular ground conductor layer non-formation part in the multilayer substrate shown in FIG. 1 was formed.

  Hereinafter, an example of an embodiment of a multilayer substrate (multilayer wiring substrate) of the present invention will be described with reference to the accompanying drawings. FIG. 1 is a cross-sectional view of a multilayer substrate according to an example of the present embodiment. FIG. 2 is a plan view of an insulating layer in which the power supply through conductor, the ground through conductor, and the signal through conductor are formed in the multilayer substrate of FIG. FIG. 3 is a plan view of an insulating layer in which a ground conductor layer having a ring-shaped ground conductor layer non-forming portion is formed in the multilayer substrate shown in FIG.

  The multilayer substrate 1 according to the present embodiment includes a plurality of insulating layers 2a to 2j and a power source conductor layer 7 formed between the insulating layers 2b and 2c, and an insulation different from that between the insulating layers 2b and 2c where the power source conductor layer 7 is formed. A mounting portion 1a having a ground conductor layer 8 formed between the layers 2a and 2b and mounting a semiconductor element 3 having a plurality of signal terminals on the outer peripheral portion of the lower surface and a plurality of power supply terminals and a plurality of ground terminals in the central portion. And a plurality of power supply through conductors 10 and ground conductors electrically connected to the power supply conductor layer 7 formed from the central portion of the mounting portion 1a of the substrate 20 toward the lower surface side of the substrate 20. A plurality of grounding through conductors 11 electrically connected to the layer 8, and a plurality of signal through conductors 12 formed from the outer peripheral portion of the mounting portion 1a of the base body 20 toward the lower surface side of the base body 20, Multiple power feedthroughs 10 and multiple grounds The through conductors 11 are alternately arranged in an annular shape from the center of the mounting portion 1a in the plan view toward the outer peripheral side, and the power supply conductor layer 7 is penetrated by a plurality of grounding through conductors 11 arranged in an annular shape in the plan view. The grounding conductor layer 8 includes a portion where the plurality of power supply through conductors 10 arranged in a ring shape in plan view penetrates the grounding conductor layer 8. It has a forming part.

  With the above configuration, since the current path between the power supply through conductors 10 is short and the current width is large, the resistance and inductance in the power supply conductor layer 7 are small. Further, since the current path between the ground through conductors 11 is short and the current width is increased, the resistance and inductance in the ground conductor layer 8 are reduced. As a result, the simultaneous switching noise is effectively suppressed, so that the malfunction of the semiconductor element 3 is suppressed and the operability of the semiconductor element 3 can be improved.

  Further, the power supply conductor layer 7 has an annular power supply conductor layer non-forming portion including a portion through which a plurality of grounding through conductors 11 arranged in a ring shape in a plan view passes, and the ground conductor layer 8 has a plan view. Since there is a ring-shaped ground conductor layer non-forming portion including a portion through which a plurality of power supply through conductors 10 arranged in a ring shape penetrate, fluctuations in the voltage level of the power supply voltage and the ground voltage (commonly called bounces) Can be reduced.

  That is, the power supply conductor layer 7 that is a substantially planar conductor repeats diffusion and reflection of a part of the signal flowing from the power supply through conductor 10 within the surface of the power supply conductor layer 7, and as a result, the voltage level of the power supply voltage is increased. If the annular power supply conductor layer non-forming portion is formed, the area of the continuous planar portion in the power supply conductor layer 7 is reduced, and the degree of diffusion and reflection of a part of the signal is reduced. Get smaller. Therefore, fluctuations in the voltage level of the power supply voltage can be suppressed. Similarly, fluctuations in the voltage level of the ground voltage can be suppressed.

  The multilayer substrate 1 according to the present embodiment is electrically connected to an electrode pad 6 on the upper surface side that is electrically connected to the semiconductor element 3 formed on the upper surface, an external driving device formed on the lower surface, wiring on the printed wiring board, and the like. The electrode pad 13 on the lower surface side, the plurality of insulating layers 2, the wiring conductor layer, and the through conductor are connected to each other. The insulating layer 2 is a general term for the plurality of insulating layers 2a to 2j. The electrode pads 13 on the lower surface side are connected to external connection conductor bumps 14 for electrical connection to an external driving device or the like.

  The wiring conductor layer of the multilayer substrate 1 includes a power source conductor layer 7 formed between the insulating layers 2b and 2c, a ground conductor layer 8 formed between the insulating layers 2a and 2b, and a signal formed between the insulating layers 2g and 2h. A conductor layer 9 is included. The through conductor includes a power supply through conductor 10 that electrically connects the power supply terminal of the semiconductor element 3 and the power supply conductor layer 7, a grounding through conductor 11 that electrically connects the ground terminal of the semiconductor element 3 and the ground conductor layer 8, A signal through conductor 12 that electrically connects the signal terminal of the semiconductor element 3 and the signal conductor layer 9 is included.

  In the semiconductor element 3, an electrode pad 4 electrically connected to the upper surface side electrode pad 6 of the multilayer substrate 1 is formed on the lower surface, and the upper surface side electrode pad 6 and the electrode pad 4 are connected via a conductor bump 5. Electrically connected.

  Moreover, each of the insulating layers 2a to 2j may further include a plurality of insulating layers. That is, each of the insulating layers 2a to 2f may be formed by stacking a plurality of thinner insulating layers.

  In the multilayer substrate 1 according to the present embodiment, the insulating layers 2a to 2j are made of an aluminum oxide sintered body, an aluminum nitride sintered body, a silicon carbide sintered body, a silicon nitride sintered body, and a mullite sintered body. Or it consists of inorganic insulating materials, such as glass ceramics. The insulating layers 2a to 2j are formed by a method such as a ceramic green sheet lamination method or an extrusion molding method.

  The insulating layer 2 is produced as follows using an inorganic insulating material. When the inorganic insulating material is made of, for example, an aluminum oxide sintered body, first, an appropriate organic binder and solvent are added to and mixed with raw material powders such as aluminum oxide, silicon oxide, calcium oxide or magnesium oxide to form a slurry. This is formed into a sheet by a doctor blade method, a calendar method, a reverse coater method or the like to obtain a ceramic green sheet. Then, a conductive paste serving as each wiring conductor layer and electrode pad is printed and applied to the ceramic green sheet in a predetermined pattern, and these are laminated to form a laminate. Finally, this laminate is reduced in a reducing atmosphere. Manufactured by firing at a temperature of 1600 ° C.

  The insulating layer 2 is formed by mixing an organic insulating material such as polyimide, epoxy resin, fluororesin, polynorbornene or benzocyclobutene, or inorganic insulating powder such as ceramic powder in a thermosetting resin such as epoxy resin. You may consist of electrically insulating materials, such as a composite insulating material.

  For example, when the insulating layer 2 is made of a composite insulating material, first, a thermosetting epoxy resin mixed with ceramic powder made of an aluminum oxide sintered body, or a glass epoxy obtained by impregnating a glass fiber woven cloth with an epoxy resin. A liquid resin precursor is applied to the upper surface of the insulating layer made of resin by a spin coat method, a curtain coat method, or the like, and this is preliminarily cured. Next, a wiring conductor layer is formed on the main surface of the insulating layer 2 by a thin film forming method such as an electroless plating method or a vapor deposition method and a photolithography method, and a plurality of insulating layers 2 are laminated to a temperature of about 170 ° C. The substrate 20 is produced by heat curing at The thickness of the substrate 20 is set so as to satisfy the conditions such as mechanical strength and electrical characteristics corresponding to the required specifications according to the characteristics of the material used.

  The electrode pads 4, 6, 13, the power supply conductor layer 7, the ground conductor layer 8, the signal conductor layer 9, the power supply through conductor 10, the ground through conductor 11, and the signal through conductor 12 are, for example, tungsten (W), molybdenum (Mo) , Molybdenum-manganese (Mo-Mn) alloy, copper (Cu), silver (Ag) or silver-palladium (Ag-Pd) alloy conductor layer, or copper (Cu), silver (Ag), nickel (Ni) , Chromium (Cr), titanium (Ti), gold (Au) or niobium (Nb) conductor layer, or a conductor layer thereof.

  Examples of the method for forming the conductor layer include a thick film method and a thin film formation method. For example, when the signal conductor layer 9 is formed by a thick film method, a conductive paste obtained by adding and mixing a suitable organic binder and solvent to Cu powder is printed and applied in a predetermined pattern on a ceramic green sheet. It can be formed by laminating a plurality of ceramic green sheets to form a laminate and firing.

  The conductor layer can be reduced in resistance and impedance by increasing the thickness of the conductor layer to such an extent that a large step is not formed at the end of the conductor layer when the ceramic green sheets are laminated. It is possible to suppress the superimposed noise.

  In addition, when the conductive paste used for forming the conductor layer includes conductive particles and insulating particles, the conductive paste contains a conductive particle by making the content of the insulating particles smaller than the content of the conductive particles. The resistance and impedance of the layer can be lowered, and the effect of suppressing noise is further improved.

The through conductors such as the power through conductor 10, the ground through conductor 11, and the signal through conductor 12 formed in the insulating layer 2 are formed by the following method. First, through holes are formed in the ceramic green sheet by a punching method using a die or punching, a laser processing method using a carbon dioxide gas (CO ₂ ) laser device, a UV-YAG laser device, or the like. Next, a conductive paste obtained by adding and mixing conductive particles such as Cu, an organic binder, a solvent, glass powder, resin beads and a filler is filled in the through holes, and the ceramic green sheet thus formed A through conductor can be formed by laminating a desired number of layers and firing.

  Further, when the conductive paste for forming the through conductor contains conductive particles and insulating particles, the content of the insulating particles in the conductive paste is made lower than the content of the conductive particles. The resistance and impedance of the through conductor can be further reduced, and the effect of suppressing noise is further improved.

  As shown in FIG. 2, the multilayer substrate 1 according to the present embodiment includes a plurality of power supply through conductors 10 and a plurality of ground through conductors 11 that are alternately annular from the center of the mounting portion 1a toward the outer periphery in a plan view. It is arranged. Further, the signal through conductors 12 are arranged in an annular shape on the outermost periphery of the mounting portion 1a.

  Thus, by arranging the through conductors in a ring shape, the distance (current path) between the through conductors is shortened. In addition, the width of the current path is increased. For example, in the current path of the power supply through conductor 10, the distance between the ground through conductors 11 adjacent to both sides of the power supply through conductor 10 is increased. As a result, the resistance and inductance in the power supply conductor layer 7 are reduced.

  For example, in the case of a conventional multilayer substrate in which a plurality of power supply through conductors and a plurality of ground through conductors are alternately arranged so as to be adjacent to each other in the mounting portion 1a of the semiconductor element 3 in plan view, the current path of the power supply through conductor 10 In the multilayer substrate 1 of the present embodiment, the length can be shortened to about 200 to 300 μm. Further, in the case of the above-described conventional multilayer substrate, the current width of the power supply through conductor 10 is about 50 μm, but in the multilayer substrate 1 of the present embodiment, it can be increased to about 100 to 200 μm. it can.

  In order to achieve such an effect, the annular shape is not limited to the quadrangular shape as shown in FIG. 2, but may be various shapes such as a triangular shape, a polygonal shape of pentagonal shape or more, a circular shape, and an elliptical shape. Good.

  Further, in the multilayer substrate 1 of the present embodiment, the plurality of power supply through conductors 10 form a group for each of a plurality of types of power supply potentials, and a plurality of ground through conductors 11 are sandwiched between the groups for each group. Thus, it may be configured to be arranged in an annular shape from the center of the mounting portion 1a toward the outer peripheral side in plan view. In this case, simultaneous switching noise can be effectively suppressed for a plurality of types of power supply potentials, and fluctuations in the voltage level of the power supply voltage can be suppressed. Further, a plurality of groups of power supply through conductors 10 arranged in a ring shape can be connected to a single power supply conductor layer 7. The ground through conductor 11 and the ground conductor layer 8 can have the same configuration. Therefore, the multilayer substrate 1 can be significantly reduced in thickness.

  For example, when a plurality of groups of power supply through conductors 10 are connected to one power supply conductor layer 7, about 10,000 to 15000 groups of power supply through conductors 10 can be connected. The same applies to the ground through conductor 11 and the ground conductor layer 8.

  As shown in FIG. 2, the number of annular groups in the case where the grounding through conductors 11 and the power supply through conductors 10 are alternately arranged in this order from the center of the mounting portion 1a depends on the size of the semiconductor element 3 and the distance between the through conductors. And the diameter of the through conductor. For example, the size of the semiconductor element 3 in plan view is 20 mm long × 20 mm wide, the distance between the power supply through conductor 10 and the ground through conductor 11, and the distance between the power supply through conductor 10 and the signal through conductor 12 Is 200 μm, and each of the power supply through conductor 10, the ground through conductor 11 and the power supply through conductor 10 has a diameter of 50 μm, the number of groups of the plurality of ground through conductors 11 arranged in a ring, and the plurality of rings arranged in a ring The number of groups of power supply through conductors 10 is about 100 each.

  In the multilayer substrate 1 of the present embodiment, it is preferable that a plurality of grounding through conductors 11 are arranged in an annular shape on the outermost periphery of the central portion of the mounting portion 1a in plan view. In this case, the plurality of grounding through conductors 11 arranged on the outermost periphery have the effect of electromagnetic shielding (shielding), and it is possible to effectively suppress the noise of electromagnetic waves trying to enter from the outside. The operability of the element 3 can be improved.

  Further, in the multilayer substrate 1 according to the present embodiment, as shown in FIG. 3, the power supply conductor layer 7 includes an annular power supply conductor layer including a portion through which a plurality of ground through conductors 11 arranged in a ring shape in plan view penetrate. It has a non-forming part 7a. Similarly, the ground conductor layer 8 has an annular ground conductor layer non-forming portion (not shown) including a portion through which a plurality of power supply through conductors 10 arranged in an annular shape in a plan view pass.

  The width of the power supply conductor layer non-forming portion 7a may be larger than the diameter of the grounding through conductor 11 (about 50 to 100 μm), and preferably about 30 to 40% larger than the diameter of the grounding through conductor 11. Within this range, the conductive paste for forming the grounding through conductor 11 can be largely prevented from coming into contact with the power supply conductor layer 7 and becoming a defective product. It can suppress that the width | variety of 7a becomes large too much and the multilayer substrate 1 is enlarged. Further, the width of the ground conductor layer non-forming portion can be configured similarly for the same reason.

  The semiconductor device of the present embodiment includes the multilayer substrate 1 of the present invention and the semiconductor element 3 mounted on the mounting portion 1a of the multilayer substrate 1. For this reason, the operation characteristics of the semiconductor element 3 mounted on the multilayer substrate 1 are good.

  The semiconductor element 3 is an integrated circuit element such as an IC or LSI, or an optical semiconductor element such as a semiconductor laser (LD) or a photodiode (PD).

  In this semiconductor element 3, for example, a large number of signal terminals are formed on the outer peripheral portion of the lower surface, a large number of power terminals and a large number of ground terminals are formed in the central portion of the lower surface, and each terminal is formed on the upper surface of the multilayer substrate 1. Electrically connected to the electrode pad 6 through conductor bumps 5 made of solder such as tin-lead (Sn-Pb) alloy, tin-silver-copper (Sn-Ag-Cu) alloy, or gold (Au). And mounted on the mounting portion 1a.

  In addition, the signal conductor layer 9 having signal wiring for transmitting signals in the multilayer substrate 1 has a desired characteristic impedance by appropriately setting the wiring width of the signal wiring and the thickness of the insulating layer 2h on which the signal conductor layer 9 is formed. Value can be set. As a result, it is possible to form the signal conductor layer 9 having good transmission characteristics. The characteristic impedance of the signal conductor layer 9 is generally set to 50Ω. If there are a plurality of signal conductor layers 9, different signals may be transmitted.

  An insulating layer 2g in which a ground conductor layer 8 in which no conductor is formed is laminated on a portion facing the signal wiring is laminated on the insulating layer 2h in which the signal conductor layer 9 having the signal wiring is formed. By appropriately adjusting the distance between the layer 8 and the signal conductor layer 9, the characteristic impedance can be adjusted more easily.

  The signal processed by the semiconductor element 3 passes through the signal through conductor 12, is transmitted through the signal wiring of the signal conductor layer 9, and again passes through the signal through conductor 12 to be external printed wiring on which the multilayer substrate 1 is mounted. It is transmitted to an external electric circuit formed on a substrate or the like.

  The power supply voltage passes through the power supply through conductor 10, is connected to the power supply voltage signal transmitted from the other power supply through conductor 10 on the power supply conductor layer 7, and is supplied again to the semiconductor element 3 through the through conductor 10. Is done.

  The ground potential is electrically connected to the semiconductor element 3 through the grounding through conductor 11 and the grounding conductor layer 8 and again through the through conductor 11.

  In addition, what is mounted on the multilayer substrate 1 of the present embodiment is not limited to the semiconductor element 3, but may be a chip resistor, a thin film resistor, a coil inductor, a cross inductor, a chip capacitor, an electrolytic capacitor, or the like. The semiconductor device of the present embodiment may be an electronic circuit module on which these electronic components are mounted.

  Further, the shape of the multilayer substrate 1 in plan view may be a rhombus shape, a hexagonal shape, an octagonal shape, a circular shape or the like in addition to the square shape and the rectangular shape. Such a multilayer substrate 1 is also used as a package for housing semiconductor elements, a substrate for mounting electronic components, a so-called multichip module and multichip package on which a large number of semiconductor elements 3 are mounted, a motherboard, and the like.

  Examples of the multilayer substrate of the present invention will be described below.

  The multilayer substrate 1 of the example of the present invention shown in FIG. 1 was produced as follows. First, an organic binder and a solvent were added to a raw material powder of an inorganic insulating material containing glass called glass ceramic to form a slurry, and this was formed into a sheet by a doctor blade method to produce a ceramic green sheet.

  Next, through holes are formed in the ceramic green sheet by a laser processing method using a UV-YAG laser device, and Cu conductive particles, organic binder, solvent, glass powder, resin beads and filler are added and mixed. The obtained conductive paste was filled in the through holes. In addition, a conductive paste containing Cu conductive particles, which becomes each conductor layer and electrode pad, was printed and applied to the ceramic green sheet in a predetermined pattern. A predetermined number of the obtained ceramic green sheets were laminated to form a laminate, and this laminate was fired in a reducing atmosphere at a temperature of about 900 ° C., thereby producing a multilayer substrate 1.

  As shown in FIGS. 2 and 3, the plurality of power supply through conductors 10 and the plurality of ground through conductors 11 are alternately arranged in an annular shape from the center of the mounting portion 1a toward the outer periphery in a plan view. The power supply conductor layer 7 has an annular power supply conductor layer non-forming portion 7a including a portion through which a plurality of grounding through conductors 11 arranged in a ring shape in a plan view passes, and the ground conductor layer 8 has a plan view in a plan view. An annular ground conductor layer non-forming portion including a portion through which a plurality of power supply through conductors 10 arranged in an annular shape passes is assumed.

  The diameter of the power supply through conductor 10 was 50 μm, and the diameter of the ground through conductor 11 was 50 μm. The length of the current path, which is the distance between the power supply through conductors 10, is 175 μm, and the width of the current path of the power supply through conductor 10 is 200 μm. The same applies to the length and width of the current path of the ground through conductor 11.

  A group of a plurality of power supply through conductors 10 arranged in a square ring shape connected to one power supply conductor layer 7 is a group of 80, a plurality of a plurality of square ring arrangements connected to one ground conductor layer 8. The group of ground through conductors 11 was 80. Therefore, in the insulating layer shown in FIG. 2, there are a plurality of power supply through conductors 10 arranged in a ring of 80 groups and a plurality of grounding through conductors 11 arranged in a ring of 80 groups.

  The width of the power supply conductor layer non-forming portion 7a is 75 μm, and is 50% larger than the diameter of the power supply through conductor 10. The same applies to the width of the portion where the ground conductor layer is not formed and the diameter of the ground through conductor 11.

  An LSI having an operating frequency of 5 GHz, a power supply voltage of 1 V, and a ground potential of 0 V was mounted as the semiconductor element 3 on the upper surface of the multilayer substrate 1 to manufacture a semiconductor device.

  Further, as a semiconductor device of a comparative example, a multilayer substrate having a configuration in which a plurality of power supply through conductors and a plurality of ground through conductors are alternately arranged so as to be adjacent to each other in the mounting portion 1a of the semiconductor element 3 in plan view, It produced similarly. In the multilayer substrate of the comparative example, the diameter of the power supply through conductor was 50 μm, and the diameter of the ground through conductor was 50 μm. The length of the current path, which is the distance between the power supply through conductors, was 360 μm, and the width of the current path of the power supply through conductor was 50 μm. The same applies to the length and width of the current path of the ground through conductor. Each power feedthrough conductor passes through a circular ground conductor layer non-forming portion having a diameter of 150 μm in the ground conductor layer, and each ground feed conductor is a circular power conductor having a diameter of 150 μm in the power supply conductor layer. The layer non-formed part was penetrated.

  For each of these semiconductor devices, the loop inductance Lr was obtained from computer-simulated Ls + Lgnd−2 × Lm (Ls is the inductance of the power supply conductor layer, Lgnd is the inductance of the ground conductor layer, and Lm is the mutual inductance).

  In the semiconductor device of the example, Lr was 224.08 (pH) because Ls of the power supply conductor layer and the ground conductor layer was 216.14 (pH) and Lm was 104.10 (pH). Moreover, Lr was 4.54 (pH) because Ls of the power supply through conductor and the ground through conductor of the through conductor portion was 12.33 (pH) and Lm was 10.06 (pH), respectively. Therefore, Lr including the conductor layer and the through conductor portion was 228.62 (pH).

  In the semiconductor device of the comparative example, Lr was 291.80 (pH) because Ls of the power supply conductor layer and the ground conductor layer was 284.54 (pH) and Lm was 138.64 (pH). Moreover, Lr was 2.91 (pH) because Ls of the power supply through conductor and the ground through conductor of the through conductor portion was 14.50 (pH) and Lm was 13.05 (pH), respectively. Therefore, Lr including the conductor layer and the through conductor portion was 294.71 (pH).

  In addition, when the bounce characteristics were obtained for each of these semiconductor devices by computer simulation, the fluctuation width of the level of the input power supply voltage due to the bounce at the input power supply voltage of 1 V was 0.121 (V) in the semiconductor device of the example. It was. In contrast, in the semiconductor device of the comparative example, the fluctuation width of the level of the input power supply voltage due to the bounce at the input power supply voltage of 1V was 0.197 (V). Therefore, the fluctuation width of the level of the input power supply voltage due to the bounce is reduced by about 38.5% in the semiconductor device of the example compared to the semiconductor device of the comparative example.

  The present invention is not limited to the above-described embodiments and examples, and various modifications can be made without departing from the scope of the present invention.

DESCRIPTION OF SYMBOLS 1 ... Multilayer board | substrates 2a-2j ... Insulating layer 3 ... Semiconductor element 7 ... Power supply conductor layer 7a ... Power supply conductor layer non-formation part 8 ... Grounding conductor layer 9 ... Signal conductor Layer 10... Power supply through conductor 11... Ground through conductor 12... Signal through conductor

Claims (4)

  A plurality of insulating layers, a power source conductor layer formed between the insulating layers, a ground conductor layer formed between the insulating layers different from the insulating layer on which the power source conductor layer is formed, and a plurality of outer peripheral portions on the lower surface A base having a mounting portion on the upper surface for mounting a signal element and a semiconductor element having a plurality of power supply terminals and a plurality of ground terminals in the central portion, and formed from the central portion of the mounting portion of the base toward the lower surface side of the base A plurality of power supply through conductors electrically connected to the power supply conductor layer, a plurality of ground through conductors electrically connected to the ground conductor layer, and an outer peripheral portion of the mounting portion of the base body A plurality of signal through conductors formed toward the lower surface side of the plurality of power supply through conductors and the plurality of ground through conductors from the center of the mounting portion toward the outer peripheral side in plan view. And the power supply conductor layer has a ring-shaped power supply conductor layer non-forming portion including a portion through which the plurality of grounding through conductors arranged in a ring shape in a plan view penetrates, The multi-layer substrate, wherein the ground conductor layer has a ring-shaped ground conductor layer non-forming portion including a portion through which the plurality of power supply through conductors arranged in a ring shape in plan view.   The plurality of power supply through conductors form a group for each of a plurality of types of power supply potentials, and the plurality of ground through conductors are sandwiched between the groups for each group, and the outer periphery from the center of the mounting portion in plan view The multilayer substrate according to claim 1, wherein the multilayer substrate is arranged in an annular shape toward the side.   3. The multilayer substrate according to claim 1, wherein a plurality of the ground through conductors are annularly arranged on an outermost periphery of a central portion of the mounting portion in a plan view.   A semiconductor device comprising: the multilayer substrate according to claim 1; and a semiconductor element mounted on the mounting portion of the multilayer substrate.

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