JPH0536857A - Semiconductor integrated circuit mounting board - Google Patents

Abstract

PURPOSE:To provide a semiconductor integrated circuit mounting board of high reliability where power supply noises are restrained in high speed switching operation, and semiconductor integrated circuits and discrete components are highly integrated and densely mounted. CONSTITUTION:A capacitor composed of a first conductor electrode layer 2, a second conductor electrode layer 4, and a dielectric layer 3 sandwiched between them is provided onto a board 1. A semiconductor integrated circuit chip 8 mounted on the uppermost surface of the board 1 is connected to the capacitor concerned through connection vias 9 and 10, so that a space required for the surface mounting and the wiring of a chip capacitor can be dispensed with, therefore more integrated circuit chips can be mounted accordingly and enhanced in degree of arrangement and connection, and thus a semiconductor integrated circuit and discrete components can be highly integrated and densely mounted.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit mounting board.

[0002]

2. Description of the Related Art In recent years, electronic devices have been increasing in speed of information processing,
There are significant movements such as miniaturization, multi-functional integration, and specialization for specific purposes. Along with this, in the field of semiconductor integrated circuits, high-speed information processing, high integration of elements, dedicated IC
However, there is a semiconductor integrated circuit mounting board as one form of semiconductor integrated circuit mounting that accurately meets these demands.

A semiconductor integrated circuit mounting board using a plurality of the semiconductor integrated circuit chips uses a wiring board having a fine wiring pattern for connecting the integrated circuits and individual parts, and has a multi-layered wiring for higher integration. There are many things that have become.

In order to realize the above-mentioned high-speed information processing on this semiconductor integrated circuit mounting board, a high-speed switching operation is performed and a large-current pulse instantaneously flows in the power supply system of the semiconductor integrated circuit. Since the power supply voltage fluctuates, there are problems that the noise margin is reduced, the circuit operation becomes unstable, and the circuit malfunctions. In addition, with the high integration of semiconductor integrated circuits and individual components, there is a problem that power supply noise and crosstalk between signal lines occur.

Therefore, in the conventional semiconductor integrated circuit mounting substrate, by connecting a bypass capacitor to the power supply system of the semiconductor integrated circuit chip 401, fluctuations in the power supply voltage are alleviated and power supply noise is suppressed. This is shown in FIGS. 6 and 7. FIG. 6 is a plan view showing its planar structure, and FIG. 7 is a side sectional view thereof.

As a conventional bypass capacitor, a chip capacitor 402 mounted on a mounting pad provided on the uppermost surface of a wiring board of a semiconductor integrated circuit mounting board.
Alternatively, a capacitor formed by two conductor electrode layers and a dielectric layer sandwiched between these two layers is used, which is stuck on almost the entire bottom layer of the multilayer wiring layer.

However, in such a conventional semiconductor integrated circuit mounting board, when a chip capacitor is used, the area occupied by the chip capacitor and the area for wiring the chip capacitor are required in the surface layer of the board, and that much space is required. The mounting area of the semiconductor integrated circuit is reduced. Further, there is a large restriction on the arrangement of the chip capacitors and the semiconductor integrated circuits and the connection between them, and there is a problem that it is not easy to achieve high integration of the semiconductor integrated circuits and individual components.

In the case of using a capacitor formed of two conductive electrode layers and a dielectric layer sandwiched between these two layers, a power supply system of a plurality of semiconductor integrated circuits is provided for one capacitor. , The power supply noises generated in the respective semiconductor integrated circuits influence each other through the capacitors, resulting in a worse noise.

[0009]

As described above, in the conventional semiconductor integrated circuit mounting board, there is a problem that the power line noise is generated during the high speed switching operation, and the noise affects the signal line. By connecting a bypass capacitor to the power supply system of a semiconductor integrated circuit, we are trying to mitigate fluctuations in the power supply voltage and suppress power supply noise.However, a chip capacitor or a capacitor formed by thick film is used as the bypass capacitor on the substrate surface. In the case of arranging, the occupied area and the area for the wiring are required on the surface of the substrate, and there is a great restriction on the degree of freedom of arrangement and wiring of them, so that high integration and high integration of semiconductor integrated circuits and individual components are required. There is a problem that density mounting is not easy.

In the case of using a capacitor formed of two conductor electrode layers and a dielectric layer sandwiched between these two layers in the laminated structure of the wiring layer and the dielectric layer, the power source noises are different from each other. However, there is a problem that the capacitors influence each other to cause worse noise, and that the wiring for connecting the capacitor and the corresponding semiconductor integrated circuit becomes complicated. .. As the speed of information processing of semiconductor integrated circuits and the integration of elements thereof are increasing more and more, the problem of power source noise generation during high-speed switching operation of semiconductor integrated circuits as described above is becoming more difficult to solve. ..

The present invention has been made in view of the above problems, and an object of the present invention is to effectively suppress the generation of power supply noise during high-speed switching operation and solve the problem of malfunction. Another object of the present invention is to provide a semiconductor integrated circuit mounting board that is highly reliable and that realizes high integration and high density mounting of a semiconductor integrated circuit and individual components.

[0012]

In order to achieve the above-mentioned object, a semiconductor integrated circuit mounting board of the present invention is provided on a multilayer wiring board in which conductor layers and first dielectric layers are alternately laminated.
In a semiconductor integrated circuit mounting board having one or more semiconductor integrated circuit chips mounted thereon and having a bypass capacitor connected between two terminals having different potentials on the semiconductor integrated circuit chip, a second dielectric layer is provided on the multilayer wiring board. Are provided and opposite electrodes of the bypass capacitor are formed on the same conductor layer on the second dielectric layer or on different conductor layers adjacent to each other via the second dielectric layer. One electrode and one end of the power supply circuit of the semiconductor integrated circuit chip, the other electrode of the bypass capacitor and the other end of the power supply circuit of the semiconductor integrated circuit chip, which has a different potential from the one end, are electrically connected. Each of the semiconductor integrated circuit chips has a structure
One or more of the bypass capacitors electrically connected are arranged in a projected area of the semiconductor integrated circuit chip onto the semiconductor integrated circuit mounting substrate.

[0013]

In the semiconductor integrated circuit mounting substrate of the present invention, the bypass capacitor formed by the first conductor electrode layer, the second conductor electrode layer, and the dielectric layer sandwiched between these two layers is a substrate. The semiconductor integrated circuit is disposed on the inner layer of the laminated structure composed of the wiring layer and the insulating layer laminated as the laminated structure above, and is connected to the semiconductor integrated circuit mounted on the surface of the uppermost layer of the laminated structure of the substrate by the connection via (via). Since they are connected, unlike the conventional ones where surface mounting of chip capacitors is required, there is no need for the occupied area and the area for wiring on the surface of the top layer of the laminated structure of the board, and their arrangement and wiring. The restrictions on the degree of freedom of are also greatly reduced.
Therefore, high integration and high-density mounting of semiconductor integrated circuits and individual components can be realized.

Further, a plurality of bypass capacitors formed by the above-mentioned first conductor electrode layer, second conductor electrode layer and the dielectric layer sandwiched between these two layers are formed. , Each of the parts is connected to the power supply system of the corresponding semiconductor integrated circuit and arranged so as to function individually, so that there is no interference of power supply noise between the semiconductor integrated circuits, and each of the divided parts is divided. Since the optimum capacitance value for noise removal of the power supply system of the connected semiconductor integrated circuit can be set for each part of, the power supply noise can be effectively suppressed and malfunctions can be prevented. it can. Also, if the corresponding bypass capacitor is placed directly below the semiconductor integrated circuit, the connecting via between the semiconductor integrated circuit and the bypass capacitor can be as short as possible, reducing the inductance and stabilizing the power supply. In addition, the connection design can be simplified and the manufacturing cost can be reduced as compared with the case where a chip capacitor or the like is mounted on the surface of the substrate by reflow soldering or the like.

[0015]

Embodiments of the present invention will now be described in detail with reference to the drawings.

(Embodiment 1) FIG. 1 is a side sectional view showing a structure of a semiconductor integrated circuit mounting board according to a first embodiment of the present invention, and FIG. 2 is a partially omitted perspective view thereof.

This semiconductor integrated circuit mounting substrate is a substrate 1.
A first conductor electrode layer 2 attached to the entire upper surface of the substrate, a dielectric layer 3 corresponding to a second dielectric layer attached to the entire upper surface of the substrate, and an upper surface of the dielectric layer 3. A second conductor electrode layer 4 that is attached and divided into a plurality of parts, an insulating layer 5 and a wiring layer 6 that are first dielectric layers alternately laminated on the second conductor electrode layer 4, and are mounted on the surface thereof. The semiconductor integrated circuit chip 8, the first conductor electrode layer 2 and the second conductor electrode layer 4, and the connection vias 9 and 10 for connecting the power supply system terminals of the semiconductor integrated circuit chip 8 corresponding thereto. It has.

The substrate 1 is a substrate made of a material such as silicon (Si) or aluminum nitride (AlN). The substrate 1 is laminated on the substrate 1 and the semiconductor integrated circuit chip 8 is further mounted thereon.

The first conductor electrode layer 2 is formed on the entire upper surface of the substrate 1.
Is pasted. The first conductor electrode layer 2 is made of aluminum (Al), tungsten (W), copper (C
It is an electrode layer made of a metal conductor such as u). This first conductor electrode layer 2 is arranged so as to be a common electrode for all the second conductor electrode layers 4 facing each other, and is connected to the power supply system terminal of each semiconductor integrated circuit chip 8. To be done.

A dielectric layer 3 is stuck on the entire upper surface of the first conductor electrode layer 2. The dielectric layer 3 is a thin film of tantalum dioxide (Ta ₂ O ₅ ) or silicon dioxide (Si) formed by sputtering or CVD.
It is a dielectric layer made of a dielectric material such as O ₂ ).

The second conductor electrode layer 4 is made up of this dielectric layer 3
And the dielectric layer 3 is sandwiched between the dielectric layer 3 and the first conductive electrode layer 2. The first conductor electrode layer 2 serves as a common electrode layer, the second conductor electrode layer 4 serves as an individual electrode, and an individual capacitor is formed by them.

As shown in FIG. 2, each of these individual capacitors is arranged in a planar positional relationship such that it is located substantially directly below the semiconductor integrated circuit chip 8 to which it is connected, The semiconductor integrated circuit chips 8 are arranged so as to be individually connected.

Then, the thickness and the dielectric constant of the dielectric layer 3 are taken into account to adjust the individual area of the second conductor electrode layer 4, and the capacitance of each individual capacitor corresponds to the corresponding semiconductor integrated circuit. It is set to be optimum for removing power supply system noise of the circuit chip 8. Moreover, in order to cope with higher-density mounting, the area of these capacitors is set so as to be within the planar projected area of the corresponding semiconductor integrated circuit chip.

Further, the above-mentioned individual capacitors located substantially directly below the semiconductor integrated circuit chip 8 are provided in a more finely divided manner, and each of them is included in one semiconductor integrated circuit chip 8 directly above it. It is also possible to connect to each of a plurality of power supply systems. That is, in the case where the power supply system inside one semiconductor integrated circuit chip 8 is divided into a plurality of functional blocks for input buffer, output buffer, internal circuit, etc., the semiconductor integrated circuit chip has a plurality of power sources. Although it has a system, it is possible to more effectively remove the power supply system noise by connecting a capacitor having an optimum electrostatic capacity to each of these power supplies.

When the dielectric constant of the dielectric layer 3 is ε, the area of the dielectric layer 3 is S, and the thickness of the dielectric layer 3 is t, the electrostatic capacitance value C of the capacitor thus constructed is C = εS /
It can be obtained from the relational expression t. For example, when Ta ₂ O ₅ having a relative dielectric constant of 20 is used for the dielectric layer 3 as in this embodiment, the thickness of the dielectric layer 3 is 0.3 μm, and the area of the dielectric of the capacitor is 25 mm ² , C is about 0.015μF
Therefore, the capacitance value is practically sufficient as a bypass capacitor.

Insulating layers 5 and wiring layers 6 are alternately laminated on the second conductor electrode layer 4.

The insulating layer 5 is a layer made of polyimide having a good insulating property, and is disposed between the wiring layers 6 to electrically insulate each wiring layer.

The wiring layer 6 is a conductor wiring layer made of copper, and as shown in FIG.
Signal wiring layer 12, power return line (ground) wiring layer 3
The layers are arranged with the insulating layer 5 interposed therebetween.

Of these, the power supply wiring layer 11 and the power supply return wiring layer 13 correspond to the power supply system wiring. The power supply wiring layer 11 is connected to the first conductor electrode layer 2 and the power supply terminal 14 of the semiconductor integrated circuit chip 8 via the connection via 9, and the power supply return wiring layer 13 is connected to the second conductivity type via the connection via 10. Body electrode layer 4
And a power supply return terminal 15 of the semiconductor integrated circuit chip 8.

The signal wiring layer 12 conducts data pulses and the like to the semiconductor integrated circuit chip 8, and the power supply layer 1
By forming the strip structure by being sandwiched between 1 and the power return line 13, crosstalk to the signal lines due to power supply noise or crosstalk between the signal lines due to high frequency signal pulse transmission is suppressed.

The connection vias 9 and 10 are, similarly to the general connection vias according to the existing technology, through the holes patterned in the insulation layer 5 at the laminating step of the insulation layer 5 and the wiring layer 6 and the wiring layers of the upper layer and the lower layer. It is formed by making contact with the wiring layer.

The semiconductor integrated circuit mounting board according to the first embodiment of the present invention has such a structure, and a capacitor having an optimum capacitance is individually connected to each semiconductor integrated circuit chip. As a result, effective removal of power system noise for each semiconductor integrated circuit chip is realized.

As the bypass capacitor for effectively removing the power supply system noise for each semiconductor integrated circuit chip, a capacitor having a capacitance value of about 0.1 μF to 0.01 μF is usually adopted. The capacitance value of this capacitor can be appropriately set to different capacitance values by adjusting the area of the dielectric and the thickness of the dielectric layer, or by selecting the material of the dielectric layer, and the corresponding semiconductor integrated It can be optimized for removing power supply system noise of the circuit chip.

(Embodiment 2) FIG. 3 is a side sectional view showing a structure of a semiconductor integrated circuit mounting board according to a second embodiment of the present invention.

The structure of the semiconductor integrated circuit mounting board according to the second embodiment is almost the same as that of the semiconductor integrated circuit mounting board according to the first embodiment, but the first conductor electrode layer 20 is used.
No. 2 is not a solid common electrode stuck on the entire surface of the substrate as in the first embodiment, but is divided into a plurality of pieces and stuck on the upper surface of the dielectric layer 203 like the second conductor electrode layer 204. A plurality of independent capacitors are formed by sandwiching the dielectric layer 203 together with the opposing second conductor electrode layer 204, and the capacitance of each of these capacitors corresponds to the corresponding semiconductor. The difference is that the film thickness of the dielectric layer 203 is set in consideration of calculation so as to be optimum for removing power system noise of the integrated circuit chip 208. This second
In the semiconductor integrated circuit mounting board according to the embodiment of the present invention, since each of the capacitors connected to each semiconductor integrated circuit chip 208 is a plurality of completely independent capacitors that do not use a common electrode, a power supply is provided between the capacitors. It is possible to prevent the noises from affecting each other more effectively than in the first embodiment.

The semiconductor integrated circuit mounting board according to the second embodiment of the present invention has such a structure, and has a completely independent capacitor having an optimum capacitance individually for each semiconductor integrated circuit chip. By connecting them, more effective removal of power system noise for each semiconductor integrated circuit chip is realized.

(Embodiment 3) FIG. 4A is a side sectional view showing a structure of a semiconductor integrated circuit mounting board according to a third embodiment.
FIG. 4B is a side sectional view taken along the line AB in which the structure of the capacitor portion is enlarged, and FIG. 5 is a partially omitted perspective view showing the structure of the semiconductor integrated circuit mounting board according to the third embodiment. ..

The semiconductor integrated circuit mounting board according to the third embodiment has substantially the same substrate, laminated structure, and semiconductor integrated circuit chip as the semiconductor integrated circuit mounting boards of the first and second embodiments. However, the dielectric layer and the conductor electrode layer are different, and in particular, the electrodes of the conductor electrode layer are comb-shaped as shown in FIG. 5, and are electrodes facing each other in the horizontal direction. It is characterized by that.

The structure will be briefly described in order from the lower layer. As shown in FIG. 4A, a substrate 301 made of a material such as silicon (Si) or aluminum nitride (AlN), and an entire upper surface of the substrate 301 are provided. The dielectric layer 303 that is stuck, and the dielectric layer 303 that is stuck on the upper surface of the dielectric layer 303,
A comb-shaped first conductor electrode 304 made of a metal conductor such as aluminum (Al), tungsten (W), or copper (Cu) is disposed so as to face the comb-shaped first conductor electrode 304 on the same plane. Comb-shaped second conductor electrode 3 made of the same material as the disposed first conductor electrode 304.
05, and an insulating layer 308 made of polyimide having a good insulating property, which is formed on the comb-shaped conductor electrodes 304 and 305 and arranged so as to fill the space between the opposing conductor electrodes. A wiring layer 307 made of a metal conductor and an insulating layer 308 made of polyimide, which are alternately laminated on the insulating layer 308, a semiconductor integrated circuit chip 310 mounted on the surface of the uppermost layer, a first conductor electrode 304, and Second
Connection conductors 305 and connection vias 311 and 312 for connecting the respective power supply system terminals of the semiconductor integrated circuit chip 310 corresponding thereto.

In the semiconductor integrated circuit mounting substrate according to the third embodiment, the comb-shaped first conductor electrodes 30 are provided so as to face each other on the same plane with the insulating layer 308 interposed therebetween.
4, a comb-shaped second conductor electrode 305 and an upper or lower dielectric layer form a capacitor.

As shown in FIG. 5, the capacitor is arranged so as to be located directly below the corresponding semiconductor integrated circuit chip 310 in plan view, and the connection via 31 is formed.
1, 312 by the comb-shaped first conductor electrode 30.
4 and the comb-shaped second conductor electrode 305, one is connected to the power supply terminal of the semiconductor integrated circuit chip 310 and the other is connected to the power supply return line (ground) terminal of the semiconductor integrated circuit chip 310. Function as a bypass capacitor of.

With respect to the electrostatic capacitance of the capacitor configured as described above, the line width, wiring interval, and dielectric layer thickness are changed so that the capacitor has an optimum value as a bypass capacitor of the semiconductor integrated circuit chip to which it is connected. To adjust. The capacitance value at this time can be obtained from the following relational expression. That is, the capacitance value C formed by the two adjacent electrodes 304 and 305 and the dielectric layer 303 in contact with these electrodes shown in FIG. The line width of the electrode 304 and the electrode 305 of the book is w, the thickness thereof is t, the gap between these two electrodes is s,
When the layer thickness of the dielectric layer 303 is h and its dielectric constant is ε, C = εK (k ′) / K (k), where k = (s / h) / (s / h + 2w / h), k ′ = (1−k ² ) ^{1/2 In} this third embodiment, the dielectric layer 303 is not limited to the lowermost layer 1 layer, but a total of 2 layers above and below the comb-shaped conductor electrode so as to sandwich the conductor electrode. You may arrange | position a layer.

The semiconductor integrated circuit mounting board according to the third embodiment of the present invention has such a structure, and a capacitor having an optimum electrostatic capacity is individually connected to each semiconductor integrated circuit chip. Thus, effective removal of power supply system noise for each semiconductor integrated circuit chip is realized.

In this embodiment, a ceramic material such as aluminum nitride (AlN) or silicon (Si) is used for the substrate, and a laminated structure of a polyimide thin film and copper is adopted as the laminated structure of the capacitor and its upper layer. It is not necessarily limited to this. For example, a thick film structure made of a ceramic material such as a green sheet may be used for the laminated structure. Also, by using a co-firing laminated structure on a substrate and forming a capacitor in the co-firing laminated structure, and using this together with the above-mentioned capacitor as a supplement, the same effect of removing power supply noise can be obtained. Obtainable.

[0045]

As described above in detail, the semiconductor integrated circuit mounting board of the present invention effectively suppresses the generation of power supply noise during high-speed switching operation and solves the problem of malfunctions. The semiconductor integrated circuit mounting board is highly reliable and realizes high integration and high density mounting of the semiconductor integrated circuit and individual components.

[Brief description of drawings]

FIG. 1 is a side sectional view showing a configuration of a semiconductor integrated circuit mounting board according to a first embodiment of the present invention.

FIG. 2 is a perspective view showing a configuration of a semiconductor integrated circuit mounting board according to the first embodiment of the present invention.

FIG. 3 is a side sectional view showing a configuration of a semiconductor integrated circuit mounting board according to a second embodiment of the present invention.

FIG. 4 is a side sectional view (a) showing a configuration of a semiconductor integrated circuit mounting board according to a third embodiment of the present invention and an AB side sectional view (b) showing an enlarged capacitor portion thereof.

FIG. 5 is a perspective view showing a configuration of a semiconductor integrated circuit mounting board according to a third embodiment of the present invention.

FIG. 6 is a plan view showing a configuration of a conventional semiconductor integrated circuit mounting board.

FIG. 7 is a side sectional view showing a configuration of a conventional semiconductor integrated circuit mounting board.

[Explanation of symbols]

 1 ………… Substrate 2 ………… First conductor electrode layer 3 ………… Dielectric layer 4 ………… Second conductor electrode layer 5 ………… Insulating layer 6 ………… Wiring layer 8 ………… Semiconductor integrated circuit chip 9, 10… Connection via 11 ………… Power supply wiring layer 12 ………… Signal wiring layer 13 ………… Power supply return (ground) wiring layer 14 ……. … Power supply terminal 15 ………… Power supply return terminal

Claims (1)

Claim: What is claimed is: 1. A semiconductor integrated circuit chip having one or more chips mounted on a multilayer wiring board, which is obtained by alternately laminating conductive layers and first dielectric layers. In a semiconductor integrated circuit mounting board having a bypass capacitor connected between two terminals having different chip potentials, a second dielectric layer is provided on the multilayer wiring board, and
Counter electrode of the bypass capacitor is formed on the same conductor layer on the dielectric layer or on different conductor layers adjacent to each other via the second dielectric layer, and one electrode of the bypass capacitor and the semiconductor integrated circuit. The semiconductor device has a structure in which one end of a power supply circuit of a circuit chip, the other electrode of the bypass capacitor, and the other end of the power supply circuit of the semiconductor integrated circuit chip having a different potential from the one end are electrically connected. One or more of the bypass capacitors electrically connected individually to each integrated circuit chip are arranged within a projected area of the semiconductor integrated circuit chip onto the semiconductor integrated circuit mounting substrate. Integrated circuit board.