TWI397362B - Multilayer printed wiring board - Google Patents

Description

Multilayer printed wiring board

The present invention relates to a multilayer printed wiring board having a deposition portion formed by electrically connecting a wiring pattern in which a plurality of wiring layers are formed via a via hole in an insulating layer.

Conventionally, a multilayer printed wiring board having a deposition portion formed by electrically connecting a wiring pattern in which a plurality of layers are laminated via an insulating layer through a via hole in an insulating layer has various structures. For example, when such a multilayer printed wiring board is turned on and off by a semiconductor device mounted at a high speed, switching noise is generated to instantaneously lower the potential of the power supply line, and in order to suppress the instantaneous decrease of the potential, it has been proposed. A method of decoupling is performed by connecting a capacitor portion between a power supply line and a ground line. As shown in Japanese Laid-Open Patent Publication No. 2001-68858, the capacitor portion is disposed in a multilayer printed wiring board.

However, in the layered capacitor portion of the above publication, since a dielectric layer composed of an organic resin containing an inorganic filler such as barium titanate is used, a large electrostatic capacity cannot be obtained, and the on-off frequency of the semiconductor element is easily caused. Since the high potential of GHz to several tens of GHz is instantaneously lowered, it is difficult to exhibit a sufficient decoupling effect.

In view of the above, an object of the present invention is to provide a multilayer printed wiring board capable of exhibiting a sufficient decoupling effect.

In order to achieve at least a portion of the above objectives, the present invention employs the following means.

The present invention has a multilayer printed wiring board in which a deposition portion formed by electrically connecting a wiring pattern in which a plurality of layers are laminated via the insulating layer is formed by a via hole in an insulating layer, and has a surface mounted with the wiring The pattern forming the mounting portion of the electrically coupled semiconductor element; between the mounting portion and the stacking portion, having a ceramic high dielectric layer and first and second layers sandwiching the high dielectric layer In the electrode, one of the first and second layered electrodes is connected to the power supply line of the semiconductor element, and the other is connected to the layered capacitor portion of the ground line.

Since the multilayer printed wiring board is made of a high dielectric layer ceramic which is connected to the layered capacitor portion between the power supply line and the ground line, the dielectric constant is higher than that of the conventional organic resin-containing organic resin. The static capacitance of the layered capacitor portion is large. Therefore, even if the frequency at which the semiconductor element is turned on and off is likely to be instantaneously lowered at a high potential of several GHz to several tens of GHz (for example, 3 GHz to 20 GHz), a sufficient decoupling effect can be exhibited.

In the high dielectric layer of the multilayer printed wiring board of the present invention, the material produced by firing the high dielectric material with the deposited portion is bonded to the deposition portion. In general, since the deposition portion is formed at a temperature of 200 ° C or lower, it is difficult to form a ceramic by firing of a high dielectric material, so that firing of a high dielectric material is required to be formed in the deposited portion. ceramics. Such a high dielectric layer is not particularly limited and may be a pair containing, for example, barium titanate (BaTiO ₃ ), barium titanate (SrTiO ₃ ), tantalum oxide (TaO ₃ , Ta ₂ O ₅ ), lead zirconate titanate. One selected from the group consisting of (PZT), lead zirconate titanate (PLZT), lead zirconate titanate (PNZT), lead zirconium titanate (PCZT), and lead zirconate titanate (PSZT) Or a raw material of two or more kinds of metal oxides is produced by firing.

The multilayer printed wiring board of the present invention may be arranged such that a lower surface side of the high dielectric layer of the first layered electrode is provided with a rod shape that can be connected to the second layered electrode a flat pattern of the through hole passing through the hole in a non-contact state, and a front side of the high dielectric layer of the second layered electrode is disposed to have a rod terminal that can be connected to the first layered electrode The contact state passes through the flat coating pattern of the holes. As a result, the first and second layered electrodes of the layered capacitor portion can have a large area, so that the layered capacitor portion can have a large electrostatic capacitance. Further, not only can the charge of the layered capacitor portion be charged from the external power source with a shorter wiring length, but also the power supply can be supplied to the semiconductor element from the layered capacitor portion with a shorter wiring length, so that the interval between the conduction and the disconnection is shorter. In the case of a semiconductor device of GHz to several tens of GHz (for example, 3 GHz to 20 GHz), a sufficient decoupling effect can be obtained, and a power shortage is unlikely to occur. In addition, each of the flat coating patterns may be disposed on one of the upper or lower portions of the high dielectric layer, or may be provided in a comprehensive manner.

The printed wiring board of the present invention may have a configuration in which the mounting portion has a plurality of connection pads connected to the electrodes of the semiconductor element, and is electrically connected to a connection pad having the same potential as the first layer electrode. Further, the number of the rod-shaped terminals through which the second layered electrode passes in a non-contact state is smaller than the number of the connection pads having the same potential as the first layered electrode. In this manner, since the rod-shaped terminal connected to the connection pad having the same potential as the first layered electrode has a small number of passage holes through which the second layered electrode passes in a non-contact state, the second layer can be formed. Since the electrode has a large area, the layered capacitor portion can have a large electrostatic capacitance.

The printed wiring board of the present invention may have a configuration in which the mounting portion has a plurality of connection pads connected to the electrodes of the semiconductor element, and is electrically connected to a connection pad having the same potential as the second layer electrode. Further, the number of the rod-shaped terminals that pass the first layered electrode in a non-contact state is smaller than the number of the connection pads that have the same potential as the second layered electrode. In this manner, since the rod-shaped terminal connected to the connection pad having the same potential as the second layered electrode has a small number of passage holes through which the first layered electrode passes in a non-contact state, the first layer can be formed. Since the electrode has a large area, the layered capacitor portion can have a large electrostatic capacitance. In this case, the rod-shaped terminal connected to the connection pad having the same potential as the second layered electrode may be such that both the first layered electrode and the second layered electrode pass in a non-contact state.

Further, the two types of rod-shaped terminals (that is, the rod-shaped terminals electrically connected to the connection pads of the same potential as the first layered electrodes and passing the second layered electrodes in a non-contact state, and the electrical connection At least a portion of the rod-shaped terminal that is connected to the second layered electrode at the same potential and that allows the first layered electrode to pass in a non-contact state may be alternately arranged in a lattice shape or a cross shape. Thus, since the loop inductance is low, it is easier to prevent an instantaneous drop in the power supply potential.

The multilayer printed wiring board of the present invention may be configured such that the mounting portion has a first connection pad that is connected to one of a power supply electrode and a ground electrode of the semiconductor element, and is connected to the other side. In the second connection pad, one of the first connection pads has a first rod terminal through which the second layer electrode passes in a non-contact state, and is electrically connected to the first layer via the first rod terminal. The electrode of one of the electrode and the external power source does not have the first rod-shaped terminal, and is electrically connected to the first connection pad having the first rod-shaped terminal, and one of the second connection pads a second rod-shaped terminal that passes the first layered electrode in a non-contact state, and is electrically connected to the other electrode of the second layered electrode and the external electrode via the second rod-shaped terminal, and the remaining portion The portion itself does not have the second rod-shaped terminal and is electrically connected to the second connection pad having the second rod-shaped terminal. In this way, since the number of the first rod-shaped terminal and the second rod-shaped terminal can be reduced, the number of the through-holes through which the first layered electrode and the second layered electrode can pass can be reduced. The first and second layered electrodes have a large area, and the layered capacitor portion has a large electrostatic capacitance. For example, the first and second layered electrodes may be substantially flat-coated. Further, not only can the charge of the layered capacitor portion be charged from the external power source with a shorter wiring length, but also the power supply can be supplied to the semiconductor element from the layered capacitor portion with a shorter wiring length, so that the interval between the conduction and the disconnection is shorter. In the case of a semiconductor device of GHz to several tens of GHz (for example, 3 GHz to 20 GHz), a sufficient decoupling effect can be obtained, and a power shortage is unlikely to occur.

The multilayer printed wiring board of the present invention may have a configuration in which the mounting portion has a first connection pad connected to one of a power supply electrode and a ground electrode of the semiconductor element, and a second connection connected to the other of the semiconductor element In the pad, one of the first connection pads has a first rod-shaped terminal through which the second layered electrode passes in a non-contact state, and is electrically connected to the first layered electrode via the first rod-shaped terminal The electrode of one of the external power sources does not have the first rod-shaped terminal, and is electrically connected to the first connection pad having the first rod-shaped terminal, and one of the second connection pads has a portion The second layered terminal through which the first layered electrode and the second layered electrode pass in a non-contact state is connected to the other electrode of the external power source via the second rod terminal, and the remaining portion itself The second rod-shaped terminal is electrically connected to at least one of the second layered electrode and the second connecting pad having the second rod-shaped terminal. In this case, since the number of the first rod-shaped terminal and the second rod-shaped terminal can be reduced, the number of the through-holes through which the first layered electrode and the second layered electrode pass can be reduced. The first and second layered electrodes can have a large area, and the layered capacitor portion can have a large electrostatic capacitance. For example, the first and second layered electrodes may be substantially flat-coated. Further, not only can the charge of the layered capacitor portion be charged from the external power source with a shorter wiring length, but also the power supply can be supplied to the semiconductor element from the layered capacitor portion with a shorter wiring length, so that the interval between the conduction and the disconnection is shorter. In the case of a semiconductor device of GHz to several tens of GHz (for example, 3 GHz to 20 GHz), a sufficient decoupling effect can be obtained, and a power shortage is unlikely to occur.

At least a part of the first rod-shaped terminal and the second rod-shaped terminal of the multilayer printed wiring board having the first rod-shaped terminal and the second rod-shaped terminal may be alternately arranged in a lattice shape or a cross shape. Thus, since the loop inductance is low, it is easier to prevent an instantaneous drop in the power supply potential.

The multilayer printed wiring board of the present invention may have a configuration in which the distance between the first and second layered electrodes is set to be substantially less than 10 μm, and the short-circuit distance does not occur. Thus, since the distance between the electrodes of the layered capacitor portion is extremely small, the layered capacitor portion has a large electrostatic capacitance.

The layered capacitor portion of the multilayer printed wiring board of the present invention should be formed directly under the semiconductor element mounted on the mounting portion. In this way, the semiconductor element can be supplied with power with the shortest wiring length.

The multilayer printed wiring board of the present invention may have a chip capacitor that is provided on the first and second layered electrodes that are disposed on the surface side of the mounting portion and that are connected to the layered capacitor portion. Thus, when the static capacitance is insufficient due to only the layered capacitor portion, the wafer capacitor can be used to supplement the insufficient portion. In addition, the decoupling effect is lower because the wiring of the wafer capacitor and the semiconductor element is longer. However, since the wafer capacitor is provided on the surface side where the mounting portion is disposed, the wiring of the semiconductor element is shortened, so that decoupling can be suppressed. The effect is reduced. Further, since the wafer capacitor and the semiconductor element are connected via the layered capacitor portion, the loss of power supply to the semiconductor element by the wafer capacitor can be reduced.

The mounting portion of the multilayer printed wiring board of the present invention and the layered capacitor portion may have a stress relieving portion formed of an elastic material. In this manner, even if a stress is generated due to a difference in thermal expansion between the semiconductor element mounted on the mounting portion and the layered capacitor portion or the deposition portion, the stress relieving portion absorbs the stress, so that the connection reliability is lowered and the insulation reliability is less likely to occur. problem. Further, since the high dielectric layer of the layered capacitor portion is thin and brittle, cracking easily occurs. However, since the stress relieving portion is provided, cracking can be prevented. At this time, the stress relieving portion may be formed only under the semiconductor element mounted on the mounting portion. The stress caused by the difference in thermal expansion caused by the problem is mainly located directly under the semiconductor element, and if the stress relaxation portion is formed only in this portion, the material cost can be reduced. The material of the stress relaxation portion is not particularly limited, and for example, a recombinant epoxy resin sheet, a polyphenylene ether resin sheet, a polyimide film, a cyano ester resin sheet, and a sulfonamide resin can be used. An organic resin sheet such as a sheet. The organic resin sheet may contain a polyolefin resin of a thermoplastic resin, a polyimide resin, a thermosetting resin, a resin, a rubber resin such as SBR, NBR, or urethane, or may contain a dispersion. Inorganic fibrous, filler-like, or flat-like materials such as helium oxygen, aluminum oxide, and zirconium oxide. Further, the Young's modulus of the stress relaxation portion should be 10 to 1000 MPa. When the Young's modulus of the stress relaxation portion is in the above range, the stress can be alleviated when a stress is generated between the semiconductor element and the layered capacitor portion mounted on the mounting portion due to a difference in thermal expansion coefficient.

[Example 1]

Next, an embodiment of the present invention will be described with reference to the drawings. 1 is a plan view of a multilayer printed wiring board 10 according to an embodiment of the present invention, and FIG. 2 is a longitudinal sectional view of the multilayer printed wiring board 10 (only the left side of the center line is shown), and FIG. 3 is a layered capacitor portion. 40 mode oblique view. As shown in FIG. 2, the multilayer printed wiring board 10 of the present embodiment has a core substrate 20 that is electrically connected to the wiring pattern 22 formed on the front and back sides via the via hole conductor 24, and a through hole 34 that is located on the core substrate 20. Electrically connected to the deposition portion 30 in which the plurality of wiring patterns 32 and 22 are laminated via the resin insulating layer 36, the high dielectric layer 43 and the first and second layer electrodes sandwiching the high dielectric layer 43 The layered capacitor portion 40 composed of 41 and 42, the stress relieving portion 50 formed of an elastic material, the mounting portion 60 for mounting the semiconductor element, and the wafer capacitor arrangement region 70 disposed around the mounting portion 60.

The core substrate 20 has wiring patterns 22 and 22 made of copper formed on the front and back surfaces of a core substrate body 21 made of a BT (Bismaleimide-Triazine) resin, a glass epoxy substrate, or the like, and a through-core substrate. The through-hole conductors 24 made of copper on the inner side surface of the through-holes on the front and back sides of the main body 21 are electrically connected via the via-hole conductors 24.

In the stacking portion 30, the resin insulating layer 36 and the wiring pattern 32 are alternately laminated on the front and back surfaces of the core substrate 20, and the wiring patterns 32 are electrically connected via the through holes 34 penetrating the front and back surfaces of the resin insulating layer 36. Such a stacking portion 30 is formed by a well-known elimination method or an additive method (including a semi-additive method and a full-addition method), and can be formed, for example, in the following manner. That is, first, a resin sheet of the resin insulating layer 36 is attached to both front and back sides of the core substrate 20. Here, the Young's modulus of the resin insulating layer 36 at normal temperature is 2 to 7 GPa. The resin sheet is formed of a recombinant epoxy resin sheet, a polyphenylene ether resin sheet, a polyimide film, or a cyanoester resin sheet, and has a thickness of approximately 20 to 80 μm. The resin sheet may contain an inorganic component such as deuterium oxide, aluminum oxide, or zirconium oxide. Next, a through-hole is formed in the attached resin sheet by a carbon carbonate laser, a UV laser, a YAG laser, or an excited molecular laser or the like, and is used as the resin insulating layer 36 on the surface of the resin insulating layer 36 and Electroless copper plating is performed inside the through hole to form a conductor layer. A plating resist is formed on the conductor layer, and electrolytic copper plating is performed on a portion where the plating resist is not formed, and then the electroless copper plating under the plating resist is removed by an etching solution to form a wiring pattern 32. Further, the conductor layer inside the through hole is used as the through hole 34. Thereafter, this step is repeated to form the stacking portion 30.

The layered capacitor portion 40 is a high dielectric layer 43 formed by firing a ceramic high dielectric material at a high temperature, and a first layered electrode 41 and a second layer sandwiching the high dielectric layer 43. The electrode 42 is formed. The first layered electrode 41 of the layered capacitor portion 40 is a copper electrode, and is electrically connected to the grounding connection pad 61 of the mounting portion 60. The second layered electrode 42 is a copper electrode and is electrically connected to the power supply of the mounting portion 60. The connection pad 62 is used. Therefore, the first and second layered electrodes 41 and 42 are respectively connected to the ground line and the power supply line of the semiconductor element mounted on the mounting portion. Further, the first layered electrode 41 is formed in a flat coating pattern on the lower surface of the high dielectric layer 43, and has a through hole 41a that is connected to the through hole 62b of the power supply connection pad 62 in a non-contact state. Each of the power supply connection pads 62 is connected to the second layered electrode 42 via a through hole 62a, and the through hole 62b is disposed corresponding to the partial through hole 62a. Since each of the through holes 62a is connected to the second layered electrode 42, it is possible to connect to the ground line through the through hole 62b as long as it has at least one through hole 62b extending downward from the second layered electrode 42. On the other hand, the second layered electrode 42 is a flat coating pattern formed on the upper surface of the high dielectric layer 43, and has a through hole 42a that is connected to the through hole 61a of the grounding connection pad 61 in a non-contact state. Further, the distance between the first and second layered electrodes 41 and 42 is set to a distance of substantially no short circuit of 10 μm or less. Further, the high dielectric layer 43 is one or more selected from the group consisting of BaTiO ₃ , SrTiO ₃ , TaO ₃ , Ta ₂ O ₅ , PZT, PLZT, PNZT, PCZT, and PSZT. The high dielectric material of the metal oxide is formed into a film shape of 0.1 to 10 μm, and then fired to form a ceramic. Further, the manufacturing steps of the layered capacitor portion 40 will be described in detail later.

Here, the layered capacitor portion 40 will be further described in detail, and some of the descriptions are repeated with the previous description. The first layered electrode 41 of the layered capacitor portion 40 is electrically connected to the grounding connection pad 61 of the mounting portion 60 via the through hole 61a, and the second layered electrode 42 is electrically connected to the mounting portion 60 via the through hole 62a. The power supply connection pad 62. Therefore, the first and second layered electrodes 41 and 42 are respectively connected to the ground line and the power supply line of the semiconductor element mounted on the mounting portion 60. Further, the first layered electrode 41 is formed in a flat coating pattern on the lower surface of the high dielectric layer 43, and has a through hole 41a penetrating through the through hole 62b of the second layered electrode 42 in a non-contact state. Further, the through hole 62b may be disposed so as to correspond to all of the power supply connection pads 62. However, this is to provide a corresponding portion of the power supply connection pad 62. Since the second layered electrode 42 is connected to each of the power supply connection pads 62 via the respective through holes 62a, it is possible to pass through the through holes 62b as long as it has at least one through hole 62b extending downward from the second layered electrode 42. All power supply connection pads 62 are connected to an external power supply line. In this way, the through hole 62b is disposed so as to correspond to the portion of the power supply connection pad 62, so that the number of the through holes 41a disposed in the first layered electrode 41 can be reduced, so that the first layered electrode 41 has a large area. The layered capacitor portion 40 also has a large electrostatic capacitance. Further, the position at which the through hole 41a is formed should be determined after considering the electrostatic capacitance of the layered capacitor portion 40 and the arrangement of the through holes 62a. On the other hand, the second layered electrode 42 is a flat coating pattern formed on the upper surface of the high dielectric layer 43, and has a through hole 42a that is connected to the through hole 61a of the grounding connection pad 61 in a non-contact state. The hole 42a may be disposed so as to correspond to all of the grounding connection pads 61. However, the second layered electrode 42 is connected to the plurality of grounding connection pads 61 on the upper side, and only the partial grounding connection pads 61 are formed. The through hole 61a penetrates the through hole 42a of the second layered electrode 42 in a non-contact state. In this way, the through hole 61a is disposed so as to correspond to the partial grounding connection pad 61, so that the number of the through holes 42a disposed in the second layered electrode 42 can be reduced, so that the second layered electrode 42 has a large area. The layered capacitor portion 40 also has a large electrostatic capacitance. Further, the position at which the through hole 42a is formed should be determined after considering the electrostatic capacitance of the layered capacitor portion 40 and the arrangement of the through holes 62a.

The stress relieving portion 50 is formed of an elastic material. The elastic material is not particularly limited, and for example, an organic resin such as a recombined epoxy resin sheet, a polyphenylene ether resin sheet, a polyimide film, a cyano ester resin sheet, or a melamine resin sheet can be used. Sheet. The organic resin sheet may contain a polyolefin resin of a thermoplastic resin, a polyimide resin, a resin of a thermosetting resin, a rubber resin such as SBR, NBR, or urethane, or may contain a ruthenium oxide. Inorganic fibrous, filler-like or flat-shaped materials such as aluminum oxide and zirconium oxide. The Young's modulus of the stress relieving portion 50 should be a low value of 10 to 1000 MPa. When the Young's modulus of the stress relaxation portion 50 is in the above range, the stress is generated when a stress is generated between the semiconductor element and the layered capacitor portion mounted on the mounting portion 60 due to a difference in thermal expansion coefficient.

The mounting portion 60 is a region on which the semiconductor element is mounted, and is formed on the surface of the multilayer printed wiring board 10. The mounting portion 60 is provided with a ground connection pad 61, a power supply connection pad 62, and a signal connection pad 63 in a lattice shape or a cross shape (see FIG. 1). In addition, the grounding connection pad 61 and the power supply connection pad 62 may be arranged in a lattice shape or a cross shape in the vicinity of the center, and the signal connection pads 63 may be arranged in a lattice shape, a cross shape, or a random manner around the center. The grounding connection pad 61 and the power supply connection pad 62 should be arranged in an interactive manner. The number of terminals of the mounting portion 60 is 1000 to 300,000. A plurality of wafer capacitor arrangement regions 70 are formed around the mounting portion 60 (see Fig. 1). The wafer capacitor arrangement region 70 forms a plurality of pairs of ground connection pads 71 and power supply connection pads 72 for connecting the ground terminal and the power supply terminal of the wafer capacitor 73. Further, each of the grounding connection pads 71 is connected to the negative electrode of the external power source via the first layered electrode 41 of the layered capacitor portion 40, and each of the power source connection pads 72 is connected to the positive electrode of the external power source via the second layered electrode 42.

Next, an example of use of the multilayer printed wiring board 10 having such a configuration will be described. First, the power supply terminal and the grounding terminal of the wafer capacitor 73 are soldered to the ground connection pad 71 and the power supply connection pad 72 of the wafer capacitor arrangement region 70, respectively. Next, the semiconductor element on which the majority of the solder bumps are arranged on the back surface is placed on the mounting portion 60. At this time, the grounding terminal, the power supply terminal, and the signal terminal of the semiconductor element are brought into contact with the grounding connection pad 61 of the mounting portion 60, the power supply connection pad 62, and the signal connection pad 63, respectively. Next, each terminal is soldered by reflow soldering. Thereafter, the multilayer printed wiring board 10 is bonded to another printed wiring board such as a mother board. At this time, solder bumps are formed on the connection pads previously formed on the back surface of the multilayer printed wiring board 10, and are joined by reflow in a state of contacting the corresponding connection pads on the other printed wiring boards.

Next, the manufacturing steps of the multilayer printed wiring board 10 of the present embodiment will be described. Since the steps of fabricating the core substrate 20 and the stacking portion 30 are well known, the steps of fabricating the layered capacitor portion 40 and the stress relieving portion 50 will be mainly described. 4 to 7 are explanatory diagrams of this step.

First, as shown in Fig. 4(a), the core substrate 20 in which the deposition portion 30 is formed at least on one side is prepared, and the interlayer insulating layer 410 is attached by a vacuum laminator at a temperature of 50 to 150 ° C and a pressure of 0.5 to 1.5 MPa. Attached to the stacking portion 30. Then, the pre-made high dielectric sheet 420 is attached to the interlayer insulating layer 410 by a vacuum laminator at a temperature of 50 to 150 ° C and a pressure of 0.5 to 1.5 MPa, and then cured at 150 ° C for 3 hours ( Refer to Figure 4 (b)). Here, the high dielectric sheet 420 is produced in the following manner. That is, the copper foil 422 having a thickness of 12 μm (later the first layered electrode 41) is contained by BaTiO ₃ , SrTiO ₃ , TaO ₃ , Ta ₂ O ₅ , PZT, or the like by a press such as a roll coater or a doctor blade. A high dielectric material of one or more metal oxides selected from the group consisting of PLZT, PNZT, PCZT, and PSZT is printed as a film having a thickness of 0.1 to 10 μm, and is used as an unfired layer. After the printing, the unfired layer is fired in a vacuum or in a non-oxidizing atmosphere such as N ₂ gas at a temperature of 600 to 950 ° C, and is used as the high dielectric layer 424. Thereafter, a metal layer such as copper, platinum, or gold is formed on the high dielectric layer 424 by a vacuum vapor deposition apparatus such as sputtering, and copper, nickel, and tin are provided on the metal layer to a degree of 10 μm by electrolytic plating or the like. The metal is formed to form the upper metal layer 426 (later part of the second layered electrode 42). As a result, a high dielectric sheet 420 is obtained.

Next, the commercially available dry film 430 is attached to a substrate on which the high dielectric sheet 420 is laminated (see FIG. 4(c)), and is often used for patterning by using a multilayer printed wiring board. (Refer to Fig. 4 (d)), etching (see Fig. 4 (e)), and film peeling (see Fig. 4 (f)), patterning of the high dielectric sheet 420 is performed. Further, the etching step uses a copper chloride etching solution.

Next, the dry film 440 is again attached to the substrate in which the patterning of the high dielectric sheet 420 is performed (see Fig. 5(a)), and development is performed by exposure (see Fig. 5(b)). Patterning is performed by etching (see Fig. 5(c)) and film peeling (see Fig. 5(d)) to perform metal layer 426 and high dielectric layer 424 on high dielectric sheet 420. Further, the etching step uses a copper chloride etching solution, however, it is a short-time process in which only the copper foil 422 is slightly etched after being etched to the metal layer 426 and the high dielectric layer 424.

Next, on the substrate in which the patterning of the metal layer 426 and the high dielectric layer 424 has been performed, the interlaminar filling resin 450 is filled with a grout roll (see FIG. 5(e)), and Dry at 20 ° for 20 minutes. Here, 100 parts by weight of a bisphenol F-type epoxy monomer (manufactured by Japan Epoxy Resins Co., Ltd., molecular weight 310, trade name YL983U) and 72 parts by weight of a surface-covered decane coupling material were mixed and stirred in a container. SiO ₂ spherical particles having a maximum particle diameter of 15 μm or less (manufactured by ADTEC Corporation, trade name CRS1101-CE) having a particle diameter of 1.6 μm and 1.5 parts by weight of a leveling agent (manufactured by SAN NOPCO LIMITED, trade name: PELENOL S4) were used to prepare interlayers. The resin 450 for filling. Its viscosity is 30 to 60 Pa/s at 23 ± 1 °C. Further, as the hardener, 6.5 parts by weight of an imidazole hardener (manufactured by Shikoku Kasei Co., Ltd., trade name 2E4MZ-CN) was used. After the resin 450 is filled and dried, the surface of the substrate to be formed is polished until the surface of the upper metal layer 426 of the high dielectric sheet 420 is exposed, and planarization is performed. Next, 100 ° C for 1 hour and 150 ° C is performed. After the heat treatment for one hour, the resin 450 is hardened to form a high dielectric interlayer filling layer 452 (see Fig. 5 (f)).

Next, at a specific position on the surface of the substrate in which the high dielectric interlayer filling layer 452 is formed, a carbonate gas laser, a UV laser, a YAG laser, and an excited molecular laser are used to form the stacking portion 30. The through hole 454 on the surface of the wiring pattern 32 (refer to Fig. 6 (a)). Next, after the electroless plating catalyst is attached to the surface of the substrate to be fabricated, the substrate is immersed in an electroless copper plating aqueous solution, on the inner wall of the through hole 454, the surface of the high dielectric sheet 420, and the high dielectric. An electroless copper plating film 456 having a thickness of 0.6 to 3.0 μm is formed on the surface of the inter-layer filling layer 452 (see Fig. 6(b)). Further, the electroless plating aqueous solution is one having the following composition. Copper sulfate: 0.03 mol/L, EDTA: 0.200 mol/L, HCHO: 0.1 g/L, NaOH: 0.1 mol/L, α, α'-bisacridine: 100 mg/L, polyethylene glycol (PEG): 0.1 g/L.

Next, a commercially available dry film 460 is attached to the electroless copper plating film 456 (refer to Fig. 6 (c)), and exposure, development, and etching are performed to form a through hole 462 (see Fig. 6 (d)). On the surface of the through hole 462, an electrolytic copper plating film 464 having a thickness of 25 μm is formed (see Fig. 6(e)). Further, the electrolytic copper plating solution uses a composition having the following composition. Sulfuric acid: 200 g/L, copper sulfate: 80 g/L, and additive: 19.5 ml/L (manufactured by ATOTECH JAPAN Co., Ltd., KAPAROSHIDO GL). Further, electrolytic copper plating was carried out under the following conditions. The current density is 1 A/dm ² , the time is 115 minutes, and the temperature is 23 ± 2 ° C. Next, the dry film 460 is peeled off, and the portion of the dry film 460 remains, that is, the electroless copper plating film 456 existing between the electrolytic copper plating film 464 and the upper metal layer 426 of the high dielectric sheet 420. The exposed portion was etched with a sulfuric acid-hydrogen peroxide-based etching solution (see Fig. 6(f)). Through this step, the layered capacitor portion 40 can be formed on the stacking portion 30. That is, the copper foil 422 corresponds to the first layered electrode 41, and the high dielectric layer 424 corresponds to the high dielectric layer 43, the upper metal layer 426, the electroless copper plating film 456, and the electrolytic copper plating film 464. It corresponds to the second layered electrode 42.

Next, an aqueous solution containing NaOH (10 g/L), NaClO ₂ (40 g/L), and Na ₂ P0 ₄ (6 g/L) is treated as a blackening liquid on the substrate in which the electrolytic copper plating film 464 has been formed ( Blackening treatment of oxidizing solution), and reduction treatment of aqueous solution containing NaOH (10 g/L) and NaBH ₄ (6 g/L) as a reducing solution to make the surface of electrolytic copper plating film 464 a roughened surface (not shown) ). Then, the resin insulating sheet 470 is attached to the layered capacitor portion 40 by a vacuum laminator at a temperature of 50 to 150 ° C and a pressure of 0.5 to 1.5 MPa, and then cured at 150 ° C for 3 hours (see paragraph 7). Figure (a)). The resin insulating sheet 470 is a recombined epoxy resin sheet, a polyphenylene ether resin sheet, a polyimide film, a cyanoester resin sheet, or a melamine resin sheet, and may also contain a thermoplastic resin. A polyolefin resin such as a polyolefin resin, a polyimide resin, a thermosetting resin, or a rubber resin such as SBR, NBR, or urethane may contain inorganic ions such as deuterium oxide, aluminum oxide, or zirconium oxide. It is fibrous, filler-like, or flat. Further, the resin insulating sheet 470 should have a Young's modulus of 10 to 1000 MPa. When the Young's modulus of the resin insulating sheet 470 is in this range, the stress caused by the difference in thermal expansion coefficient between the semiconductor element and the substrate can be alleviated.

On the resin insulating sheet 470, a through hole 472 of Φ 65 μm was formed by a CO ₂ laser with a mask diameter of Φ 1.4 mm, an energy density of 2.0 mj, and a 1-stroke condition (see Fig. 7(b)). Thereafter, the film was immersed in a 60 g/L solution containing permanganic acid at 80 ° C for 10 minutes to roughen the surface of the resin insulating sheet 470. Next, the substrate which was subjected to roughening was immersed in a neutralizing solution (manufactured by Shipley Co., Ltd., trade name Circuit Board MLB NEUTRALIZER), and washed with water. Further, the substrate is immersed in a catalyst liquid containing palladium dichloride (PbCl ₂ ) and lanthanum chloride (SnCl ₂ ) to precipitate a palladium metal, and the palladium catalyst is attached to the surface of the resin insulating sheet 470 (including the through hole 472). The inner wall is included). Next, the substrate is immersed in an electroless copper plating aqueous solution, and treated at a liquid temperature of 34 ° C for 40 minutes to form an electroless copper plating film having a thickness of 0.6 to 3.0 μm on the surface of the resin insulating sheet 470 and the wall surface of the through hole 472. (not shown on the map). Further, the electroless copper plating aqueous solution uses a composition having the following composition. Copper sulfate: 0.03 mol/L, EDTA: 0.200 mol/L, HCHO: 0.1 g/L, NaOH: 0.1 mol/L, α, α'-bisacridine: 100 mg/L, polyethylene glycol (PEG): 0.1 g/L. Next, a dry film was formed on the electroless copper plating film, and an electrolytic copper plating film (not shown) having a thickness of 25 μm was formed under the following conditions. Further, the electrolytic copper plating solution uses a composition having the following composition. Sulfuric acid: 200 g/L, copper sulfate: 80 g/L, and additive: 19.5 ml/L (manufactured by ATOTECH JAPAN Co., Ltd., KAPAROSHIDO GL). Further, electrolytic copper plating is carried out under the following conditions. The current density is 1 A/dm ² , the time is 115 minutes, and the temperature is 23 ± 2 ° C. Next, the dry film 460 is peeled off, and the multilayer printed wiring board 10 corresponding to FIG. 1 and FIG. 2 is obtained (refer to FIG. 7(c)). Further, the resin insulating sheet 470 corresponds to the stress relaxing portion 50. Further, the copper plating film 474 filling the through holes 472 corresponds to the various terminals 61, 62, and 63.

After that, the commercially available solder resist composition is applied and dried, and then the side on which the chrome layer is formed is adhered to the solder resist layer so that a circular pattern in which the solder resist opening portion is drawn by the chrome layer is placed. The soda-lime glass substrate of the mask pattern is exposed to ultraviolet light. After development, heat treatment is performed to form a pattern of a solder resist layer on which openings are formed on the various terminals 61, 62, and 63, and then electroless nickel plating is performed and further Electroless gold plating is performed to form a nickel plating layer and a gold plating layer, and the solder paste is printed and reflowed to form a solder bump. Further, a solder resist layer may be formed or a solder resist layer may not be formed.

According to the multilayer printed wiring board 10 described in detail above, the high dielectric layer 43 of the layered capacitor portion 40 connected between the power supply line and the ground line is made of ceramic, compared with the conventional organic resin-containing organic resin. With a higher dielectric constant, the layered capacitor portion 40 also has a larger electrostatic capacitance. Therefore, in the case where the frequency at which the semiconductor element is turned on and off is a high number of GHz to several tens of GHz (3 GHz to 20 GHz), a sufficient decoupling effect can be exhibited, so that an instantaneous decrease in potential is less likely to occur.

Further, in general, since the deposition portion 30 is usually produced under a temperature condition of 200 ° C or lower, it is difficult to form a high dielectric material during the formation of the deposition portion 30 to be ceramic, in the above embodiment. Since the high dielectric layer 43 of the layered capacitor portion 40 is formed by firing a high dielectric material separately from the deposition portion 30, it is easy to have a sufficiently high dielectric constant.

Further, the first layered electrode 41 constituting the layered capacitor portion 40 is a flat coating pattern formed on the first surface of the high dielectric layer 43 which is distant from the mounting portion 60, that is, The flat coating pattern formed on the lower surface of the high dielectric layer 43 is formed by a flat coating pattern of the second surface closer to the mounting portion 60, that is, formed on the high dielectric layer 43. The upper flat pattern has a shape in which the through holes 61a connected to the first layered electrode 41 pass through the holes 42a in a non-contact state, so that the layered electrodes 41 and 42 have a large enough area. The layered capacitor portion 40 also has a large electrostatic capacitance. Here, the through hole 61a connected to the first layered electrode 41 and the through hole 62a connecting the second layered electrode 42 are arranged in a lattice-like manner, and the loop inductance is low, so that it is easy to prevent the instantaneous decrease of the power supply potential. . In addition, the through hole 61a and the through hole 62a may be alternately arranged in a cross shape, and the same effect can be obtained.

Further, since the distance between the first and second layered electrodes 41 and 42 of the layered capacitor portion 40 is set to be substantially less than 10 μm, the distance between the electrodes of the layered capacitor portion 40 is extremely small, so that the distance between the electrodes of the layered capacitor portion 40 is extremely small. The layered capacitor portion 40 also has a large electrostatic capacitance.

Next, when the static capacitance is insufficient due to only the layered capacitor portion 40, the wafer capacitor 73 can be used to supplement the insufficient portion. In other words, the wafer capacitor 73 can be mounted as needed. Further, the decoupling effect is lower because the wiring of the wafer capacitor 73 and the semiconductor element is longer. However, since the wafer capacitor 73 is provided on the surface side of the mounting portion 60, the wiring of the semiconductor element is shortened, so that decoupling can be suppressed. The effect is reduced.

Further, even if the semiconductor element mounted on the mounting portion 60 and the layered capacitor portion 40 or the deposition portion 30 are stressed due to a difference in thermal expansion, the stress relieving portion 50 can absorb the stress without causing a problem. Further, the stress relaxing portion 50 may be formed only under the semiconductor element mounted on the mounting portion 60. The stress caused by the difference in thermal expansion which causes problems is mainly located directly under the semiconductor element, and if the stress relieving portion 50 is formed only in this portion, the material cost can be reduced.

Further, the present invention is not limited to the above embodiments, and may be various embodiments as long as it falls within the technical scope of the present invention.

[Embodiment 2]

Fig. 8 is a longitudinal sectional view showing the multilayer printed wiring board 110 of the second embodiment (only the left side of the center line is shown). As shown in FIG. 8, the multilayer printed wiring board 110 of the present embodiment has the core substrate 20 similar to that of the first embodiment, and the through hole 34 on the upper surface of the core substrate 20 is electrically connected to each other via the resin insulating layer 36. The stacked wiring pattern 22 and the stacked portion 30 of the wiring pattern 32, the interlayer insulating layer 120 laminated on the deposition portion 30, the high dielectric layer 143 laminated on the interlayer insulating layer 120, and the high dielectric layer sandwiched therebetween The layered capacitor portion 140 including the first and second layered electrodes 141 and 142 of 143, the stress relieving portion 150 formed of an elastic material laminated on the layered capacitor portion 140, and the mounting portion 160 for mounting the semiconductor element And a wafer capacitor arrangement region 170 disposed around the mounting portion 160.

The first layered electrode 141 of the layered capacitor portion 140 of the present embodiment is a copper electrode, and is electrically connected to the grounding connection pad 161 of the mounting portion 160 via the through hole 161a, and the second layered electrode 142 is a copper electrode. The hole 162a is electrically connected to the power supply connection pad 162 of the mounting portion 160. Therefore, the first and second layered electrodes 141 and 142 are respectively connected to the ground line and the power supply line of the semiconductor element mounted on the mounting portion 160.

Further, the first layered electrode 141 is a flat coating pattern formed on the lower surface of the high dielectric layer 143, and has a through hole 141a penetrating through the through hole 162b of the second layered electrode 142 in a non-contact state. The through hole 162b may be disposed corresponding to all of the power supply connection pads 162, and is disposed to correspond to a part of the power supply connection pads 162. The reason is as follows. In other words, the plurality of power supply connection pads 162 of the power supply connection pads 162 are electrically connected to the second layered electrode 142 via the through holes 162a, and the remaining power supply connection pads 162 are electrically connected via the through holes 162a. The other power supply connection pads 162 of the second layered electrode 142 and the unillustrated wirings (for example, the wirings disposed on the mounting portion 160) are electrically connected, so that all the power supply connection pads 162 are connected to the first The two layered electrodes 142 can have all of the power supply connection pads 162 connected to the external power supply line via the through holes 162b as long as they have at least one through hole 162b extending downward from the second layered electrode 142. Next, the through hole 162b is provided corresponding to the portion of the power supply connection pad 162, and the number of the through holes 141a disposed in the first layered electrode 141 can be reduced. The first layered electrode 141 has a large area, and the layered capacitor The portion 140 also has a large electrostatic capacitance. Further, the number of the through holes 141a and the position at which the through holes 141a are formed should be determined after considering the arrangement of the electrostatic capacitance of the layered capacitor portion 140 and the through holes 162a.

On the other hand, the second layered electrode 142 is a flat coating pattern formed on the upper surface of the high dielectric layer 143, and has a through hole 142a that is connected to the through hole 161a of the ground connection pad 161 in a non-contact state. The through hole 161a may be disposed so as to correspond to all of the grounding connection pads 161. However, the through holes 161a are provided so as to correspond to the partial grounding connection pads 161. The reason is as follows. In other words, the grounding connection pads 161 are electrically connected by wires (not for example, the wires disposed on the mounting portion 160), which are not shown in the drawings, and have at least one non-contact extending from the grounding connection pads 161 downward. The second layered electrode 142 is in contact with the through hole 161a of the first layered electrode 141, and all of the grounding connection pads 161 can be connected to the external ground line via the through hole 161a. Next, the through hole 161a is disposed corresponding to the portion of the grounding connection pad 161, and the number of the through holes 142a disposed in the second layered electrode 142 can be reduced. The second layered electrode 142 has a large area, and the layered capacitor The portion 140 also has a large electrostatic capacitance. Further, the number of the through holes 142a and the position at which the through holes 142a are formed should be determined after considering the arrangement of the electrostatic capacitance of the layered capacitor portion 140 and the through holes 161a.

As described above, since the layered capacitor portion 140 can have a large electrostatic capacitance, a sufficient decoupling effect can be exhibited, and the transistor of the semiconductor element (IC) mounted on the mounting portion 160 is less likely to be insufficient in power supply. In addition, a wiring for electrically connecting the grounding connection pad 161 having no through hole directly underneath, and a grounding connection pad 161 having a through hole directly under the hole, and a connection pad 162 for electrically connecting the power supply without a through hole directly underneath The wiring of the power supply connection pad 162 having the through hole may be disposed on the mounting portion 60 or may be disposed on the surface of the core substrate 20 or the stacking portion 30. Further, a wiring layer may be further disposed between the layered capacitor portion 140 and the mounting portion 160 to connect the layers.

The stress relieving portion 150 is formed of the same elastic material as that of the first embodiment. In addition, the grounding connection pads 161, the power supply connection pads 162, and the signal connection pads 163 disposed in the mounting portion 160 are arranged in a lattice shape or a cross shape (see FIG. 1). In addition, the grounding connection pad 161 and the power supply connection pad 162 may be arranged in a lattice shape or a cross shape in the vicinity of the center, and the signal connection pads 163 may be arranged in a lattice shape, a cross shape, or a random manner around the center. The number of terminals of the mounting portion 160 is 1000 to 300,000. A plurality of wafer capacitor arrangement regions 170 are formed around the mounting portion 160, and a plurality of pairs of ground connection pads 171 and power sources for connecting the ground terminals and the power supply terminals of the wafer capacitor 173 are formed in the wafer capacitor arrangement region 170. Bonding pad 172.

Each of the grounding connection pads 171 is connected to the negative electrode of the external power source via the first layered electrode 141 of the layered capacitor portion 140, and each of the power supply connection pads 172 is connected to the positive electrode of the external power source via the second layered electrode 142. The grounding connection pad 161 and the power supply connection pad 162 of the present embodiment correspond to the first connection pad and the second connection pad of the eighth aspect of the patent application, respectively, and the through hole 161a and the through hole 162b correspond to the patent application scope, respectively. The first rod terminal and the second rod terminal of the eight items.

Next, the manufacturing steps of the multilayer printed wiring board 110 of the present embodiment will be described with reference to FIGS. 9 to 11 .

First, as shown in Fig. 9(a), the substrate 500 having the deposition portion 30 formed on at least one side of the core substrate 20 is prepared, and the interlayer is laminated by a vacuum laminator at a temperature of 50 to 150 ° C and a pressure of 0.5 to 1.5 MPa. The insulating layer 510 (a thermosetting insulating film which is the interlayer resin layer 120 of FIG. 8 and ABF-45SH manufactured by AJINOMOTO Co., Ltd.) is attached to the deposition portion 30. Next, a high dielectric sheet 520 having a structure in which a copper foil 522 and a copper foil 526 are sandwiched between the high dielectric layer 524 and a copper foil 522 and a copper foil 526 are laminated by a vacuum laminator at a temperature of 50 to 150 ° C and a pressure of 0.5 to 105 MPa. It was attached to the interlayer insulating layer 510, and thereafter dried at 150 ° C for 1 hour (refer to Fig. 9 (b)). The two copper foils 522, 526 of the high dielectric sheet 520 during lamination should all be flat coatings without forming an electrical circuit. If one part of the two copper foils 522, 526 is removed by etching or the like, (i) the metal residual ratio of the front and back sides may change, or the high dielectric sheet may be formed into a meandering shape by using the removed portion as a starting point, (ii) If a part of the copper foil is removed to form a corner (refer to Fig. 12), the lamination pressure will concentrate on the portion, and (iii) the high dielectric layer is likely to be generated because the laminator directly contacts the high dielectric layer. Cracking, in the subsequent plating step, if the cracked portion is plated, a short circuit is formed between the two copper foils. Further, if some of the electrodes are removed before lamination, the problem of a decrease in the electrostatic capacitance of the high dielectric sheet is caused, and when the stack of the high dielectric sheets is carried out, the position of the high dielectric sheet and the stacking portion must be performed. Align and fit again. In addition, since the high dielectric sheet is thin and not rigid, the positional accuracy when removing a part of the copper foil is inferior. Further, in consideration of the adjustment precision, it is necessary to remove a part of the copper foil, so that it is necessary to remove a large amount of copper foil, and the accuracy of the alignment is also deteriorated due to the thinness of the high dielectric sheet. For the above reasons, the two copper foils 522, 526 of the high dielectric sheet 520 during lamination should all be flat coatings without forming an electrical circuit.

Next, a description will be given of a manufacturing procedure of the high dielectric sheet 520.

(1) Dissolving 1.0 mil/liter of diethoxy ruthenium and bis-tetraisopropoxy titanium in a mixed solvent of dehydrated methanol and 2-methylglycol in a dry nitrogen (volume ratio 3) : 2), stirring for 3 days under a nitrogen atmosphere at room temperature, and adjusting the alkoxide precursor composition solution of bismuth and titanium. Next, the stirring of the precursor composition solution was carried out at 0 ° C, and water sprayed in advance by decarboxylation treatment was carried out in a nitrogen stream at a rate of 0.5 μl/min to carry out hydrolysis.

(2) The precipitates and the like of the sol-gel solution prepared in this manner were filtered out using a 0.2 μm filter.

(3) The filtrate prepared in the above (2) was spin-coated at 1500 rpm for 1 minute on a copper foil 522 (hereinafter, the first layered electrode 141) having a thickness of 12 μm. The substrate coated with the solution was placed on a hot plate maintained at 150 ° C and dried for 3 minutes. Thereafter, the substrate was placed in an electric furnace maintained at 850 ° C and fired for 15 minutes. Here, the viscosity of the molten gel solution was adjusted so that the film thickness was 0.03 μm by one spin coating/drying/baking. Further, in addition to copper, the first layered electrode 141 may be nickel, platinum, gold, silver or the like.

(4) Spin coating/drying/baking was repeated 40 times to obtain a 1.2 μm high dielectric layer 524.

(5) Thereafter, a copper layer is formed on the high dielectric layer 524 by a vacuum vapor deposition apparatus such as sputtering, and copper is formed on the copper layer to a level of 10 μm by electrolytic plating or the like to form a copper foil 526 (later) One of the two layered electrodes 142). In this way, a high dielectric sheet 520 can be obtained. The dielectric properties were measured using an INPEDANCE/GAIN PHASE ANALYZER (manufactured by HEWLETT-PACHARD, product name: 4194A) at a frequency of 1 kHz, a temperature of 25 ° C, and an OSC level of 1 V. The relative dielectric constant was 1.850. Further, a metal layer such as platinum or gold other than copper may be formed by vacuum evaporation, or a metal layer such as nickel or tin other than copper may be formed by electrolytic plating. In addition, the high dielectric layer is barium titanate. However, with other lyophilized solutions, the high dielectric layer may also be barium titanate (SrTiO ₃ ), yttrium oxide (TaO ₃ , Ta ₂ O ₅ ), zirconium. Lead titanate (PZT), lead zirconate titanate (PLZT), lead zirconate titanate (PNZT), lead zirconate titanate (PCZT), and lead zirconate titanate (PSZT).

In addition, the high dielectric sheet 520 can also be fabricated by other methods. In other words, barium titanate powder (manufactured by FUTI TITANIUM INDUSTRY, HPBT series) is dispersed in 5 parts by weight of polyvinyl alcohol, 50 parts by weight of pure water, and 1 part by weight based on the total weight of the barium titanate powder. As a solvent-based plasticizer, the binder solution is mixed in the ratio of diisooctyl phthalate or dibutyl phthalate, and the thickness is measured by a press such as a roll coater, a doctor blade, and an alpha coater. The 12 μm copper foil 522 (later the first layered electrode 141) is printed into a film having a thickness of about 5 to 7 μm, and is subjected to 1 hour at 60 ° C, 3 hours at 80 ° C, 1 hour at 100 ° C, and 1 at 120 ° C. It is dried in an hour and at a temperature of 150 ° C for 3 hours, and is used as an unfired layer. One selected from the group consisting of SrTiO ₃ , TaO ₃ , Ta ₂ O ₅ , PZT, PLZT, PNZT, PCZT, and PSZT other than BaTiO ₃ can also be used by a printer such as a roll coater or a doctor blade. Or a paste of two or more kinds of metal oxides is printed into a film having a thickness of 0.1 to 10 μm, dried, and used as an unfired layer. After the printing, the unfired layer is fired in a temperature range of 600 to 950 ° C to obtain a high dielectric layer 524. Thereafter, a copper layer is formed on the high dielectric layer 524 by a vacuum vapor deposition apparatus such as sputtering, and copper is formed on the copper layer to a level of 10 μm by electrolytic plating or the like to form a copper foil 526 (later layer 2) One of the electrodes 142). Further, a metal layer such as platinum or gold other than copper may be formed by vacuum evaporation, or a metal layer such as nickel or tin other than copper may be formed by electrolytic plating. Others, sputtering using barium titanate as a target can also be used.

Next, the through holes 530 and 531 are formed by using a carbon dioxide laser, a UV laser, a YAG laser, and an excited molecular laser at a specific position of the substrate in which the high dielectric sheet 520 is laminated. Figure 9 (c)). The through hole 530 having a deep depth penetrates the through hole of the high dielectric sheet 520 and the interlayer insulating layer 510 reaching the surface of the wiring pattern 32 of the deposition portion 30. The through hole 531 having a shallow depth is a through hole of the copper foil 526 and the high dielectric layer 524 reaching the surface of the copper foil 522. Here, the through hole is formed, and a deep through hole 530 is formed first, and then a shallow through hole 531 is formed. The depth adjustment is performed by changing the number of laser strokes. Specifically, the through hole 531 is implemented by a UV laser manufactured by Hitachi Via Mechanics, Ltd., and is output under the conditions of an output of 3 to 10 W, a frequency of 30 to 60 kHz, and a stroke number of 4. The through hole 530 is except for the number of strokes of 31. The conditions are the same. Then, the through-hole filling resin 532, which will be described later, is filled in the through holes 530 and 531, and dried at 80 ° C for 1 hour, at 120 ° C for 1 hour, and at 150 ° C for 30 minutes (see Fig. 9 (d)). . Further, the through holes 530 and 531 are not formed so as to correspond to all of the power supply connection pads 162 and the ground connection pads 161 shown in FIG.

The resin for through-hole filling was produced by the following method. 100 parts by weight of a bisphenol F type epoxy monomer (manufactured by Japan Epoxy Resins Co., Ltd., molecular weight: 310, trade name: E-807), and 6 parts by weight of an imidazole hardener (four countries) , trade name: 2E4MZ-CN), and 170 parts by weight of SiO ₂ spherical particles having an average particle diameter of 1.6 μm were mixed into the mixture, and kneaded by three rolls to have a viscosity of 23 ± 1 ° C of the mixture. The resin for filling the through holes was obtained by adjusting 45,000 to 49000 cps.

Next, the through-holes 530a and 531a are formed by the through-hole filling resin 532 which is filled in the previous step, and the permanganic acid solution is immersed and roughened, and then dried and hardened at 170 ° C for 3 hours to completely harden (see 9 (e)). The through hole 530a penetrates the through hole of the through hole filling resin 532 that reaches the surface of the wiring pattern 32 of the deposition portion 30. The other through hole 531a penetrates the through hole of the through hole filling resin 532, the copper foil 522, and the interlayer insulating layer 510 to the surface of the wiring pattern 32 of the deposition portion 30. Further, the through hole 530a is formed by a CO ₂ laser with a mask diameter of Φ 1.4 mm, an energy density of 2.0 mj, and a 2-stroke condition, and the formation of the through hole 531a is performed except for the 52-stroke by UV laser. The conditions are the same (output: 3 to 10w, frequency: 30 to 60 kHz).

Thereafter, the electroless copper plating catalyst is adhered to the surface of the substrate and immersed in the electroless copper plating solution to form an electroless copper plating film 540 of 0.6 to 3.0 μm on the surface of the substrate (see Fig. 10 (a)). . Further, the electroless copper plating aqueous solution uses a composition having the following composition. Copper sulfate: 0.03 mol/L, EDTA: 0.200 mol/L, HCHO: 0.1 g/L, NaOH: 0.1 mol/L, α, α'-bisacridine: 100 mg/L, polyethylene glycol (PEG) 0.1 g/L.

Next, a dry film of a commercially available product is attached to the electroless copper plating film 540, and exposure and development are performed to form a plating resist 541 (refer to FIG. 10(b)), and a thickness of 25 μm is formed in a portion where the plating resist is not formed. Electrolytic copper plating film 542 (refer to Fig. 10 (c)). Further, the electrolytic copper plating solution uses a composition having the following composition. Sulfuric acid: 200 g/L, copper sulfate: 80 g/L, and additive: 19.5 ml/L (manufactured by ATOTECH JAPAN Co., Ltd., KAPAROSHIDO GL). Further, electrolytic copper plating was carried out under the following conditions. The current density is 1 A/dm ² , the time is 115 minutes, and the temperature is 23 ± 2 ° C. Next, the plating resist 541 is peeled off, and a portion of the plating resist 541 remaining thereon is etched with a sulfuric acid-hydrogen peroxide-based etching solution, that is, a sulfuric acid-hydrogen peroxide-based etching solution is present between the electrolytic copper plating films 542. The electroless copper plating film 540 is etched (rapidly etched) to form a molding section 544 that is coupled to the upper electrode 543 and the copper foil 522 (see FIG. 10(d)).

Next, the stress relieving sheet 550 (the stress relieving portion 150 of FIG. 8) is attached to the upper electrode 543 and the forming section 544 at a temperature of 50 to 150 ° C and a pressure of 0.5 to 1.5 MPa, and is 150 degrees. It is dried for 1 hour (refer to Fig. 10 (e)).

The stress relieving sheet 550 was produced by the method shown below. In other words, 100 parts by weight of a naphthalene type epoxy resin (manufactured by Nippon Kayaku Co., Ltd., trade name: NC-7000L) and 20 parts by weight of phenol-two are dissolved by a roll coater (manufactured by CERMA TRONICS Trading Co., Ltd.). Toluene glycol condensed resin (manufactured by Mitsui Chemicals, trade name: XLC-LL), 90 parts by weight of carboxylic acid-denatured NBR (manufactured by Mitsui Chemicals Co., Ltd.) having a Tg of -50 ° C (JSR), trade name: XER- 91), and 4 parts by weight of a resin composition of 300 parts by weight of ethyl lactate of 1-cyanoethyl-2-ethyl-4-methylimidazole, coated on polymethylpentene (TPX) (Mitsui Petroleum) It is made of a chemical industry product, trade name: OPULENT X88) on a film having a thickness of 42 to 45 μm, and then dried at 80 ° C for 2 hours, at 120 ° C for 1 hour, and at 150 ° C for 30 minutes to obtain a stress relaxation sheet having a thickness of 40 μm. . Further, the Young's modulus of the stress-relieving sheet was 500 MPa at 30 °C.

Secondly, at a specific position of the stress relieving sheet 550, a CO ₂ laser is used to A mask diameter of 1.4 mm, an energy density of 2.0 mj, and a through hole 560 are formed in one stroke (refer to Fig. 11 (a)). Next, the roughening treatment and dry curing at 150 ° C for 3 hours were carried out to completely cure the stress relieving sheet 550. Thereafter, a step of attaching a catalyst, chemical copper, plating formation, electroplating copper, plating peeling, and rapid etching is performed to fill the metal to the via 560, and a bonding pad is formed on each of the via holes 560 of the outermost layer (grounding) The multilayer printed wiring board 110 having the mounting portion 160 is obtained by the connection pad 161, the power supply connection pad 162, and the signal connection pad 163) (Fig. 11(b)). Further, the grounding connection pads 161 connected to the molding section 544 and the copper foil 542 are connected to the grounding wire, and the power supply connection pads 162 connected to the upper electrode 543 are connected to the power supply line. Further, the signal connection pad 163 is connected to the signal line. Here, the copper foil 522 corresponds to the first layered electrode 141, the copper foil 526 and the upper electrode 543 correspond to the second layered electrode 142, and the high dielectric layer 524 corresponds to the high dielectric layer 143. Capacitor portion 140.

Thereafter, solder bumps may be formed on the respective terminals of the mounting portion 60 (for the formation method, refer to the first embodiment). Further, when the wafer capacitor 173 is mounted as shown in FIG. 8, after the step (b) of FIG. 9, an etching step of electrically connecting one of the terminal terminals of the wafer capacitor 173 and the first layered electrode 141 by the conductor 562 is performed. (The so-called masking method). This etching step uses a copper chloride etching solution. However, after etching to the copper foil 526 and the high dielectric layer 524, only a small amount of etching of the copper foil 522 is performed for a short time. Finally, the metal layer bonded to the copper foil 522 is disposed on the stress relaxation sheet 550, and the connection pad 171 is disposed on the metal layer. Further, a connection pad 172 for the purpose of connecting the other terminal of the wafer capacitor 173 is formed on the metal filled on one of the through holes 560 formed in the stress relaxation sheet 550.

According to the multilayer printed wiring board 110 of the second embodiment described in detail above, the same effects as those of the above-described first embodiment can be obtained. In the present embodiment, the relative area S of the first layered electrode 141 and the second layered electrode 142 is determined such that the electrostatic capacitance C of the layered capacitor portion 140 directly under the module is 0.5 μF, and The area S determines the number and position of the through holes 141a of the first layered electrode 141 and the number and position of the through holes 142a of the second layered electrode 142. Here, the relative area S is calculated by C = ε ₀ ‧ ε _r ‧ d / S. That is, since the relative dielectric constant ε _r of the high dielectric layer 142 is 1850 and the thickness d thereof is 1.2 μm, the value is substituted into the above equation, and the electrostatic capacitance C is substituted at 0.5 μF to calculate the relative area S. Further, ε ₀ is a dielectric constant (fixed number) at the time of vacuum.

[Example 3]

Fig. 13 is a longitudinal sectional view showing the multilayer printed wiring board 210 of the third embodiment (only the left side of the center line is shown). As shown in FIG. 13, the multilayer printed wiring board 210 of the present embodiment has a core substrate 20 similar to that of the first embodiment, and a via hole 34 located on the upper surface of the core substrate 20 is electrically connected to each other via the resin insulating layer 36. The stacked wiring pattern 22 and the stacked portion 30 of the wiring pattern 32, the interlayer insulating layer 220 laminated on the deposition portion 30, the high dielectric layer 243 laminated on the interlayer insulating layer 220, and the high dielectric layer sandwiched therebetween a layered capacitor portion 240 composed of the first and second layered electrodes 241 and 242 of 243, an interlayer insulating layer 245 laminated on the layered capacitor portion 240, and a stress layer formed of an elastic material laminated on the interlayer insulating layer 245 The damper portion 250, the mounting portion 260 for mounting the semiconductor element, and the wafer capacitor arrangement region 270 disposed around the mounting portion 260.

The first layered electrode 241 of the layered capacitor portion 240 of the present embodiment is a copper electrode formed in a flat pattern on the lower surface of the high dielectric layer 243, and is electrically connected to the ground connection pad 261 of the mounting portion 260. In the description, the grounding connection pad 261 is divided into two types of the ground connection pad 261x and the ground connection pad 261y. The grounding connection pad 261x is electrically connected to the forming section 266x via the through hole 261a. There is no through hole directly below the forming section 266x. Further, the grounding connection pad 261y is coupled to the molding section 266y via the through hole 261a, and the molding section 266y is electrically connected to the grounding wiring of the wiring pattern 32 of the first layered electrode 241 and the deposition section 30 via the through hole 261b. Further, the forming section 268 connected to the through hole 261b and the second layered electrode 242 are electrically separated. Further, the forming section 266x connected to the grounding connection pad 261x and the molding section 266y connected to the grounding connection pad 261y are electrically connected by a wiring 246 (see FIG. 14). As a result, all of the grounding connection pads 261 will have the same potential. In this way, the first layered electrode 241 is connected to the grounding wire of the wiring pattern 32 of the deposition portion 30 in addition to the grounding connection pad 261, and is connected to the external ground line via the grounding wire. In addition, the first layered electrode 241 has a through hole 241a that penetrates the through hole 262c described later in a non-contact state. However, the through hole 262c is disposed so as to correspond to the finite power supply connection pad 262y as will be described later. Only a small number of passage holes 241a are required. As a result, the first layered electrode 241 has a large area, and the layered capacitor portion 240 also has a large electrostatic capacitance. Further, the number of the holes 241a and the position at which the holes 241a are formed should be determined after considering the static capacitance of the layered capacitor portion 240 or the like.

On the other hand, the second layered electrode 242 is a copper electrode formed in a flat pattern on the upper surface of the high dielectric layer 243, and is electrically connected to the power supply connection pad 262 of the mounting portion 260. In the description, the power supply connection pad 262 is divided into two types of the power supply connection pad 262x and the power supply connection pad 262y. The power supply connection pad 262x is connected to the molding segment 267x via the through hole 262a, and the molding segment 267x is electrically connected to the second layer electrode 242 via the through hole 262b. Further, the power supply connection pad 262y is coupled to the molding section 267y via the through hole 262a, and the molding section 267y is electrically connected to the deposition section 30 via the through hole 262c so as not to contact the first and second layered electrodes 241 and 242. The power supply wiring among the wiring patterns 32. In addition, the molding section 267x connected to the power supply connection pad 262x and the molding section 267y connected to the power supply connection pad 262y are electrically connected by a wiring 247 (see FIG. 14). As a result, all of the power supply connection pads 262 will have the same potential. In addition to the power supply connection pads 262, the second layer electrode 242 is connected to the power supply wiring of the wiring pattern 32 of the deposition unit 30, and is connected to the external power supply line via the power supply wiring. Therefore, the second layered electrode 242 can be supplied with power from the power supply wiring of the wiring pattern 32 of the deposition portion 30 via the through hole 262c, the wiring 247, and the through hole 262b. Further, the second layered electrode 242 has a through hole 242a that penetrates the through hole 262c in a non-contact state, and a through hole 242b for the purpose of ensuring insulation with the forming section 268. However, the through hole 262c is disposed in the power supply connection pad 262. One of the power supply connection pads 262y and the through hole 242b are disposed so as to correspond to a ground connection pad 261y of a portion of the ground connection pad 261, so that fewer pass holes 242a, 242b are provided. number. As a result, the second layered electrode 242 has a large area, and the layered capacitor portion 240 also has a large electrostatic capacitance. Further, the number of the through holes 242a and 242b and the position at which the through holes 242a and 242b are formed should be determined after considering the static capacitance of the layered capacitor portion 240 or the like.

As described above, since the layered capacitor portion 240 can have a large electrostatic capacitance, it has a sufficient decoupling effect, and the transistor of the semiconductor element (IC) mounted on the mounting portion 260 is less likely to be insufficient in power supply. In addition, the grounding connection pad 261x and the grounding connection pad 261y are connected via the wiring 246 on the interlayer insulating layer 245, and the power supply connection pad 262x and the power supply connection pad 262y are connected via the wiring 247 on the interlayer insulating layer 245. However, such a wiring may be disposed on any one of the layers above the second layered electrode (the mounting portion may be), the surface of the core substrate 20, and the deposition portion 30. In addition, when the grounding connection pad 261x and the grounding connection pad 261y, and the power supply connection pad 262x and the power supply connection pad 262y are connected to each other, it is not necessary to arrange the through hole 261a in all of the ground connection pads 261. Below, and without the need to arrange the through holes 262a directly under the power supply connection pads 262. In this way, the number of forming segments of the layer directly below the mounting portion can also be reduced. Therefore, since the number of through holes and the number of forming sections that must be disposed can be reduced, the density can be increased.

The stress relieving portion 250 is formed of the same elastic material as in the first embodiment. In addition, the grounding connection pad 261, the power supply connection pad 262, and the signal connection pad 263 which are disposed in the attachment portion 260 are arranged in a lattice shape or a cross shape in the same manner as in the first embodiment (see FIG. 1). Further, the number is also the same as that of the first embodiment. Here, the signal connection pad 263 does not contact any one of the first and second layered electrodes 241 and 242 of the layered capacitor portion 240. In addition, the grounding connection pad 261 and the power supply connection pad 262 may be arranged in a lattice shape or a cross shape in the vicinity of the center, and the signal connection pads 263 may be arranged in a lattice shape, a cross shape, or a random manner around the center. A plurality of wafer capacitor arrangement regions 270 are formed around the mounting portion 260, and the wafer capacitor arrangement region 270 forms a plurality of ground connection pads 271 and power supply connection pads for connecting the ground terminal and the power supply terminal of the wafer capacitor 273. 272.

Each of the grounding connection pads 271 is connected to the negative electrode of the external power source via the first layered electrode 241 of the layered capacitor portion 240, and each of the power source connection pads 272 is connected to the positive electrode of the external power source via the second layered electrode 242. The grounding connection pad 261 and the power supply connection pad 262 of the present embodiment correspond to the first connection pad and the second connection pad of claim 9 respectively, and the through hole 261b and the through hole 262c are respectively equivalent to the patent application scope. The first rod terminal and the second rod terminal of the ninth item.

Each of the grounding connection pads 271 is connected to the negative electrode of the external power source via the first layered electrode 241 of the layered capacitor portion 240, and each of the power supply connection pads 272 is connected to the positive electrode of the external power source via the second layered electrode 242. The grounding connection pad 261 and the power supply connection pad 262 of the present embodiment correspond to the first connection pad and the second connection pad of the sixth item of the patent application, respectively, and the through holes 261a and 261b and the through holes 262a and 262b are respectively It corresponds to the first rod terminal and the second rod terminal of the sixth item of the patent application.

Next, a manufacturing procedure of the multilayer printed wiring board 210 of the present embodiment will be described with reference to Figs. 15 to 17 . In addition, FIG. 13 and FIG. 14 are diagrams in which the power supply connection pads 261 and the ground connection pads 262 are arranged in a lattice shape or a cross shape directly under the semiconductor element (that is, directly under the module). In the cross-sectional view, FIG. 15 to FIG. 17 are cross-sectional views showing a portion in which the power supply connection pad 261 and the ground connection pad 262 are alternately arranged.

First, as shown in Fig. 15 (a), the substrate 600 having the deposition portion 30 formed on at least one side of the core substrate 20 is prepared, and the interlayer is laminated by a vacuum laminator at a temperature of 50 to 150 ° C and a pressure of 0.5 to 1.5 MPa. The insulating layer 610 (thermosetting insulating film, ABF-45SH, manufactured by AJINOMOTO Co., Ltd.) is attached to the deposition portion 30. Next, a high dielectric sheet 620 (the production step is the same as that of the high dielectric sheet 520 of Example 2) is preliminarily laminated by a vacuum laminator at a temperature of 50 to 150 ° C and a pressure of 0.5 to 1.5 MPa. The insulating layer 610 (which is the interlayer insulating layer 220 of Fig. 13) is then dried at 150 ° C for 1 hour (see Fig. 15 (b)). The copper foils 622, 626 of the high dielectric foil 620 are all flat coatings that do not form an electrical circuit. Thereafter, etching of the high dielectric sheet 620 is performed by a masking method. In the etching step, a copper chloride etching solution is used. However, after the copper foil 626 and the high dielectric layer 624 are etched, only a small etching process of the copper foil 622 is performed (refer to Fig. 15 (c)). . In Fig. 15(c), a portion of the copper foil 626 is separated by etching into an isolated shaped section 626a (which becomes the forming section 268 of Fig. 13). Then, an interlayer insulating layer (the interlayer insulating layer 245 of FIG. 13, a thermosetting insulating film, ABF-45SH, manufactured by AJINOMOTO Co., Ltd.) 628 is laminated on the high dielectric sheet 620 (Fig. 15 (d)). . Next, a through hole 630 is formed at a specific position of the substrate in which the interlayer insulating layer 628 is laminated, using a carbon dioxide laser, a UV laser, a YAG laser, and an excited molecular laser (see FIG. 15 (e). )). A through hole 630 penetrating the surface of the wiring pattern 32 of the deposition portion 30 is formed through the interlayer insulating layer 628, the high dielectric sheet 620, and the interlayer insulating layer 610. The laser conditions were obtained by using a UV laser manufactured by Hitachi Via Mechanics, Ltd. under the conditions of an output of 3 to 10 kW, a frequency of 30 to 60 kHz, and a stroke number of 54.

After the through hole 630 is formed, the through hole filling resin 640 (the manufacturing step is the same as the through hole filling resin 532 of the second embodiment) is filled in the through hole 630 and dried (see Fig. 16 (a)). Next, through holes 651, 652, and 653 are formed by a carbon dioxide gas laser, a UV laser, a YAG laser, and an excited molecular laser at a specific position of the substrate to be formed (see FIG. 16(b)). The through hole 651 is formed so as to penetrate the surface of the wiring pattern 32 of the through hole filling resin 640 reaching the deposition portion 30, and the through hole 652 is formed to penetrate the surface of the copper foil 626 through the interlayer insulating layer 628, and the through hole 653 is formed. The interlayer insulating layer 628, the high dielectric sheet 620 (the forming section 626a, the high dielectric layer 624, and the copper foil 622), and the interlayer insulating layer 610 are formed to reach the surface of the wiring pattern 32 of the stacking portion 30. . The through holes 651, 652, and 653 are formed by forming the through holes 651 and sequentially forming the through holes 652 and 653. The depth adjustment of the through hole is adjusted by changing the type of laser and the number of laser strokes. For example, the through hole 651 utilizes a CO ₂ laser and is employed With a mask diameter of 1.4 mm, an energy density of 2.0 mj, and a 3-stroke condition, the through-hole 652 is the same as the above-described conditions except for one stroke, and the through-hole 653 utilizes a UV laser and adopts a stroke other than 56 strokes. The conditions are the same as above (output: 3 to 10 W, frequency: 30 to 60 kHz). Further, the through hole 630 is not formed so as to correspond to only all of the power supply connection pads 262 shown in FIG. 13 (that is, corresponding to the power supply connection pad 262y), and the through hole 653 is not Corresponding to all of the grounding connection pads 261 shown in Fig. 13, the corresponding portions (i.e., corresponding to the ground connection pads 261y) are formed.

Thereafter, it was subjected to dry hardening at 170 ° C for 3 hours to completely harden it. Next, the catalyst is attached to the surface of the substrate and subjected to a usual semi-additive method, and the metal is filled into the through holes 651, 652, and 653 to form through holes 262c, 262b, and 261b, and the through holes 262c, 262b, Forming sections 267y, 267x, and 266y are formed on the upper surface of 261b, and wiring 247 for joining the forming section 267x and the forming section 267y is further formed (refer to Fig. 16(c)). The wiring pattern 32 of the deposition portion 30 and the copper foil 626 (the second layered electrode 242) are connected via the wiring 247. Further, the forming section 266x and the wiring 246 of Fig. 14 which are not shown in the drawings are also formed at the same time. Next, the stress relieving sheet 670 (which is the object of the stress relieving portion 250 of Fig. 13 and the manufacturing step is referred to the stress relieving sheet 550 of the second embodiment) is laminated (see Fig. 16 (d)).

Next, a through hole 680 is formed at a position directly above each of the forming sections 267y, 267x, and 266y of the stress relieving sheet 670 (refer to Fig. 17(a)), and roughening, complete hardening, adhesion catalyst, chemical copper, The plating resist, the electroplated copper, the plating resist, and the rapid etching are filled, and the metal is filled in each of the through holes 680 to form a joint pad on the filled metal (see Fig. 17(b)). Therefore, the through hole 262a and the power supply connection pad 262y are formed in the forming section 267y, the through hole 262a and the power supply connection pad 262x are formed in the forming section 267x, and the through hole 261a and the grounding connection pad 261y are formed in the forming section 266y. Further, the through hole 261a and the grounding connection pad 261x (not shown) are formed on the forming section 266x of Figs. 13 and 14 . Thus, the multilayer printed wiring board 210 of Fig. 13 can be obtained. Further, the copper foil 622 corresponds to the first layered electrode 241, the copper foil 626 corresponds to the second layered electrode 242, and the high dielectric layer 624 corresponds to the high dielectric layer 243, and the layered capacitor portion 240 is configured by the above. When the ground connection pad 261x of the third embodiment is connected to the ground connection pad 261y by any layer (for example, the attachment portion 260), the through hole 261a and the molding portion 266x are not required. Similarly, when the electrode connection pad 262x is connected to the electrode connection pad 262y by any layer (for example, the attachment portion 260), the through hole 262a, the molding portion 267x, and the through hole 262b directly under the power supply connection pad 262x are not required. . In this way, the through holes and the forming sections can be reduced.

Thereafter, solder bumps may be formed on the respective terminals of the mounting portion 260 (for the formation method, refer to the first embodiment). Further, as shown in Fig. 13, when the wafer capacitor 273 is mounted, the connection pads 271 and 272 can be formed in the same manner as in the second embodiment.

According to the multilayer printed wiring board 110 of the third embodiment described in detail above, the same effects as those of the above-described first embodiment can be obtained. Further, in the present embodiment, since the layered capacitor portion 240 is not bypassed from the stacking portion 30, the high dielectric sheet 620 is electrically charged from the external power source via the through holes 262c, 262b, and the external power supply can be shortened. The wiring length of the second layered electrode 242 that connects the power supply electrode of the layered capacitor portion 240 and the wiring length of the first layered electrode 241 that connects the ground electrode are used, so that the semiconductor element (IC) that is driven at a high speed is used. When mounted on the mounting portion 260, the layered capacitor portion 240 is less likely to be insufficiently charged. Further, in the present embodiment, the relative area S of the first layered electrode 241 and the second layered electrode 242 is determined such that the electrostatic capacitance C of the layered capacitor portion 240 directly under the module is 0.5 μF, and The relative area S determines the number and position of the through holes 241a of the first layered electrode 241 and the number and positions of the through holes 242a and 242b of the second layered electrode 242. Here, the relative area S is calculated by C = ε ₀ ‧ ε _r ‧ d / S. That is, since the relative dielectric constant ε _r of the high dielectric layer 242 is 1850 and the thickness d is 1.2 μm, the value is substituted into the above equation, and the electrostatic capacitance C is substituted at 0.5 μF to calculate the relative area S. Further, ε ₀ is a dielectric constant (fixed number) at the time of vacuum.

Further, in the above manufacturing step, the lamination of the interlayer insulating layer 628 is performed after the step of FIG. 15(c) (see FIG. 15(d)), and the through hole 630 is formed at a specific position of the interlayer insulating layer 628. (see Fig. 15(e)), after the through hole 650 is filled with the resin 640 and dried (see Fig. 16(a)), the through hole 651 is formed in the through hole filling resin 640 ( Referring to Fig. 16(b)), however, the method shown below can also be employed. That is, after the step of FIG. 15(c), the dry film of the marketer is attached to the surface of the substrate, and then the dielectric material is formed by the masking method to form the via hole 262c (refer to FIG. 16(c)). The thin film 620 is etched away to form an enlarged hole 632 larger than the through hole 262c (refer to Fig. 18(a)), and thereafter, the interlayer insulating layer 628 is laminated on the high dielectric sheet 620, and the etching layer is removed by etching. The formed enlarged hole 632 is filled with the interlayer insulating layer 628 and then dried (Fig. 18(b)). Next, the steps after the steps for forming the through holes 651, 652, and 653 of the third embodiment can be carried out thereafter. Therefore, the step of filling the through hole 630 can be deleted.

[Example 4]

The through hole 530 and the through hole 531 of the second embodiment are formed at positions corresponding to all of the power supply connection pads and the ground connection pads. As a result, the electrostatic capacitance of the layered capacitor portion was 0.4 μF.

[Example 5]

The through hole 630 and the through hole 653 of the third embodiment are formed at positions corresponding to all of the power supply connection pads and the ground connection pads. As a result, the electrostatic capacitance of the layered capacitor portion was 0.4 μF.

[Embodiment 6]

The number of repetitions of spin coating/drying/firing in the production step (4) of the high dielectric sheet of Example 2 was changed to 20 times to obtain a high dielectric layer of 0.6 μm. The rest is the same as in Embodiment 2. As a result, the electrostatic capacitance of the layered capacitor portion directly under the module was 1.0 μF.

[Embodiment 7]

The number of repetitions of spin coating/drying/firing in the production step (4) of the high dielectric sheet of Example 3 was changed to 20 times to obtain a high dielectric layer of 0.6 μm. The rest is the same as in the third embodiment. As a result, the electrostatic capacitance of the layered capacitor portion directly under the module was 1.0 μF.

[Embodiment 8]

The number of repetitions of spin coating/drying/firing in the production step (4) of the high dielectric sheet of Example 2 was changed to one time to obtain a high dielectric layer of 0.03 μm. The rest is the same as in Embodiment 2. As a result, the electrostatic capacitance of the layered capacitor portion directly under the module was 20 μF.

[Embodiment 9]

The number of repetitions of spin coating/drying/firing in the production step (4) of the high dielectric sheet of Example 3 was changed to one time to obtain a high dielectric layer of 0.03 μm. The rest is the same as in the third embodiment. As a result, the electrostatic capacitance of the layered capacitor portion directly under the module was 20 μF.

[Embodiment 10]

The number of repetitions of spin coating/drying/firing in the production step (4) of the high dielectric sheet of Example 2 was changed to four times to obtain a high dielectric layer of 0.12 μm. The rest is the same as in Embodiment 2. As a result, the electrostatic capacitance of the layered capacitor portion directly under the module was 5 μF.

[Example 11]

The number of repetitions of spin coating/drying/firing in the production step (4) of the high dielectric sheet of Example 3 was changed to four times to obtain a high dielectric layer of 0.12 μm. The rest is the same as in the third embodiment. As a result, the electrostatic capacitance of the layered capacitor portion directly under the module was 5 μF.

[Embodiment 12]

The number of repetitions of spin coating/drying/firing in the production step (4) of the high dielectric sheet of Example 2 was changed to two times to obtain a high dielectric layer of 0.06 μm. The rest is the same as in Embodiment 2. As a result, the electrostatic capacitance directly under the module becomes 10 μF.

[Example 13]

The number of repetitions of spin coating/drying/firing in the production step (4) of the high dielectric sheet of Example 3 was changed to two times to obtain a high dielectric layer of 0.06 μm. The rest is the same as in the third embodiment. As a result, the electrostatic capacitance directly under the module becomes 10 μF.

[Embodiment 14]

The through hole 530 and the through hole 531 of the eighth embodiment are formed at positions corresponding to all of the power supply connection pads and the ground connection pads. As a result, the electrostatic capacitance was 16 μF.

[Example 15]

The through hole 630 and the through hole 653 of the ninth embodiment are formed at positions corresponding to all of the power supply connection pads and the ground connection pads. As a result, the electrostatic capacitance was 16 μF.

[Example 16]

The number of repetitions of spin coating/drying/firing in the production step (4) of the high dielectric sheet of Example 2 was changed to 330 times to obtain a high dielectric layer of 10 μm. The rest is the same as in Embodiment 2. As a result, the electrostatic capacitance directly under the module becomes 0.06 μF.

[Example 17]

The number of repetitions of spin coating/drying/firing in the production step (4) of the high dielectric sheet of Example 3 was changed to 330 times to obtain a high dielectric layer of 10 μm. The rest is the same as in the third embodiment. As a result, the electrostatic capacitance directly under the module becomes 0.06 μF.

[Embodiment 18]

The number of repetitions of spin coating/drying/firing in the production step (4) of the high dielectric sheet of Example 2 was changed to 10 times to obtain a high dielectric layer of 0.3 μm. The rest is the same as in Embodiment 2. As a result, the electrostatic capacitance directly under the module becomes 2.0 μF.

[Embodiment 19]

The number of repetitions of spin coating/drying/firing in the production step (4) of the high dielectric sheet of Example 3 was changed to 10 times to obtain a high dielectric layer of 0.3 μm. The rest is the same as in the third embodiment. As a result, the electrostatic capacitance directly under the module becomes 2.0 μF.

[Example 20]

The number of repetitions of spin coating/drying/firing in the production step (4) of the high dielectric sheet of Example 2 was changed to 25 times to obtain a high dielectric layer of 0.75 μm. The rest is the same as in Embodiment 2. As a result, the electrostatic capacitance directly under the module becomes 0.8 μF.

[Example 21]

The number of repetitions of spin coating/drying/firing in the production step (4) of the high dielectric sheet of Example 3 was changed to 25 times to obtain a high dielectric layer of 0.75 μm. The rest is the same as in the third embodiment. As a result, the electrostatic capacitance directly under the module becomes 0.8 μF.

[Example 22]

The high dielectric sheet of Example 3 was etched in advance to remove portions of the copper foil 626 and the high dielectric layer 624. Thereafter, the high dielectric sheet is attached to the substrate 600 on which the deposition portion 30 is formed by the interlayer insulating layer 610. That is, the high dielectric sheet attaching step of Embodiment 3 and the etching step of the high dielectric sheet are replaced. The subsequent steps are the same as in the third embodiment.

[Example 23]

The wafer capacitor was mounted on the multilayer printed wiring board of Example 4.

[Example 24]

The wafer capacitor was mounted on the multilayer printed wiring board of Example 5.

[Example 25]

The stress relieving portion 150 of the second embodiment is replaced with an interlayer insulating layer 510 (see Fig. 9(a)). The rest is the same as in Embodiment 2.

[Example 26]

The stress relaxation portion 250 of the third embodiment is replaced with an interlayer insulating layer 610 (see Fig. 15 (a)). The rest is the same as in the third embodiment.

[Examples 27 to 49]

In Examples 27 to 49, a multilayer printed wiring board was produced by replacing the stress relieving portions of Examples 2 to 24 with an interlayer insulating layer.

[Comparative example]

The high dielectric sheet of the comparative example was produced by the other production steps of the high dielectric sheet described in Example 2. However, the electrode was not formed on the unfired layer after drying without firing. The rest is the same as in Embodiment 2. As a result, the static capacitance directly under the module is 0.001 μF or less.

Evaluation test 1

In the multilayer printed wiring boards of the second to fourth and fourth comparative examples, an IC chip having a driving frequency of 3.6 GHz and an FSB of 1066 MHz was mounted, and switching was repeated 100 times, using Pulse Pattern Generator/Error Detector (product name: D3186, manufactured by ADVANTEST Co., Ltd.). /3286), confirm whether there is any wrong action.

[Evaluation Test 2, HAST Test]

A voltage of 3.3 V was applied between the first layered electrode and the second layered electrode of the multilayer printed wiring boards of Examples 2 to 49, and placed in an environmental tester at 85 ° C X 85% for 50 hours. In the meantime, discharge was performed every 2 hours. Thereafter, an IC chip having a drive frequency of 3.6 GHz and an FSB of 1066 MHz was mounted, and switching was repeated 100 times at the same time, and the pulse pattern generator/Error Detector was used to confirm the presence or absence of an erroneous operation.

[Evaluation Test 3, HAST Test]

In the same manner as in Evaluation Test 2, a voltage of 3.3 V was applied between the first layered electrode and the second layered electrode of the multilayer printed wiring board after the evaluation test 2 was completed, and placed at 85 ° C X 85% of the environmental testing machine. Within 50 hours. In the meantime, discharge was performed every 2 hours. Then, an IC chip having a drive frequency of 3.6 GHz and an FSB of 1066 MHz was mounted, and switching was repeated 100 times at the same time, and the presence or absence of an erroneous operation was confirmed by the Pulse Pattern Generator/Error Detector.

[Evaluation Test 4, Thermal Cycle Test]

The following thermal cycle tests were carried out on the multilayer printed wiring boards of Examples 2 to 26.

Thermal cycle test conditions: 100 times or 500 times - 55 ° C X 30 minutes, 125 ° C X 30 minutes, install the IC chip with a drive frequency of 3.6 GHz and FSB 1066 MHz, and repeat the switch switching 100 times, using the aforementioned Pulse Pattern Generator / Error Detector to confirm the presence or absence of an error action.

[Evaluation Test 5]

An IC wafer having a driving frequency of 5.7 GHz and FSB 1066 MHz was mounted instead of the IC chip of the test frequency of 3.6 GHz and FSB 1066 MHz, and the same test as the evaluation test 1 was carried out. As a result, the multilayer printed wiring board having a static capacitance of 1.0 μF or more directly under the module does not malfunction.

[evaluation result]

Table 1 shows the results of evaluation tests 1 to 4. When no error is observed, it is ○, and when an error is observed, it is ×. Further, Table 1 does not disclose the electrostatic capacitances directly under the modules of Examples 27 to 49 and the evaluation results of Evaluation Tests 1 to 3. However, the results were the same as in Examples 2 to 24, respectively.

As a result of the evaluation test 1, it is understood that, in addition to the deposition portion, the ceramic is formed by firing of a high dielectric material and used as a high dielectric layer, and has a high dielectric constant, and as a result, the potential can be suppressed. Reduced instantly.

Further, as a result of the evaluation test 4, it was found that the comparative example could not instantaneously lower the potential of the IC wafer after 100 cycles. Although the reason is unknown, however, it is estimated that the bonding between the high dielectric particles is weak, so that cracks are generated therefrom, and the function of the capacitor is lost.

Further, the thermal cycle test was carried out on the example 22 of the high dielectric sheet forming circuit before being attached to the stacking portion, and the potential of the IC chip could not be instantaneously lowered. Although the reason is not clear, it is estimated that the pressure concentration portion at the time of lamination may be cracked due to the heat cycle test.

Further, in the examples 25 and 26 in which the stress relieving portion was not provided, the thermal cycle test was carried out, and the potential of the IC chip could not be instantaneously lowered. Although the reason is unknown, however, it is estimated that there is no stress relaxation portion, and the stress caused by the difference in thermal expansion coefficient between the IC chip and the multilayer printed wiring board may cause cracking or cracking of the high dielectric layer. starting point. Since the starting point of cracking occurs due to the heat cycle test, at the time of the simultaneous switching test, since the high dielectric layer is repeatedly charged and discharged, the particle displacement at this time may cause cracking.

Further, in the case of the fourth and fifth embodiments in which the electrostatic capacitance immediately below the module was 0.4 μF or less, after the evaluation test 2 was performed, the potential of the IC chip could not be instantaneously lowered. Although the reason is unknown, it is estimated that the HAST test may cause deterioration of the high dielectric layer, and the relative dielectric constant may be lowered to obtain a sufficient decoupling effect. In addition, when the electrostatic capacitance immediately below the module is 0.5 μF or less, after the evaluation test 2 is performed, the potential of the IC chip cannot be instantaneously lowered. On the other hand, the electrostatic capacitance directly under the module is the same as that of the fourth and fifth embodiments. Embodiments 23 and 24 do not cause problems. Although the reason for this is unknown, it is estimated that the potential of the IC chip can be instantaneously lowered by performing power supply using the wafer capacitor. Further, after performing the evaluation test 2 on the embodiments 14 and 15 in which the electrostatic capacitance is large, the potential of the IC chip cannot be instantaneously lowered. Although the reason is unknown, however, it is estimated that the high dielectric layer may be affected by the HAST test because of the large electrostatic capacitance, so that the high dielectric layer is deteriorated in insulation or dielectric breakdown.

In Examples 12 to 15 in which the electrostatic capacitance was large, the result of the evaluation test 4 ^*3 was ×. It is inferred that the dielectric displacement occurs during repeated charging and discharging of the dielectric, and the stress accumulated during thermal cycling is added to the stress caused by the displacement, so that the relative dielectric constant of the high dielectric layer is degraded. ×. Further, the evaluation test 4 ^{*3 of} Examples 2 to 5, 16, and 17 in which the electrostatic capacitance was relatively small was also ×. It is inferred that the thermal cycle test causes the dielectric to expand and contract, so that the relative dielectric constant of the high dielectric layer is degraded, and the electrostatic capacitance immediately below the module is reduced to become ×.

It can be seen from the results of Table 1 that if the static capacitance directly under the module is 0.8 to 5 μF, the instantaneous voltage of the transistor corresponding to the IC can be lowered after the environmental test, and no problem occurs after the HAST test and the thermal cycle test. Therefore, it has excellent insulation reliability and connection reliability.

Further, in all of the embodiments, the first layered electrode is used as the ground and the second layered electrode is used as the power source. However, the reverse may be applied.

The multilayer printed wiring board of the present invention can be used for mounting a semiconductor element such as an IC chip, and can be applied to, for example, an electric related industry and a communication-related industry.

10. . . Multilayer printed wiring board

20. . . Core substrate

twenty one. . . Core substrate body

twenty two. . . Wiring pattern

twenty four. . . Through-hole conductor

30. . . Stacking department

32. . . Wiring pattern

34. . . Through hole

36. . . Resin insulation

40. . . Layered capacitor

41. . . First layer electrode

41a. . . Through hole

42. . . Second layer electrode

42a. . . Through hole

43. . . High dielectric layer

60. . . Installation department

61. . . Grounding connection pad

61a. . . Through hole

62a. . . Through hole

62b. . . Through hole

62. . . Power connection pad

63. . . Signal connection pad

70. . . Wafer capacitor configuration area

71. . . Grounding connection pad

72. . . Power connection pad

73. . . Wafer capacitor

110. . . Multilayer printed wiring board

120. . . Interlayer insulation

140. . . Layered capacitor

141. . . First layer electrode

141a. . . Through hole

142. . . Second layer electrode

142a. . . Through hole

143. . . High dielectric layer

150. . . Stress relief

160. . . Installation department

161. . . Grounding connection pad

161a. . . Through hole

162a. . . Through hole

162b. . . Through hole

162. . . Power connection pad

163. . . Signal connection pad

170. . . Wafer capacitor configuration area

171. . . Grounding connection pad

172. . . Power connection pad

173. . . Wafer capacitor

210. . . Multilayer printed wiring board

220. . . Interlayer insulation

240. . . Layered capacitor

241. . . First layer electrode

241a. . . Through hole

242. . . Second layer electrode

242a. . . Through hole

242b. . . Through hole

243. . . High dielectric layer

245. . . Interlayer insulation

246. . . Wiring

247. . . Wiring

250. . . Stress relief

260. . . Installation department

261. . . Grounding connection pad

261x. . . Grounding connection pad

261y. . . Grounding connection pad

261a. . . Through hole

261b. . . Through hole

262a. . . Through hole

262b. . . Through hole

262c. . . Through hole

262. . . Power connection pad

262x. . . Power connection pad

262y. . . Power connection pad

263. . . Signal connection pad

266x. . . Forming section

266y. . . Forming section

267x. . . Forming section

267y. . . Forming section

268. . . Forming section

270. . . Wafer capacitor configuration area

271. . . Grounding connection pad

272. . . Power connection pad

273. . . Wafer capacitor

410. . . Interlayer insulation

420. . . High dielectric sheet

422. . . Copper foil

424. . . High dielectric layer

426. . . Upper metal layer

430. . . Dry film

440. . . Dry film

450. . . Interlayer filling resin

452. . . High dielectric interlayer filling layer

454. . . Through hole

456. . . Electroless copper plating

460. . . Dry film

462. . . Through hole

464. . . Electrolytic copper plating

470. . . Resin insulating sheet

472. . . Through hole

474. . . Copper plating film

500. . . Substrate

510. . . Interlayer insulation

520. . . High dielectric sheet

522. . . Copper foil

524. . . High dielectric layer

526. . . Copper foil

530. . . Through hole

530a. . . Through hole

531. . . Through hole

531a. . . Through hole

532. . . Through hole filling resin

540. . . Electroless copper plating

541. . . Anti-plating

542. . . Electrolytic copper plating

543. . . Upper electrode

544. . . Forming section

550. . . Stress relief sheet

560. . . Through hole

562. . . conductor

600. . . Substrate

610. . . Interlayer insulation

620. . . High dielectric sheet

622. . . Copper foil

624. . . High dielectric layer

626a. . . Forming section

626. . . Copper foil

628. . . Interlayer insulation

630. . . Through hole

632. . . Enlarge hole

640. . . Through hole filling resin

651. . . Through hole

652. . . Through hole

653. . . Through hole

670. . . Stress relief sheet

680. . . Through hole

Fig. 1 is a plan view showing a multilayer printed wiring board 10 of the first embodiment.

Fig. 2 is a longitudinal sectional view of the multilayer printed wiring board 10 (only the left side of the center line is shown).

Fig. 3 is a schematic perspective view of the layered capacitor portion 40.

Fig. 4 is an explanatory view showing a manufacturing procedure of the multilayer printed wiring board 10.

Fig. 5 is an explanatory view showing a manufacturing procedure of the multilayer printed wiring board 10.

Fig. 6 is an explanatory view showing a manufacturing procedure of the multilayer printed wiring board 10.

Fig. 7 is an explanatory view showing a manufacturing procedure of the multilayer printed wiring board 10.

Fig. 8 is a longitudinal sectional view showing a multilayer printed wiring board 110 of the second embodiment.

Fig. 9 is an explanatory view showing a manufacturing procedure of the multilayer printed wiring board 110.

Fig. 10 is an explanatory view showing a manufacturing procedure of the multilayer printed wiring board 110.

Fig. 11 is an explanatory view showing a manufacturing procedure of the multilayer printed wiring board 110.

Fig. 12 is an explanatory view of a high dielectric sheet 520 having corners.

Fig. 13 is a longitudinal sectional view showing a multilayer printed wiring board 210 of the third embodiment.

Fig. 14 is a schematic perspective view of the layered capacitor portion 240.

Fig. 15 is an explanatory view showing a manufacturing procedure of the multilayer printed wiring board 210.

Fig. 16 is an explanatory view showing a manufacturing procedure of the multilayer printed wiring board 210.

Fig. 17 is an explanatory view showing a manufacturing procedure of the multilayer printed wiring board 210.

Fig. 18 is an explanatory view showing the manufacturing steps of the other multilayer printed wiring board 210.

71. . . Grounding connection pad

73. . . Wafer capacitor

72. . . Power connection pad

70. . . Wafer capacitor configuration area

63. . . Signal connection pad

42a. . . Through hole

61. . . Grounding connection pad

61a. . . Through hole

50. . . Stress relief

62. . . Power connection pad

60. . . Installation department

62a. . . Through hole

10. . . Multilayer printed wiring board

42. . . Second layer electrode

43. . . High dielectric layer

41. . . First layer electrode

40. . . Layered capacitor

34. . . Through hole

32. . . Wiring pattern

36. . . Resin insulation

30. . . Stacking department

twenty two. . . Wiring pattern

twenty four. . . Through-hole conductor

twenty one. . . Core substrate body

20. . . Core substrate

twenty two. . . Wiring pattern

Claims (3)

A method of manufacturing a multilayer printed wiring board for manufacturing a multilayer wiring board including a deposition portion, a mounting portion, and a layered capacitor portion; the deposition portion is partitioned by a through hole in the insulating layer The wiring pattern in which the resin insulating layer is formed in a plurality of layers is electrically connected to each other, and is configured such that the mounting portion is mounted on the surface of the semiconductor element electrically connected to the wiring pattern; and the layered capacitor portion is a high dielectric layer made of ceramic and a first and second layered electrode sandwiching the high dielectric layer between the deposition portion and the mounting portion, the first and second layers One of the electrodes is connected to the power supply line of the semiconductor element and the other is connected to the ground line; and the method includes forming a thin film of a high dielectric material on the metal foil as the first layered electrode, and firing the film a high dielectric material to form the high dielectric layer, and a high dielectric layer is formed on the high dielectric layer by forming a metal layer as the second layer electrode; of Engineering the substrate heart; the high-dielectric layer system with the bulk part of a firing opening, on said stacking portion engaging the high dielectric sheet of engineering. A method of manufacturing a multilayer printed wiring board for manufacturing a multilayer wiring board including a deposition portion, a mounting portion, and a layered capacitor portion; the deposition portion is partitioned by a through hole in the insulating layer The resin insulating layer is electrically connected to the wiring pattern of the plurality of layers, so that Forming on both sides of the core substrate; the mounting portion is mounted on the surface of the semiconductor element electrically connected to the wiring pattern; and the layered capacitor portion is provided between the stacking portion and the mounting portion a high dielectric layer made of ceramic and a first and second layered electrode sandwiching the high dielectric layer, wherein one of the first and second layered electrodes is connected to a power supply line of the semiconductor element and One of the wires is connected to the grounding wire, and is characterized in that: a thin film of a high dielectric material is formed on the metal foil as the first layered electrode, and the high dielectric layer is formed by firing the high dielectric material. A process of obtaining a high dielectric sheet on the high dielectric layer by forming a metal layer as the second layered electrode; preparing a core substrate on which the deposition portion is formed on both sides; the high dielectric material The layer is fired in the deposition portion, and the high dielectric sheet is bonded to the surface on the opposite side of the core substrate in the deposition portion. The method for producing a multilayer printed wiring board according to claim 1 or 2, wherein the high dielectric material contains barium titanate (BaTiO ₃ ), barium titanate (SrTiO ₃ ), or cerium oxide ( TaO ₃ , Ta ₂ O ₃ ), lead zirconate titanate (PZT), lead zirconate titanate (PLZT), lead zirconate titanate (PNZT), lead zirconate titanate (PCZT), and lead zirconate titanate (PSZT) A raw material of one or more metal oxides selected from the group consisting of (PSZT).