TW201116186A - Multi-layer printed circuit board - Google Patents

Abstract

Multi-layer printed circuit board (10) has: a mounting part (60) for installing a semiconductor device electrically connected to a wiring pattern (32) on a surface; and a ceramic high dielectric layer (43) and a first and second layered electrode (41,42) sandwiching the high dielectric layer (43). One side of the first and second layered electrodes (41,42) is linked to a power line of the semiconductor device and the other side is linked to layered capacitor part (40) of grounding wire. In the multi-layer printed circuit board (10), since the high dielectric layer (43) of the layered capacitor part (40) is linked between the power line and the grounding wire is ceramic, the layered capacitor part (40) has a larger static capacitance. Therefore, even under the condition that a sudden drop of electrical potential happens easily, adequate decoupling effect can still be obtained.

Description

[Technical Field] The present invention relates to a multilayer printed wiring board having an electrical connection portion formed by a wiring pattern in which a plurality of wiring layers are formed by using a via insulating layer in an insulating layer. [Prior Art] Φ Conventionally, a layer printed wiring board having a wiring pattern in which a plurality of laminated wiring layers are electrically connected by through holes in an insulating layer has various structures. For example, when such a wiring board is turned on and off by a semiconductor device mounted at a high speed, switching noise is generated, and the potential of the power supply line is instantaneously lowered, and the potential of the potential is lowered. It is proposed to perform decoupling at the power supply line and the grounded capacitor portion. The method. In the capacitor portion 200 1 - 68 8 5 8 , the layered capacitor portion is provided in the wiring board. SUMMARY OF THE INVENTION However, in the layered capacitor portion of the above-mentioned publication, a dielectric layer composed of an organic resin such as ruthenium or the like is used, and a large electrostatic capacitance is used, and the semiconductor element is easily turned off by GHz to several tens of GHz. The situation in which the high potential is instantaneously reduced is a problem of fully decoupling effects. In view of the above, it is an object of the present invention to provide a multi-layer printing which can be used to form a solid portion of a stacked insulating layer, and to prevent the connection between the wires. Multilayer printing is a multilayer printed wiring board that does not have enough frequency to appear in the presence of titanic acid, so it is difficult to fully decouple the -5-201116186 effect. In order to achieve at least a part of the above objects, the present invention employs the following means. The present invention has a multilayer printed wiring board in which a deposition portion formed by electrically connecting a wiring pattern in which a plurality of layers are laminated via the insulating layer is formed by a via hole in an insulating layer, and has a surface mounted with the wiring The pattern forming the mounting portion of the electrically coupled semiconductor element; between the mounting portion and the stacking portion, having a ceramic high dielectric layer and first and second layers sandwiching the high dielectric layer In the electrode, one of the first and second layered electrodes is connected to the power supply line of the semiconductor element, and the other is connected to the layered capacitor portion of the ground line. Since the multilayer printed wiring board is made of a high dielectric layer ceramic which is connected to the layered capacitor portion between the power supply line and the ground line, the dielectric constant is higher than that of the conventional organic resin-containing organic resin. Therefore, the static capacitance of the layered capacitor portion is large. Therefore, even if the frequency at which the semiconductor element is turned on and off is liable to be instantaneously lowered at a high potential of several GHz to several tens of GHz (e.g., 3 GHz to 20 GHz), a sufficient decoupling effect can be exhibited. The high dielectric layer of the multilayer printed wiring board of the present invention is formed by bonding an object produced by firing the high dielectric material to the deposited portion. In general, since the deposition portion is formed at a temperature of 200 ° C or lower, it is difficult to form the ceramic by firing of a high dielectric material, so that the high dielectric material should be fired with the deposited portion. Forming ceramics. Such a high dielectric layer is not particularly limited and may be, for example, from -6 to 201116186, such as barium titanate (BaTi03), barium titanate (SrTi03), oxidized giant (Ta03 'Ta205), lead zirconate titanate ( One selected from the group consisting of PZT), lead zirconate titanate (PLZT), lead zirconate titanate (PNZT), lead calcium titanate (PCZT), and lead zirconate titanate (PSZT) or A multilayer printed wiring board of the present invention may be produced by firing a raw material of two or more kinds of metal oxides, that is, a lower surface side of the high dielectric layer of the first layered electrode, a flat coating pattern having a through hole through which the rod-shaped terminal connected to the second layered electrode passes in a non-contact state is disposed, and the upper surface side of the high dielectric layer of the second layered electrode is disposed A flat coating pattern having a through hole through which the rod-shaped terminal connected to the first layered electrode can pass in a non-contact state is provided. Thus, the first and second layered electrodes of the layered capacitor portion can have a large area, so that the layered capacitor portion can have a large electrostatic capacitance. Further, not only can the charge of the layered capacitor portion be charged from the external power source with a shorter wiring length, but the power supply can be supplied from the layered capacitor portion to the semiconductor φ element with a shorter wiring length, so that the interval between the conduction and the disconnection is shorter. In the case of a semiconductor component of several GHz to several tens of GHz (for example, 3 GHz to 20 GHz), a sufficient decoupling effect can be obtained, and a power shortage is unlikely to occur. In addition, each of the flat patterns may be disposed on one of the upper or lower portions of the high dielectric layer, or may be provided in a comprehensive manner. The printed wiring board of the present invention may have a configuration in which the mounting portion has a plurality of connection pads connected to the electrodes of the semiconductor element, and is electrically connected to a connection pad having the same potential as the first layer electrode. Further, the number of the rod-shaped terminals through which the second layered electrode passes in a non-contact state is less than the number of the connection pads of the same potential as the first layered electrode of 201116186. In this manner, since the rod-shaped terminal connected to the connection pad having the same potential as the first layered electrode has a small number of passage holes through which the second layered electrode passes in a non-contact state, the second layer can be formed. Since the electrode has a large area, the layered capacitor portion can have a large electrostatic capacitance. The printed wiring board of the present invention may have a configuration in which the mounting portion has a plurality of connection pads connected to the electrodes of the semiconductor element, and is electrically connected to a connection pad having the same potential as the second layer electrode. Further, the number of the rod-shaped terminals that pass the first layered electrode in a non-contact state is smaller than the number of the connection pads that have the same potential as the second layered electrode. In this manner, since the rod-shaped terminal connected to the connection pad having the same potential as the second layered electrode has a small number of passage holes through which the first layered electrode passes in a non-contact state, the first layer can be formed. Since the electrode has a large area, the layered capacitor portion can have a large electrostatic capacitance. In this case, the rod-shaped terminals connected to the connection pads of the same potential as the second layered electrodes may be such that the first layered electrode and the second layered electrode are both in a non-contact state. Further, the two types of rod-shaped terminals (that is, the rod-shaped terminals electrically connected to the connection pads of the same potential as the first layered electrodes and passing the second layered electrodes in a non-contact state, and the electrical connection At least a portion of the rod-shaped terminal that is connected to the second layered electrode at the same potential and that allows the first layered electrode to pass in a non-contact state may be alternately arranged in a lattice shape or a cross shape. Thus, since the loop inductance is low, it is easier to prevent the instantaneous drop of the power supply potential. The multilayer printed wiring board of the present invention may be configured as follows, that is, -8 - 201116186, wherein the mounting portion has a first connection pad connected to one of a power supply electrode and a ground electrode of the semiconductor element, and is connected to In the other second connection pad, one of the first connection pads has a first rod terminal through which the second layer electrode passes in a non-contact state, and is electrically connected to the first rod terminal via the first rod terminal. The electrode of one of the first layered electrode and the external power source does not have the first rod-shaped terminal, and is electrically connected to the first connection pad having the first rod-shaped terminal, and the second connection pad One of φ has a second rod-shaped terminal through which the first layered electrode passes in a non-contact state, and is electrically connected to the second layered electrode and the external electrode via the second rod-shaped terminal The other electrode itself does not have the second rod-shaped terminal and is electrically connected to the second connection pad having the second rod-shaped terminal. In this way, since the number of the first rod-shaped terminal and the second rod-shaped terminal can be reduced, the number of the through-holes through which the first layered electrode and the second layered electrode can pass can be reduced. The first and second layered electrodes have a large area, and the layered capacitor portion has a large electrostatic capacitance. For example, φ, the first and second layered electrodes may be substantially flat-coated. Further, not only can the charge of the layered capacitor portion be charged from the external power source with a shorter wiring length, but also the power supply can be supplied to the semiconductor element from the layered capacitor portion with a shorter wiring length, so that the interval between the on and off is shorter. In the case of a semiconductor component of GHz to tens of GHz (for example, 3 GHz to 20 GHz), a sufficient decoupling effect can be obtained, and a power shortage is unlikely to occur. The multilayer printed wiring board of the present invention may have a configuration in which the mounting portion has a first connection pad connected to one of a power supply electrode and a ground electrode of the semiconductor element, and a second connection connected to the other of the semiconductor element -9- 201116186 Pad One of the first connection pads has a first rod terminal through which the second layer electrode passes in a non-contact state, and is electrically connected to the first via the first rod terminal The electrode of one of the layered electrode and the external power source does not have the first rod-shaped terminal, and is electrically connected to the first connection pad having the first rod-shaped terminal, and one of the second connection pads a part of the electrode having the second rod-shaped terminal that passes through the first layered electrode and the second layered electrode in a non-contact state, and is connected to the other external power source via the second rod-shaped terminal. The remaining portion itself does not have the second rod-shaped terminal, and is electrically connected to at least one of the second layered electrode and the second connection pad having the second rod-shaped terminal. In this case, since the number of the first rod-shaped terminal and the second rod-shaped terminal can be reduced, the number of the through-holes through which the first layered electrode and the second layered electrode pass can be reduced. The first and second layered electrodes can have a large area, and the layered capacitor portion can have a large electrostatic capacitance. For example, the first and second layered electrodes can be made substantially flat. Further, not only can the charge of the layered capacitor portion be charged from the external power source with a shorter wiring length, but also the power supply can be supplied to the semiconductor element from the layered capacitor portion with a shorter wiring length, so that the interval between the on and off is shorter. In the case of a semiconductor component of GHz to several tens of GHz (for example, 3 GHz to 20 GHz), a sufficient decoupling effect can be obtained, and a power shortage is unlikely to occur. At least a part of the first rod-shaped terminal and the second rod-shaped terminal of the multilayer printed wiring board having the first rod-shaped terminal and the second rod-shaped terminal may be alternately arranged in a lattice shape or a cross shape. Thus, since the loop inductance is low, it is easier to prevent an instantaneous drop in the power supply potential. -10- 201116186 The configuration of the multilayer printed wiring board of the present invention may be as follows, that is, the layered capacitor portion has a distance between the first and second layered electrodes of 10/zm or less. The distance from the short circuit will occur. Thus, since the distance between the electrodes of the layered capacitor portion is extremely small, the layered capacitor portion has a large electrostatic capacitance. The layered capacitor portion of the multilayer printed wiring board of the present invention should be formed directly under the semiconductor element mounted on the mounting portion. In this way, the power supply can be supplied to the semiconductor element with the shortest wiring length of φ. The multilayer printed wiring board of the present invention may have a chip capacitor which is provided on the surface of the mounting portion and which is connected to the first and second layered electrodes of the layered capacitor portion. Thus, when the electrostatic capacitance is insufficient due to only the layered capacitor portion, the wafer capacitor can be used to supplement the insufficient portion. In addition, the decoupling effect is lower because the wiring of the wafer capacitor and the semiconductor element is longer. However, since the wafer capacitor is provided on the surface side where the mounting portion is disposed, the wiring of the semiconductor element is shortened, so that the solution φ can be suppressed. The coupling effect is reduced. Further, since the wafer capacitor and the semiconductor element are connected via the layered capacitor portion, the loss of power supply to the semiconductor element by the wafer capacitor can be reduced. The mounting portion of the multilayer printed wiring board of the present invention and the layered capacitor portion may have a stress relieving portion formed of an elastic material. In this manner, even if a stress is generated due to a difference in thermal expansion between the semiconductor element mounted on the mounting portion and the layered capacitor portion or the deposition portion, the stress relieving portion absorbs the stress, so that the connection reliability is lowered and the insulation reliability is less likely to occur. problem. In addition, because the high dielectric layer of the layered capacitor portion is thinner and thinner

S -11 - 201116186 is brittle, so it is prone to cracking. However, because it has a stress relieving part, cracking can be prevented. In this case, the stress relieving portion may be formed only under the semiconductor element mounted on the mounting portion. The stress caused by the difference in thermal expansion caused by the problem is mainly located directly under the semiconductor element. If the stress relaxation portion is formed only in this portion, the material cost can be reduced. The material of the stress relaxation portion is not particularly limited, and for example, a recombinant epoxy resin sheet, a polyphenylene ether resin sheet, a polyimide film, a cyano ester resin sheet, and a sulfonamide resin can be used. An organic resin sheet such as a sheet. The organic resin sheet may contain a polyolefin resin of a thermoplastic resin, a polyimide resin, a thermosetting resin, a resin, a rubber resin such as SBR, NBR or urethane, or may contain a dispersion. Inorganic fibrous, tantalum, or flat material such as helium oxygen, aluminum oxide, or cone oxygen. Further, the Young's modulus of the stress relaxation portion should be 10 to 100 MPa. When the Young's modulus of the stress relaxation portion is in the above range, the stress is generated when a stress is generated between the semiconductor element and the layered capacitor portion mounted on the mounting portion due to a difference in thermal expansion coefficient. [Embodiment] [Embodiment 1] Next, an embodiment of the present invention will be described with reference to the drawings. 1 is a plan view of a multilayer printed wiring board 10 according to an embodiment of the present invention, and FIG. 2 is a longitudinal sectional view of the multilayer printed wiring board 1 (only the left side of the center line is shown). A schematic perspective view of the capacitor portion 40. As shown in FIG. 2, the multilayer printed wiring board 10 of the present embodiment has a core substrate 20' on which the wiring pattern 2 2 formed on the front and back sides is electrically connected via a through hole -12-201116186. The upper via hole 34 is electrically connected to the deposition portion 30 in which the plurality of wiring patterns 32 and 22 are laminated via the resin insulating layer 36, and the high dielectric layer 43 and the high dielectric layer 43 are interposed therebetween. The layered capacitor portion 40 composed of the first and second layered electrodes 41 and 42 , the stress relieving portion 50 formed of an elastic material, the mounting portion 60 for mounting the semiconductor element, and the wafer disposed around the mounting portion 60 Capacitor configuration area 70. The core substrate 20 has wiring patterns 22 and 22 made of copper formed on the front and back surfaces of the core substrate main body 21 made of BT (Bismaleimide-Triazine) resin or glass epoxy substrate, and formed on the through core substrate. The through-hole conductors 24 made of copper on the inner side surface of the through-holes on the front and back sides of the main body 2 are electrically connected via the via-hole conductors 24. In the stacking portion 30, the resin insulating layer 36 and the wiring pattern 32 are alternately laminated on the front and back surfaces of the core substrate 20, and the wiring patterns 32 are electrically connected via the through holes 34 penetrating the front and back sides of the resin insulating layer 36. Such a stacking portion 3 is formed by a well-known elimination method or addition method (including a semi-additive method and a full additive method), and can be formed, for example, in the following manner. That is, first, a resin sheet of the resin insulating layer 36 is attached to both front and back sides of the core substrate 20. Here, the Young's modulus of the resin insulating layer 36 at normal temperature is 2 to 7 GPa. The resin sheet is formed of a recombinant epoxy resin sheet, a polyphenylene ether resin sheet, a polyimide film, or a cyano ester resin sheet, and has a thickness of approximately 20 to 80 / zm. The resin sheet may contain an inorganic component such as deuterium oxide, aluminum oxide or oxygen. Next, in the attached resin sheet, a liquid crystal laser, a UV laser, a YAG laser, or an excited molecular laser is used to form a through hole and is used as a resin insulating layer 36 in the resin. Electroless copper plating is performed on the surface of the insulating layer 36 and the inside of the through hole to form a conductor layer. A plating resist is formed on the conductor layer, and electrolytic copper plating is performed on a portion where the plating resist is not formed, and the electroless copper under the plating resist is removed by an etching solution to form a wiring pattern 32. Further, the conductor layer inside the through hole is used as the through hole 34. Thereafter, this step is repeated to form the stacking portion 30. The layered capacitor portion 40 is a high dielectric layer 43 formed by firing a ceramic high dielectric material at a high temperature, and a first layered electrode 41 and a second layer sandwiching the high dielectric layer 43. The electrode 42 is formed. The first layered electrode 41 of the layered capacitor portion 40 is a copper electrode, and is electrically connected to the grounding connection pad 161 of the mounting portion 60. The second layered electrode 42 is a copper electrode and is electrically connected to the mounting portion 60. The power supply connection pad 62. Therefore, the first and second layered electrodes 41 and 42 are respectively connected to the ground line and the power supply line of the semiconductor element mounted on the mounting portion. Further, the first layered electrode 41 is formed in a flat coating pattern formed on the lower surface of the high dielectric layer 43, and has a through hole 41a penetrating through the through hole 62b of the power supply connection pad 62 in a non-contact state. Each of the power supply connection pads 62 is connected to the second layered electrode 42 via a through hole 62a, and the through hole 62b is disposed corresponding to the partial through hole 62a. Since each of the through holes 62 a is connected to the second layered electrode 42 , it can be connected to the ground line through the through hole 62 b as long as it has at least one through hole 62 b extending downward from the second layered electrode 42 . . On the other hand, the second layered electrode 42 is a flat coating pattern formed on the upper surface of the high dielectric layer 43, and has a through hole 42a that is connected to the through hole 6 1 a of the ground connection pad 6 1 in a non-contact state. Further, the distance between the first and second layered electrodes 41 and 42 is set to -14 to 201116186 to 10/zm or less, and substantially no short-circuit distance occurs. Further, the high dielectric layer 43 is high in one or more metal oxides selected from the group consisting of BaTi03, SrTiO3, Ta03, Ta205, PZT, PLZT, PNZT, PCZT, and PSZT. The dielectric material is formed into a film shape of 0.1 to 〇, and then fired to form a ceramic. Further, the manufacturing procedure of the layered capacitor portion 40 will be described in detail later. Here, the layered capacitor portion 40 will be further described in detail, and φ is partially described as being redundant with the above description. The first layered electrode 41 of the layered capacitor portion 40 is electrically connected to the grounding connection pad 61 of the mounting portion 60 via the through hole 61a, and the second layered electrode 42 is electrically connected to the mounting portion 60 via the through hole 62a. The power supply connection pad 62. Therefore, the first and second layered electrodes 41 and 42 are respectively connected to the ground line and the power supply line of the semiconductor element mounted on the mounting portion 60. Further, the first layered electrode 41 is formed in a flat pattern on the lower surface of the high dielectric layer 43, and has a through hole 41a penetrating through the through hole 62b of the second layered electrode 42 in a non-contact state. Further, the through hole 62b may be disposed so as to correspond to all of the connection holes 62 for the power source. However, the hole 62b is provided so as to correspond to the portion of the power supply connection pad 62. Since the second layered electrode 42 is connected to each of the power supply connection pads 62 via the respective through holes 62 a, it is sufficient to have at least one through hole 62 b ′ extending downward from the second layered electrode 42 . 62b Connect all power supply connection pads 62 to the external power line. In this way, by providing the through hole 62b' so as to correspond to the portion of the power supply connection pad 62, the number of the through holes 41a disposed in the first layered electrode 41 can be reduced, so that the first layered electrode 41 has a large area. The layered capacitor portion 40 also has a large electrostatic capacitance. Further, the position at which the through hole 4 1 a is formed should be determined after considering the arrangement of the capacitor -15 - 201116186 capacitor and the via hole 62a of the layered capacitor portion 4 . On the other hand, the second layered electrode 42 is a flat coating pattern formed on the upper surface of the high dielectric layer 43, and has a through hole 42a that is connected to the through hole 6 1 a of the grounding connection pad 6 1 in a non-contact state. The hole 42a may be disposed so as to correspond to all of the grounding connection pads 6'. However, the second layered electrode 42 is connected to the plurality of grounding connection pads 6 1 on the upper side, and only the partial grounding connection pads are used. 6 1 forms a through hole 6 1 a and penetrates the through hole 42 a of the second layered electrode 42 in a non-contact state. In this way, the through hole 6 1 a is disposed so as to correspond to the partial grounding connection pad 6 1 , so that the number of the through holes 42 a disposed in the second layered electrode 42 can be reduced, so that the second layered electrode 42 has a larger size. The area of the layered capacitor portion 40 also has a large electrostatic capacitance. Further, the position at which the through hole 42a is formed should be determined after considering the electrostatic capacitance of the layered capacitor portion 40 and the arrangement of the through holes 62a. The stress relieving portion 50 is formed of an elastic material. The elastic material is not particularly limited, and for example, an organic resin such as a recombined epoxy resin sheet, a polyphenylene ether resin sheet, a polyimide film, a cyano ester resin sheet, or a melamine resin sheet can be used. Sheet. The organic resin sheet may contain a polyolefin resin of a thermoplastic resin, a polyimide resin, a resin of a thermosetting resin, a rubber resin such as SBR, NBR, or urethane, or may contain a ruthenium oxide. An inorganic, fibrous, crucible or flat material such as aluminum oxide or zirconium oxide. The Young's modulus of the stress relieving portion 50 should be a lower 値 of 10 to 100 MPa. When the Young's modulus of the stress relaxation portion 50 is in the above range, the stress is generated when the semiconductor element and the layered capacitor portion mounted on the mounting portion 60 are inferior in thermal expansion coefficient, and the stress can be alleviated. -16- 201116186 The mounting portion 60 is a region for mounting a semiconductor element and is formed on the surface of the multilayer printed wiring board 1 . The mounting portion 60 is provided with a ground connection pad 61, a power supply connection pad 62, and a signal connection pad 63 in a lattice shape or a cross shape (see Fig. 1). Further, the grounding connection pad 6 1 and the power supply connection pad 62 may be arranged in a lattice shape or a cross shape near the center, and the signal connection pads 6 3 may be arranged in a lattice shape, a cross shape or a random manner around the center. . The grounding connection pad 6 1 and the power supply connection pad 6 2 should be arranged in an interactive manner. The number of terminals of the mounting portion 60 of the φ is 1 〇〇〇 to 300,000. A plurality of wafer capacitor arrangement regions 70 are formed around the mounting portion 60 (see Fig. 1). The wafer capacitor arrangement region 70 is formed with a plurality of pairs of ground connection pads 71 and power supply connection pads 72 for connecting the ground terminals of the wafer capacitors 73 and the power supply terminals. Further, each of the grounding connection pads 71 is connected to the negative electrode of the external power source via the first layered electrode 41 of the layered capacitor portion 40, and each of the power supply connection pads 72 is connected to the positive electrode of the external power source via the second layered electrode 42. . Next, a use example φ of the multilayer printed wiring board 10 having such a configuration will be described. First, the power supply terminal and the ground terminal of the wafer capacitor 73 are soldered to the ground connection pad 71 and the power supply connection pad 72 of the wafer capacitor arrangement region 70, respectively. Next, the semiconductor component on which the majority of the solder bumps are arranged on the back surface is placed on the mounting portion 60. At this time, the grounding terminal for the semiconductor element, the power supply terminal, and the signal terminal are respectively brought into contact with the grounding connection pad 61 of the mounting portion 60, the power supply connection pad 62, and the signal connection pad 63. Next, each terminal is soldered by reflow soldering. Thereafter, the multilayer printed wiring board 10 is bonded to another printed wiring board such as a mother board. At this time, solder bumps are formed on the bonding pads which are formed in advance on the back surface of the multilayer printed wiring board 1 and are joined by reflow in a state of being in contact with the corresponding bonding pads on the other printed wiring boards -17-201116186. Next, the manufacturing steps of the multilayer printed wiring board 10 of the present embodiment will be described. Since the steps of fabricating the core substrate 20 and the stacking portion 30 are well known, the steps of fabricating the layered capacitor portion 40 and the stress relieving portion 50 will be mainly described. Fig. 4 to Fig. 7 are explanatory diagrams of this step. First, as shown in Fig. 4(a), the core substrate 20 in which the deposition portion 30 is formed at least on one side is prepared, and the interlayer insulating layer 410 is laminated by a vacuum laminator at a temperature of 50 to 150 ° C and a pressure of 0.5 to 1.5 MPa. Attached to the stacking portion 30. Next, the pre-made high dielectric sheet 420 is attached to the interlayer insulating layer 410 by a vacuum laminator at a temperature of 50 to 150 ° C and a pressure of 55 to 1.5 MPa. Hardening at °C for 3 hours (refer to Figure 4(b)). Here, the high dielectric sheet 420 is produced in the following manner. That is, in a copper foil 422 having a thickness of 12 // m (later the first layered electrode 41), a press such as a roll coater and a doctor blade will contain BaTi03, SrTi03, Ta03, Ta205, PZT, PLZT, PNZT. A high dielectric material of one or more metal oxides selected from the group consisting of PCZT and PSZT is printed as a film having a thickness of 0.1 to 10 μm, and is used as an unfired layer. After the printing, the unfired layer is fired in a vacuum or in a non-oxidizing atmosphere such as N2 gas at a temperature of from 600 to 950 °C, and is used as the high dielectric layer 424. Thereafter, a metal layer such as copper, platinum, or gold is formed on the high dielectric layer 424 by a vacuum vapor deposition apparatus such as sputtering, and the metal layer has a copper layer of about 10/m by electrolytic plating or the like. A metal such as nickel or tin is used to form the upper metal layer 426 (the portion of the second layered electrode 42 later). As a result, a high dielectric sheet 420 is obtained. 201116186 Next, a commercially available dry film 430 is attached to a substrate on which a high dielectric sheet 420 is laminated (see FIG. 4(c)), and is often used for patterning using a multilayer printed wiring board. Patterning of the high dielectric sheet 420 is performed by development (see Fig. 4 (d)), etching (see Fig. 4 (e)), and film peeling (see Fig. 4 (f)). Further, the etching step uses a copper chloride etching solution. Next, the dry film 440 is again attached to the substrate in which the φ patterning of the high dielectric sheet 420 is performed (see Fig. 5(a)), and exposure and development are performed (refer to Fig. 5(b). The etching (see Fig. 5(c)) and the film peeling (see Fig. 5(d)) are performed to pattern the metal layer 426 and the high dielectric layer 424 on the high dielectric sheet 420. Further, the etching step uses a copper chloride etching solution, however, it is a short-time treatment in which only the copper foil 422 is slightly etched after being etched to the metal layer 426 and the high dielectric layer 424. Next, on the substrate in which the patterning φ of the metal layer 426 and the high dielectric layer 424 is formed, the interlaminar filling resin 450 is filled with a grout roll (see FIG. 5(e)). It was dried at 100 ° C for 20 minutes. Here, 100 parts by weight of a bisphenol F-type epoxy monomer (manufactured by Japan Epoxy Resins Co., Ltd., molecular weight 310, trade name YL983 U) and 72 parts by weight of a surface-covered decane coupling material were mixed and stirred in a container. SiO 2 spherical particles having a maximum particle diameter of 1.6 μm or less and a particle diameter of 15 μm or less (manufactured by ADTEC Corporation, trade name: CRS1101-CE), and 1.5 parts by weight of a leveling agent (manufactured by SAN NOPCO LIMITED, trade name PELENOL S4) The inter-layer filling resin 450 is prepared. Its viscosity is 23~1 -19-201116186 °C for 30~60P a / s. Further, 6.5 parts by weight of an imidazole curing agent (manufactured by Shikoku Kasei Co., Ltd., trade name 2E4MZ-CN) was used as the curing agent. Further, after the resin 450 was filled and dried, the surface of the substrate to be produced was honed until high. The surface of the upper metal layer 426 of the dielectric sheet 420 is exposed, and planarization is performed. Next, heat treatment is performed for 1 hour at 1 ° C and 1 hour at 150 ° C to cure the resin 45 0. The high dielectric interlayer filling layer 452 (refer to Fig. 5 (f)). Next, a specific portion of the surface of the substrate in which the high dielectric interlayer filling layer 452 is formed is formed by using a carbon dioxide laser, a UV laser, a YAG laser, and an excited molecular laser to form the stacking portion 3 Wiring pattern 0 of 0 2 through-hole 454 on the surface (refer to Fig. 6 (a)). Next, after the electroless plating catalyst is attached to the surface of the substrate to be produced, the substrate is immersed in an electroless copper plating aqueous solution, the inner wall of the through hole 45 4, the surface of the high dielectric sheet 420, and the high medium. An electroless copper plating film 456 having a thickness of 0.6 to 3.0 " m is formed on the surface of the electrically charged interlayer filling layer 452 (see Fig. 6(b)). Further, the electroless plating aqueous solution is one having the following composition. Copper sulfate: 0.03mol/L, EDTA: 0.200mol/L, HCHO: O.lg/ L, NaOH: 0.1mol/L, α, α'-biguanide: l〇〇mg/L, polyethylene glycol (PEG) : O.lg/ L.

Next, the commercially available dry film 460 is attached to the electroless copper plating film 456 (refer to Fig. 6 (c)), and exposed, developed, and etched to form a through hole 462 (refer to Fig. 6 (d) )), an electrolytic copper plating film 464 having a thickness of 25 /Z m is formed on the surface of the through hole 462 (refer to Fig. 6 (e)). Further, the electrolytic copper plating solution uses a composition having the following composition. Sulfuric acid: 2 00 g / L 201116186 , copper sulfate: 80 g / L, additive: 1 9.5 ml / L (ATOTECH JAPAN company, KAPAROSHIDO GL). Further, electrolytic copper plating was carried out under the following conditions. The current density is 1 A/dm2, the time is 1 15 minutes, and the temperature is 23±2t. Next, the dry film 460 is peeled off, and the portion of the dry film 460 remains, that is, the electroless copper plating film 456 existing between the electrolytic copper plating film 464 and the upper metal layer 426 of the high dielectric sheet 420. The exposed portion was etched with a sulfuric acid-hydrogen peroxide-based etching solution (see Fig. 6(f)). After the step φ, the layered capacitor portion 40 can be formed on the stacking portion 30. That is, the copper foil 422 corresponds to the first layered electrode 41, and the high dielectric layer 424 corresponds to the high dielectric layer 43, the upper metal layer 426, the electroless copper plating film 456, and the electrolytic copper plating film 464. It corresponds to the second layered electrode 42. Next, an aqueous solution containing NaOH (10 g/L), NaC102 (40 g/L), and Na3P〇4 (6 g/L) is used as a blackening liquid (oxidizing liquid) on the substrate in which the electrolytic copper film 464 has been formed. The blackening treatment and the reduction treatment of the aqueous solution containing NaOH (10 g/L) and NaBH4 (6 g/L) as φ as the reducing solution, so that the surface of the electrolytic copper plating film 464 becomes a roughened surface (not shown) . Then, the resin insulating sheet 470 is attached to the layered capacitor portion 40 by a vacuum laminator at a temperature of 50 to 150 ° C and a pressure of 0.5 to 1.5 MPa, and then cured at 150 ° C for 3 hours (refer to Figure 7 (a)). The resin insulating sheet 470 is a recombined epoxy resin sheet, a polyphenylene ether resin sheet, a polyimide film, a cyanoester resin sheet, or a melamine resin sheet, and may also contain a thermoplastic resin. A rubber-based resin such as a polyolefin resin, a polyimide resin, a thermosetting resin, or a rubber resin such as SBR, NBR, or urethane may contain a dispersed oxygen of -21 to 201116186. An inorganic, fibrous, crucible, or flat material such as aluminum oxide or zirconium oxide. Further, the resin insulating sheet 470 should have a Young's modulus of 10 to 100 MPa. If the Young's modulus of the resin insulating sheet 470 is in this range, the stress caused by the difference in thermal expansion coefficient between the semiconductor element and the substrate can be alleviated.

On the resin insulating sheet 470, a CO 2 laser is used to 0. 4mm mask diameter, 2.  The energy density of Omj and the condition of one stroke form a through hole 472 of 0 65 μm (refer to Fig. 7(b)). Thereafter, it was immersed in a 60 g/L solution containing permanganic acid at 80 ° C for 10 minutes to carry out roughening of the surface of the resin insulating sheet 4 70. Next, the substrate which was subjected to roughening was immersed in a neutralizing solution (manufactured by Shipley Co., Ltd., trade name Circuit Board MLB NEUTRALIZER) and washed with water. Further, the substrate is immersed in a catalyst liquid containing palladium chloride (PbCl 2 ) and lanthanum chloride (SnCl 2 ) to precipitate palladium metal, and the palladium catalyst is attached to the surface of the resin insulating sheet 470 (including the through hole 472). Wall). Next, the substrate was immersed in an electroless copper plating aqueous solution, and treated at a liquid temperature of 34 ° C for 40 minutes to form a thickness of 0 on the surface of the resin insulating sheet 470 and the wall surface of the through hole 472. 6~3. 0 //m electroless copper plating film (not shown). Further, an electroless copper plating aqueous solution is used having the following composition. Copper sulfate: 〇. 〇3mol/L, EDTA: 0. 200mol/L, HCHO: 0 · 1 g / L, N a Ο Η : 0 · 1 m ο 1 / L, acridine: l〇〇mg/L, polyethylene glycol (PEG): 〇. Lg / L. Next, a dry film was formed on the electroless copper plating film, and an electrolytic copper plating film (not shown) having a thickness of 25/zm was formed under the following conditions. Further, the electrolytic copper plating solution uses a composition having the following composition. Sulfuric acid: 200g / L 201116186 ' Copper sulfate: 80g / L, additive: 19. 5 ml/L (manufactured by ATOTECH JAPAN, KAPAROSHIDO GL). Further, electrolytic copper is carried out under the following conditions. Current density 1 A/dm2, time 1 15 minutes, temperature 23 ± 2 °C. Then, the dry film 460 is peeled off to obtain a multilayer printed wiring board 10 corresponding to Figs. 1 and 2 (see Fig. 7(c)). Further, the resin insulating sheet 470 corresponds to the stress relieving portion 50. Further, the copper plating film 474 of the through hole 472 is equivalent to the various terminals 61, 62, and 63. After that, the commercially available solder resist composition is applied and dried, and then the side on which the chrome layer is formed is adhered to the solder resist layer so that a circular pattern in which the solder resist opening portion is drawn by the chrome layer is placed. The soda-lime glass substrate of the mask pattern is subjected to heat treatment after exposure and development with ultraviolet rays, and a pattern of a solder resist layer having openings formed on the upper surfaces of the various terminals 61, 62, 63 is formed, and then electroless nickel plating is performed and further Electroless gold plating is performed to form a nickel plating layer and a gold plating layer, and the solder paste is printed and reflowed to form a solder bump. Further, a solder resist layer may be formed or a solder resist layer may not be formed. According to the multilayer printed wiring board 1A described in detail above, the high dielectric layer 43 of the layered capacitor portion 40 connected between the power supply line and the ground line is made of ceramic, and is made of a conventional organic resin-containing organic resin. In comparison, since the dielectric constant is high, the layered capacitor portion 40 also has a large electrostatic capacitance. Therefore, in the case where the frequency at which the semiconductor element is turned on and off is a high number of GHz to several tens of GHz (3 GHz to 20 GHz), a sufficient decoupling effect can be exhibited, so that an instantaneous drop in potential is less likely to occur. Further, in general, since the deposition portion 30 is usually produced under a temperature condition of 200 ° C or lower, it is difficult to perform the firing of the high--23-201116186 dielectric material on the way to form the deposition portion 30 to become a ceramic. In the above embodiment, since the high dielectric layer 43 of the layered capacitor portion 40 is formed by firing a high dielectric material separately from the deposition portion 30, it is easy to make it have a high dielectric. constant. Further, the first layered electrode 41 constituting the layered capacitor portion 40 is formed by a flat coating pattern on the first surface of the high dielectric layer 43 which is located farther from the mounting portion 60, that is, The flat coating pattern formed on the lower surface of the high dielectric layer 43 is formed by a flat coating pattern of the second surface closer to the mounting portion 60, that is, formed on the high dielectric layer 43. The upper flat pattern has a shape in which the through hole 42a that can be connected to the first layered electrode 41 passes through the hole 42a in a non-contact state, so that each of the layered electrodes 41 and 42 has a large enough area. The layered capacitor portion 40 also has a large electrostatic capacitance. Here, the through hole 61a connected to the first layered electrode 41 and the through hole 62a connecting the second layered electrode 42 are arranged in a lattice-like manner, and the loop inductance is low, so that it is easy to prevent the instantaneous decrease of the power supply potential. . In addition, the through holes 6 1 a and the through holes 62 a may also be cross-shaped and juxtaposed, and the same effect can be obtained. Further, since the distance between the first and second layered electrodes 41 and 42 of the layered capacitor portion 40 is set to be substantially no distance of 10/zm or less, the distance between the electrodes of the layered capacitor portion 40 is extremely small. Therefore, the layered capacitor portion 40 also has a large electrostatic capacitance. Next, when the static capacitance is insufficient due to only the layered capacitor portion 40, the wafer capacitor 73 can be used to supplement the insufficient portion. That is, the wafer capacitor 73 can be mounted as needed. In addition, the decoupling effect is lower because the wiring of the chip 201116186 chip capacitor 73 and the semiconductor element is longer. However, since the wafer capacitor 73 is provided on the surface side of the mounting portion 60, the wiring of the semiconductor element is shortened, so that it can be suppressed. The decoupling effect is reduced. Further, even if the semiconductor element mounted on the mounting portion 60 and the layered capacitor portion 40 or the stacking portion 30 are subjected to stress due to a difference in thermal expansion, the stress relieving portion 50 can absorb the stress without causing a problem. Further, the stress relieving portion 50 may be formed only under the positive φ of the semiconductor element mounted on the mounting portion 60. The stress caused by the difference in thermal expansion which causes problems is mainly located directly under the semiconductor element, and if the stress relieving portion 50 is formed only in this portion, the material cost can be reduced. Further, the present invention is not limited to the above embodiments, and may be various embodiments as long as it falls within the technical scope of the present invention. [Embodiment 2] Fig. 8 is a longitudinal sectional view of a multilayer printed wiring board 1 of Example 2 (φ is only shown on the left side of the center line). As shown in FIG. 8, the multilayer printed wiring board 1 10 of the present embodiment has a core substrate 20 similar to that of the first embodiment, and a through-hole 34 on the upper surface of the core substrate 20 is electrically connected to the resin insulating layer. 36. The stacked portion 30 of the wiring pattern 22 and the wiring pattern 32, the interlayer insulating layer 1200 laminated on the deposition portion 30, and the high dielectric layer 143 laminated on the interlayer insulating layer 120 and sandwiched therebetween The layered capacitor portion 140 composed of the first and second layered electrodes 141 and 142 of the high dielectric layer 143, and the stress relieving portion 150 formed of an elastic material laminated on the layered capacitor portion 1400 A mounting portion 160 for mounting a semiconductor element, and a wafer capacitor arrangement region 170 disposed around the mounting portion 160 - 25 - 201116186. The first layered electrode 141 of the layered capacitor portion 140 of the present embodiment is a copper electrode, and is electrically connected to the grounding connection pad 161 of the mounting portion 160 via the through hole 161a, and the second layered electrode 142 is copper. The electrode is electrically connected to the power supply connection pad 162 of the mounting portion 160 via the through hole 162a. Therefore, the first and second layered electrodes 141 and 142 are respectively connected to the ground line and the power supply line of the semiconductor element mounted on the mounting portion 160. Further, the first layered electrode 141 is formed in a flat coating pattern on the lower surface of the high dielectric layer 143, and has a through hole 141a penetrating through the through hole 162b of the second layered electrode 142 in a non-contact state. The through hole 162b may be disposed corresponding to all of the power supply connection pads 1 62, and is disposed to correspond to a part of the power supply connection pads 1 62. The reason is as follows. In other words, the plurality of power supply connection pads 162 of the power supply connection pads 162 are electrically connected to the second layered electrodes 142 via the through holes 162a, and the remaining power supply connection pads 162 are electrically connected via the through holes 162a. The other power supply connection pads 1 62 connected to the second layered electrode 142 and the unillustrated wirings (for example, the wirings disposed on the mounting portion 1 60) are electrically connected, so that all the power supply connection pads 1 62 are provided. Each of the power supply connection pads 1 62 is connected to the external power supply line via the through hole 162b as long as it has at least one through hole 162b extending downward from the second layered electrode 142. . Then, the number of the through holes 162a disposed in the first layered electrode 141 can be reduced by the number of the through holes 162a corresponding to the portion of the power supply connection pads 162, and the first layered electrode 141 has a large area. The capacitor portion 140 also has a large electrostatic capacitance. Further, the number of the through holes 141a and the position at which the through holes 141a are formed should be determined in consideration of the arrangement of the electrostatic capacitance of the layered capacitors 201116186 and the through holes 162a. On the other hand, the second layered electrode 142 is a flat coating pattern formed on the upper surface of the high dielectric layer 143, and has a through hole 142a that is connected to the through hole 161a of the grounding connection pad 161 in a non-contact state. The through hole 161a may be disposed so as to correspond to all of the grounding connection pads 161. However, the hole 161a is provided so as to correspond to the portion of the grounding connection pad 161. The reason is as follows. In other words, the grounding connection pads 161 are electrically connected by wires (for example, φ and wirings disposed on the mounting portion 160) which are not shown in the drawing, as long as they have at least one non-contact grounding connection pad 161. The through hole 161a' of the second layered electrode 142 which is extended downward is in contact with the first layered electrode 141, and all of the grounding connection pads 161 can be connected to the external grounding wire via the through hole 161a, and the corresponding portion is grounded. The connection pad 161 is provided with a through hole 1 6 1 a 'the number of the through holes 142a disposed in the second layered electrode 142 is reduced. The second layered electrode 142 has a large area, and the layered capacitor portion 14 is provided. 0 also has a large static capacitance. Further, the number of the through holes 142a and the position at which the through holes 142a are formed should be determined after the arrangement of the electrostatic capacitance of the layered capacitor portion 140 and the arrangement of the through holes 161a. As described above, since the layered capacitor portion 140 can have a large electrostatic capacitance, a sufficient decoupling effect can be exerted, and the transistor mounted on the semiconductor device (1C) of the mounting portion 160 is less likely to be insufficient in power supply. In addition, the wiring for the grounding connection pad 161 having no through hole directly underneath, and the wiring for the grounding connection pad 161 having the through hole directly underneath, and the power supply for electrically connecting the via hole without the through hole directly The pad 162 and the wiring for the power supply connection pad 162 having the through hole directly under the pad 162 may be disposed on the mounting portion 60, or -27-201116186 may be disposed on the surface of the core substrate 20 or the stacking portion 30. Further, a wiring layer may be further disposed between the layered capacitor portion 140 and the mounting portion 160 to connect the layers. The stress relieving portion 150 is formed of the same elastic material as in the first embodiment. Further, the grounding connection pads 161, the power supply connection pads 162, and the signal connection pads 163 disposed in the mounting portion 160 are arranged in a lattice shape or a cross shape (see Fig. 1). In addition, the grounding connection pad 161 and the power supply connection pad 1 62 may be arranged in a lattice shape or a cross shape near the center, and the signal connection pads may be arranged in a lattice shape, a cross shape or a random manner around the center. 163. The number of terminals of the mounting portion 160 is 1 〇〇〇 to 300,000. A plurality of wafer capacitor arrangement regions 1 70 are formed around the mounting portion 1 60, and a plurality of ground connection pads 171 for connecting the ground terminal and the power supply terminal of the wafer capacitor 173 are formed in the wafer capacitor arrangement region 170, and The power supply connection pad 172. Each of the grounding connection pads 171 is connected to the negative electrode of the external power source via the first layer electrode 141 of the layered capacitor portion 140, and each of the power source connection pads 172 is connected to the positive electrode of the external power source via the second layered electrode 142. The grounding connection pad 161 and the power supply connection pad 1 62 of the present embodiment correspond to the first connection pad and the second connection pad of the eighth item of the patent application, respectively, and the through hole 161a and the through hole 162b respectively correspond to the application. The first rod terminal and the second rod terminal of the eighth item of the patent range Next, the manufacturing steps of the multilayer printed wiring board 1 1 本 of the present embodiment will be described with reference to Figs. 9 to 11 . First, as shown in Fig. 9(a), a substrate 500 having a deposition portion 30 formed on at least one side of the core substrate 20 is prepared, and a vacuum laminator is used at a temperature of 50 201116186 to 150 ° C and a pressure of 5 5 to 1. In the lamination condition of 5 MPa, the interlayer insulating layer 510 (the thermosetting insulating film which is the interlayer resin layer 120 of Fig. 8 'ABF-45SH, manufactured by AJINOMOTO Co., Ltd.) is attached to the deposition portion 30. Secondly, the vacuum laminator is used at a temperature of 50 to 150 ° C and a pressure of 0. The lamination condition of 5 to 105 MPa is applied to the interlayer insulating layer 510 by preliminarily forming a high dielectric sheet 520 having a structure in which a copper foil 5 22 and a copper foil 5 26 sandwich the high dielectric layer 524, and thereafter, Dry at 150 ° C for 1 hour (see Figure 9 (b)) φ . The two copper foils 522, 526 of the high dielectric sheet 520 during lamination should all be flat coatings that do not form an electrical circuit. If one of the two copper foils 5 22 and 5 26 is removed by etching or the like, (i) the metal residual ratio of the front side or the back surface is changed, or the high dielectric sheet is formed into a meandering shape by using the removed portion as a starting point. Ii) If a part of the copper foil is removed to form a corner (refer to Fig. 12), the lamination pressure will concentrate on the portion '(iii) because the laminator is in direct contact with the high dielectric layer, etc. 'high dielectric layer Cracks are likely to occur, and in the subsequent plating step, if the cracked portion is plated, a short circuit is formed between the two copper foils. In addition, if some of the electrodes are removed before stacking, the static capacitance of the high dielectric sheet is reduced. When the stack of the high dielectric sheets is performed, it is necessary to implement a high dielectric sheet and a stack. Position and fit again. In addition, since the high dielectric sheet is thin and not rigid, the positional accuracy of removing a part of the copper foil is inferior. In addition, it is necessary to remove a part of the copper foil in consideration of the precision of the alignment. Therefore, it is necessary to remove a large amount of copper foil, and the accuracy of the alignment is also deteriorated due to the thinness of the high dielectric sheet. For the above reasons, the two copper boxes 522, 526 of the high dielectric sheet 520 at the time of lamination should all be flat coatings without forming an electrical circuit. Next, the production steps of the high dielectric sheet 52A will be described. -29- 201116186 (1) In dry nitrogen, the concentration will be l. o Moule / liter of diethoxy hydrazine and bis tetraisopropoxy titanium dissolved in dehydrated methanol and 2-methyl glycol mixed solvent (3: 2 by volume), nitrogen atmosphere at room temperature The stirring of 3 Torr was carried out to adjust the alkoxide precursor composition solution of bismuth and titanium. Next, the stirring of the precursor composition solution is carried out at 〇 ° C, to 0. At a rate of 5 μl/min, a pre-decarburized water spray was applied to the nitrogen stream to effect hydrolysis. (2) to 0. A 2-micron filter filters out precipitates and the like of the sol-gel solution prepared in this manner. (3) The filtrate prepared in the above (2) was spin-coated at 1,500 rpm for 1 minute on a copper foil 522 (hereinafter, the first layered electrode 141) having a thickness of 12/im. The substrate coated with the solution was placed on a hot plate maintained at 150 ° C and dried for 3 minutes. Thereafter, the substrate was placed in an electric furnace maintained at 850 ° C and fired for 15 minutes. Here, the film thickness can be obtained by spin coating/drying/sintering once. Adjust the viscosity of the molten gel solution in the manner of 〇3. Further, in addition to copper, the first layered electrode 141 may be made of nickel, platinum, gold, silver or the like. (4) Repeat 40 times of spin coating/drying/burning' to obtain 1. A high dielectric layer 524 of 2/zm. (5) Thereafter, a copper layer is formed on the high dielectric layer 524 by a vacuum vapor deposition apparatus such as sputtering, and copper is formed on the copper layer by electrolytic plating or the like to form a copper foil 526 (later) One of the two layered electrodes 142). In this way, a high dielectric sheet 520 can be obtained. The dielectric properties were measured using INPEDANCE / GAIN PHASE ANALYZER (manufactured by HEWLETT-201116186 PACHARD, product name: 4194A) at a frequency of 1 kHz, a temperature of 25 ° C, and a Ο SC level of IV. The relative dielectric constant was 1. 8 5 0. Further, a metal layer such as platinum or gold other than copper may be formed by vacuum deposition, or a metal layer such as nickel or tin other than copper may be formed by electrolytic plating. In addition, the high dielectric layer is barium titanate. However, with other lyophilized solutions, the high dielectric layer may also be barium titanate (SrTi03), molybdenum oxide (Ta03, Ta205), lead zirconate titanate (PZT). ), lead zirconate titanate (φ PLZT ), lead barium titanate (PNZT), lead zirconate titanate (PCZT), and pin strontium titanate (PS ZT ). In addition, the high dielectric sheet 520 can also be fabricated by other methods. In other words, 'the barium titanate powder (manufactured by FUTI TITANIUM INDUSTRY, HPBT system IJ) was dispersed in 5 parts by weight of polyvinyl alcohol, 50 parts by weight of pure water, and 1 with respect to the total weight of the barium titanate powder. a part by weight of a binder solution in which a solvent-based plasticizer is used in a ratio of diisooctyl phthalate or dibutyl phthalate, and a roll coater, a doctor blade, a φ α coater, or the like is used. The printing machine prints a copper foil 522 having a thickness of 12 // m (later the first layered electrode 141) into a film having a thickness of about 5 to 7 μm, and performing 6 hours of 6 CTC, 3 hours of 80 ° C, and 100 ° C. It was dried for 1 hour, 1 hour at 120 ° C, and 3 hours at 150 ° C, and used as an unfired layer. One or more selected from the group consisting of SrTi03, Ta03, Ta205, PZT, PLZT, PNZT, PCZT, and PSZT other than BaTi〇3 may be used by a printer such as a roll coater or a doctor blade. The metal oxide paste is printed to a thickness of 0. The film shape of 1 to 10 was dried and used as an unfired layer. After the printing, the unfired layer was fired at a temperature of from 600 to 950 ° C to a high dielectric layer 524. Thereafter, a copper layer is formed on the high dielectric layer 524 by a vacuum vapor deposition apparatus such as sputtering, and copper is formed on the copper layer by 10 or more degrees by electrolytic plating or the like to form a copper foil 526 (later) One of the two layered electrodes 142). Further, a metal layer such as platinum or gold other than copper may be formed by vacuum evaporation, or a metal layer such as nickel or tin other than copper may be formed by electrolytic plating. In addition, sputtering using barium titanate as a target can also be used. Next, through holes 530, 531 are formed at specific positions of the substrate in which the high dielectric sheet 520 has been laminated by using a carbon dioxide laser, a UV laser, a YAG laser, and an excited molecular laser. Refer to Figure 9(c)). The through hole 305 having a deep depth penetrates the through hole of the surface of the wiring pattern 3 2 of the high dielectric sheet 520 and the interlayer insulating layer 5 10 to the stacking portion 30. The deeper through hole 531 is a through hole of the copper foil 526 and the high dielectric layer 524 reaching the surface of the copper foil 522. Here, the through hole is formed by forming a deep through hole 53 0 and then forming a shallow through hole 53 1 » to adjust the depth by changing the number of laser strokes. Specifically, the through hole 53 1 utilizes Hitachi Via Mechanics, Ltd. The UV laser was applied under the conditions of an output of 3 to 10 W, a frequency of 30 to 60 kHz, and a stroke number of 4. The through hole 530 was the same except that the number of strokes was 3 1 . Then, the through-hole filling resin 532, which will be described later, is filled into the through-holes 530 and 531. The drying is carried out for one hour at 80 t, one hour at 120 ° C, and 30 minutes at 150 ° C (refer to Fig. 9). (d)). Further, the through holes 530 and 531 are not formed so as to correspond to all of the power supply connection pads 162 and the ground connection pads 161 shown in Fig. 8 . 201116186 A resin for through-hole filling was produced by the following method. Mix 100 parts by weight of bisphenol F-type epoxy monomer (Japan Epoxy Resins Co.) ,Ltd. Preparation, molecular weight: 3 10, trade name: E-8 07), and 6 parts by weight of imidazole hardener (four countries, product name: 2E4MZ-CN), in addition, 170 parts by weight of the average particle size of 1. 6O m of SiO 2 spherical particles were mixed into the mixture, and the mixture was kneaded by three rolls to adjust the viscosity of the mixture at 23 ± 1 ° C to 45,000 to 49000 cps to obtain a through-hole filling resin. φ Next, the through-holes 530a and 531a are formed by the resin 532 for filling the through-hole filling in the previous step, and the permanganic acid solution is immersed for roughening, and then dried and hardened at 1 70 ° C for 3 hours. Completely hardened (see Figure 9 (e)). The through hole 530a penetrates the through hole of the surface of the wiring pattern 32 of the stacking portion 30 through the resin 5323 for the through hole. The other through hole 53 la penetrates through the through hole hole filling resin 5 3 2, the copper foil 522, and the through hole of the interlayer insulating layer 510 reaching the surface of the wiring pattern 32 of the stacking portion 30. In addition, the through hole 5 30a uses a CO 2 laser to 0. 4mm mask diameter 0, 2. Omj's energy density and two-stroke conditions are formed, and the formation of the through hole 53 la is the same except that the UV laser is used for the 52 stroke, and the other conditions are the same (output: 3 to 10 w, frequency: 30 to 60 kHz). The electroless copper plating catalyst is attached to the surface of the substrate and immersed in the following electroless copper liquid to form a surface of 0. 6 to 3 · 0 v m No electrolytic copper plating film 5 40 (refer to Fig. 10 (a)). Further, an electroless copper plating aqueous solution is used having the following composition. Copper sulfate: 〇. 〇3mol/L, EDTA: 0. 200mol/L' HCHO: 0. 1g/L' NaOH: O. Lmol / 匕, 〇:, ^'-bisacridine: 1〇〇1^/[, PEG (?£0)0_18/1^ -33- 201116186 Secondly, the dry film of the market is attached to The electrolytic copper plating film 540 is subjected to exposure and development to form a plating resist 541 (see FIG. 10(b)), and an electrolytic copper film 542 having a thickness of 25/zm is formed in a portion where the plating resist is not formed (refer to 1〇图(c)). Further, the electrolytic copper plating solution uses a composition having the following composition. Sulfuric acid: 200g / L, copper sulfate: 80g / L, additives: 19. 5 ml/L (manufactured by ATOTECH J A P AN, K A P A R 0 S ΗID Ο GL ). Further, electrolytic copper plating was carried out under the following conditions. Current density 1 A / dm2, time 115 minutes, temperature 23 ± 2 °C. Next, the plating resist 541 is peeled off, and a portion of the plating resist 541 remaining thereon is etched with a sulfuric acid-hydrogen peroxide-based etching solution, that is, a sulfuric acid-hydrogen peroxide-based etching solution is present between the electrolytic copper plating film 542. The electroless copper plating film 540 is etched (rapidly etched) to form a molding section 544 that is coupled to the upper electrode 543 and the copper foil 522 (see Fig. 10(d)). Secondly, the temperature is 50~150 °C, the pressure is 〇·5~1. Lamination condition of 5 MPa The following stress relieving sheet 550 (stress relief portion 150 of Fig. 8) is attached to the upper electrode 543 and the molding section 544, and dried at 150 degrees for one hour (refer to Fig. 10 (e) )). The stress relieving sheet 550 was produced by the method shown below. In other words, 100 parts by weight of a naphthalene type epoxy resin (manufactured by Nippon Kayaku Co., Ltd., trade name: NC-7000L) and 20 parts by weight of phenol-two are dissolved by a roll coater (manufactured by CERMA TRONICS Trading Co., Ltd.). Toluene glycol condensed resin (manufactured by Mitsui Chemicals, trade name: XLC-LL), 90 parts by weight of carboxylic acid denatured NBR (JSR (stock) system, business 201116186 name) as a bridge rubber particle with a Tg of -50 °C : XER-91), and a resin composition of 300 parts by weight of ethyl lactate of 4 parts by weight of 1-cyanoethyl-2-ethyl-4-methylimidazole, coated on polymethylpentene (TPX) (Mitsubishi Petrochemical Industry, trade name: OPULENT X88) made of 42~45//m thick film, then 2 hours at 80 °C, 1 hour at 1 20 °C, 1 50 After drying at °C for 30 minutes, a stress relaxation sheet having a thickness of 40/zm was obtained. Further, the Young's modulus of the stress relieving sheet was 500 MPa at 30 °C. φ Next, at a specific position of the stress relieving sheet 550, a C02 laser is used. 1. 4mm mask diameter, 2. The energy density of 0 mj and the one-stroke forming via 560 (refer to Fig. 1 (a)). Next, the roughening treatment and the dry hardening at 150 ° C for 3 hours were carried out to completely cure the stress relieving sheet 505. Thereafter, a step of attaching a catalyst, chemical copper, plating formation, electroplating copper, plating peeling, and rapid etching is performed to fill the metal to the via 560, and a bonding pad is formed on each of the via holes 560 of the outermost layer ( The grounding connection pad 161, the power supply connection pad 1 62, and the signal connection pad 1 63 ) are used to obtain a multilayer printed wiring board 1 1 0 having a mounting portion φ 1 60 (Fig. 1 (b)). Further, the grounding connection pad 161 connected to the forming section 544 and the copper foil 540 is connected to the grounding wire, and the power supply connecting pad 162 connected to the upper electrode 543 is connected to the power supply line. Further, the signal connection pad 163 is connected to the signal line. Here, the copper foil 522 corresponds to the first layered electrode 141, the copper foil 526 and the upper electrode 543 correspond to the second layered electrode 142, and the high dielectric layer 524 corresponds to the high dielectric layer 143. Capacitor portion 140. Thereafter, solder bumps may be formed on the respective terminals of the mounting portion 60 (see Embodiment 1 for the formation method). Further, when the wafer capacitor 35-201116186 is mounted as shown in FIG. 8, after the step (b) of FIG. 9, the one terminal and the first terminal of the wafer capacitor 1 73 are electrically connected by the conductor 5 62. An etching step of the layered electrode 141 (so-called masking method). This etching step uses a copper chloride etching solution. However, after etching to the copper foil 526 and the high dielectric layer 524, only a small amount of etching of the copper foil 522 is performed for a short time. Finally, the metal layer bonded to the copper foil 522 is disposed on the stress relaxation sheet 550, and the connection pad 177 is disposed on the upper surface of the metal layer. Further, a bonding pad 1 72 for the purpose of connecting the other terminal of the wafer capacitor 173 is formed on the metal which is filled to a through hole 560 formed in the stress relaxation sheet 550. According to the multilayer printed wiring board 110 of the second embodiment described in detail above, the same effects as those of the above-described first embodiment can be obtained. In this embodiment, the electrostatic capacitance C of the layered capacitor portion 140 directly under the module is 0. The relative area S of the first layered electrode 141 and the second layered electrode 142 is determined by the method of 5/zF, and the number and position of the through holes 141a of the first layered electrode 141 are determined based on the relative area S, and The number and position of the through holes 142a of the two layered electrodes 142. Here, the relative area S is calculated using C = e Q · ε r · d / S. That is, since the high dielectric constant 142 has a relative dielectric constant ε·· of 1850 and a thickness d of 1. 2/zm, the 値 is substituted into the above formula, and the static capacitance C is 0. By substituting 5yF, the relative area S can be calculated. In addition, the dielectric constant (fixed number) of ε 〇 is vacuum. [Embodiment 3] Fig. 3 is a longitudinal sectional view of a multilayer printed wiring board 2 of Embodiment 3 (only the left side of the center line is shown). The multilayer printed wiring board 2 1 0 - 36 - 201116186 of the present embodiment has the same core substrate 20 as that of the first embodiment, and is electrically connected by the through hole 34 on the core substrate 20 as shown in FIG. The stacked portion 30 of the wiring pattern 22 and the wiring pattern 32 which are laminated via the resin insulating layer 36, the interlayer insulating layer 220 laminated on the deposition portion 30, and the high dielectric layer 243 laminated on the interlayer insulating layer 220 and The layered capacitor portion 240 including the first and second layered electrodes 241 and 242 sandwiching the high dielectric layer 243, the interlayer insulating layer 245 laminated on the layered capacitor portion 240, and the interlayer insulating layer φ The layer 245 has a stress relaxing portion 250 formed of an elastic material, a mounting portion 260 for mounting the semiconductor element, and a wafer capacitor arrangement region 270 disposed around the mounting portion 260. The first layered electrode 241 of the layered capacitor portion 240 of the present embodiment is formed on the copper electrode of the flat pattern on the lower surface of the high dielectric layer 243, and is electrically connected to the ground connection pad 261 of the mounting portion 260. In the description, the grounding connection pad 261 is divided into two types of a ground connection pad 261 and a ground connection pad 261y. The grounding connection pad 26 lx is electrically connected to the φ forming section 266x via the through hole 26 la. There is no through hole directly below the forming section 266x. In addition, the grounding connection pad 261 y is connected to the forming section 2 66y via the through hole 26 la, and the forming section 266y is electrically connected to the first layered electrode 241 via the through hole 26 lb. And the grounding wiring of the wiring pattern 3 2 of the stacking portion 30. Further, the forming section 268 connected to the through hole 261b and the second layered electrode 242 are electrically separated. Further, the forming section 266x connected to the grounding connection pad 26 lx and the forming section 266y connected to the grounding connection pad 261y are electrically connected by a wiring 246 (see Fig. 14). As a result, all of the grounding connection pads 26 1 will have the same potential. In this way, the first layered electrode 241 is connected to the grounding wiring of the wiring pattern 32 of the deposition unit 30, and is connected to the external ground line via the grounding wiring, in addition to the grounding connection pads 26 1 - 37 to 2011 16186. . In addition, the first layered electrode 24 1 has a through hole 241a that penetrates the through hole 262c described later in a non-contact state. However, the through hole 262c is disposed so as to correspond to the finite power supply connection pad 262y as will be described later. Therefore, only a small number of holes 24 la are required. As a result, the first layered electrode 24 1 has a large area, and the layered capacitor portion 240 also has a large electrostatic capacitance. Further, the number of the holes 241a and the position of the through holes 241a should be determined after considering the electrostatic capacitance of the layered capacitor portion 240 or the like. On the other hand, the second layered electrode 242 is a copper electrode formed in a flat pattern on the upper surface of the high dielectric layer 243, and is electrically connected to the power supply connection pad 262 of the mounting portion 260. In the description, the power supply connection pad 262 is divided into two types of the power supply connection pad 262x and the power supply connection pad 262y. The power supply connection pad 262x is coupled to the molding section 267x via the through hole 262a, and the molding section 267x is electrically connected to the second layered electrode 242 via the through hole 262b. Further, the power supply connecting pad 262y is connected to the forming section 267y via the through hole 262a. The forming section 267y is electrically connected to the stacking section 30 via the through hole 262c so as not to contact the first and second layered electrodes 241 and 242. The power supply wiring among the wiring patterns 32. Further, the forming section 267x connected to the power supply connection pad 2 62x and the molding section 267y connected to the power supply connection pad 262y are electrically connected by the wiring 247 (see Fig. 14). As a result, all of the power supply connection pads 262 will have the same potential. The second layer electrode 242 is connected to the power supply wiring of the wiring pattern 3 2 of the deposition unit 30 in addition to the connection pads 2 6 2 of the power supply, and is connected to the external power source 201116186 via the power supply wiring. . Therefore, the second layered electrode 242 can be supplied with power from the power supply wiring of the wiring pattern 3 of the stacking portion 30 via the through hole 262c, the wiring 247, and the through hole 262b. Further, the second layered electrode 242 has a through hole 242a that penetrates the through hole 262c in a non-contact state, and a through hole 242b for the purpose of ensuring insulation with the forming section 268. However, the through hole 262c is disposed in the power supply connection pad 262. One of the power supply connection pads 262y and the through holes 242b are provided with φ corresponding to the ground connection pads 26 1 y of a portion of the ground connection pads 26 1 , so that fewer pass holes are provided. The number of 242a, 242b. As a result, the second layered electrode 2 42 has a large area, and the layered capacitor portion 240 also has a large electrostatic capacitance. Further, the number of the through holes 242a, 242b and the position at which the through holes 2 42a, 242b are formed should be determined after considering the static capacitance of the layered capacitor portion 240 or the like. Thus, since the layered capacitor portion 240 can have a large electrostatic capacitance, it has a sufficient decoupling effect, and the transistor mounted on the semiconductor element (1C) of the mounting portion 2 60 is less likely to be insufficient in power supply. Further, the grounding φ connection pad 261x and the ground connection pad 261y are connected via the wiring 246 on the interlayer insulating layer 245, and the power supply connection pad 262x and the power supply connection pad 262y are formed via the wiring 247 on the interlayer insulating layer 245. Although it is connected, such a wiring may be disposed on any one of the layers above the second layered electrode (the mounting portion may be), the surface of the core substrate 20, and the deposition portion 30. In addition, when the grounding connection pad 26 1 X and the grounding connection pad 261y, and the power supply connection pad 262x and the power supply connection pad 262y are connected to each other, it is not necessary to arrange the through holes 261a in all the ground connection pads. Immediately below 261, it is not necessary to arrange the through holes 262a under the positive-39-201116186 of all the power supply connection pads 262. In this way, the number of forming segments of the layer directly below the mounting portion can also be reduced. Therefore, since the number of through holes and the number of forming sections that must be disposed can be reduced, the density can be increased. The stress relaxing portion 250 is formed of the same elastic material as in the first embodiment. In addition, the grounding connection pad 261, the power supply connection pad 262, and the signal connection pad 263 which are disposed in the mounting portion 260 are arranged in a lattice shape or a cross shape in the same manner as in the first embodiment (see FIG. 1). In addition, the number is also the same as that of the first embodiment. Here, the signal connection pad 263 does not contact any of the first and second layer electrodes 241 and 242 of the layered capacitor portion 240. Further, the grounding connection pad 261 and the power supply connection pad 262 may be arranged in a lattice shape or a cross shape near the center, and the signal connection pads 263 may be arranged in a lattice shape, a cross shape or a random manner around the center. A plurality of wafer capacitor arrangement regions 270 are formed around the mounting portion 260. The wafer capacitor arrangement region 270 forms a plurality of pairs of ground connection pads 271 and power supply connection pads for connecting the ground terminal and the power supply terminal of the wafer capacitor 273. 272. Each of the grounding connection pads 271 is connected to the negative electrode of the external power supply via the first layered electrode 241 of the layered capacitor portion 240, and each of the power supply connection pads 272 is connected to the positive electrode of the external power supply via the second layered electrode 242. The grounding connection pad 26 1 and the power supply connection pad 262 of the present embodiment correspond to the first connection pad and the second connection pad of claim 9 of the patent application, respectively, and the through hole 261b and the through hole 262c are respectively equivalent to the patent application. The first rod terminal and the second rod terminal of the ninth item. Each of the grounding connection pads 271 is connected to the negative electrode of the external power supply via the first layer 201116186 electrode 241 of the layered capacitor portion 240, and each of the power supply connection pads 272 is connected to the positive electrode of the external power supply via the second layered electrode 242. The grounding connection pad 261 and the power supply connection pad 262 of the present embodiment correspond to the first connection pad and the second connection pad of the sixth item of the patent application, the through holes 261a and 2 61b, and the through holes 2 62 a and 262b, respectively. It is equivalent to the first rod terminal and the second rod terminal of the sixth item of the patent application. Next, a manufacturing procedure of the multilayer printed φ brush wiring board 210 of the present embodiment will be described with reference to Figs. 15 to 17 . In addition, in the first and third embodiments, the power supply connection pad 261 and the ground connection pad 262 directly under the semiconductor element (that is, directly below the module) are arranged in a lattice or cross shape. In the cut sectional view, the sectional views of the power supply connection pad 261 and the ground connection pad 262 are alternately arranged in the first to fifth embodiments.

First, as shown in Fig. 15 (a), a substrate 600 having a deposition portion 30 formed on at least one side of the core substrate 20 is prepared, and a vacuum laminator is used at a temperature of 50 to 150 ° C and a pressure of 〇. 5~ 1. 5 Μ P a lamination condition The interlayer insulating layer • 610 (thermosetting insulating film, AJINOMOTO Co., Ltd., ABF-45SH) was attached to the deposition unit 30. Next, a high dielectric sheet 620 is prepared in advance by a vacuum laminator at a temperature of 50 to 150 ° C and a pressure of 0.5 to 1.5 MPa (the production steps are the same as those of the high dielectric sheet 520 of the second embodiment). The interlayer insulating layer 610 (becomes the interlayer insulating layer 220 of Fig. 3) is then dried at 150 ° C for 1 hour (see Fig. 15 (b)). The copper foils 622, 626 of the high dielectric foil 620 are all flat layers that do not form an electrical circuit. Thereafter, etching of the high dielectric sheet 620 is performed by a masking method. In the etching step, a copper chloride etching solution is used. However, after etching to the copper foils 626-41 to 201116186 and the high dielectric layer 624, only a small amount of etching is performed on the copper foil 62 2 (refer to the first step). 5 Figure (c)). In Fig. 15(c), a portion of the copper foil 626 is etched into an isolated shaped section 626a (which becomes the forming section 268 of Fig. 3). Then, an interlayer insulating layer (which is an interlayer insulating layer 245 of Fig. 3, a thermosetting insulating film, ABF-45SH, manufactured by Azbil Corporation) 628 is laminated on the high dielectric sheet 620 (Fig. 15(d) ). Next, a through hole 630 is formed at a specific position of the substrate in which the interlayer insulating layer 628 is laminated, using a carbon dioxide laser, a UV laser, a YAG laser, and an excited molecular laser (see FIG. 15 (e). )). A through hole 630 penetrating the interlayer insulating layer 62 8 , the high dielectric sheet 620 , and the interlayer insulating layer 610 on the surface of the wiring pattern 32 of the stacking portion 30 is formed. The laser conditions were obtained by using a UV laser manufactured by Hitachi Via Mechanics, Ltd., which was an output of 3 to 1 OkW, a frequency of 30 to 60 kHz, and a stroke number of 54. After the through hole 63 0 is formed, the through hole filling resin 640 (the manufacturing step is the same as the through hole filling resin 5 3 2 of the second embodiment) is filled in the through hole 63 0 and dried (refer to Fig. 16). (a)). Next, a through hole 651, 6 5 2, 65 3 is formed at a specific position of the substrate in the fabrication by using a carbon dioxide laser, a UV laser, a YAG laser, and an excited molecular laser (see FIG. b)). The through hole 65 1 is formed to penetrate the surface of the wiring pattern 32 of the through-hole filling resin 640 to reach the deposition portion 30, and the through hole 652 is formed so as to penetrate the surface of the copper foil 626 through the interlayer insulating layer 628. The hole 65 3 penetrates the interlayer insulating layer 628, the high dielectric sheet 620 (the forming section 626a, the high dielectric layer 624, and the copper foil 622), and the wiring of the interlayer insulating layer 610 to the stacking portion 30. The pattern 3 2 surface is formed in the form of 201116186. The through holes 651, 652, and 653 are formed by forming the through holes 651 and forming the through holes 652 and 653 in order. The depth adjustment of the perforation is adjusted by changing the type of laser and the number of laser strokes. For example, the through hole 65 1 is formed by using a CO 2 laser and adopting a mask diameter of 1.4 mm, an energy density of 2. Omj, and a 3-stroke condition, and the through hole 65 2 is the same as the foregoing except for one stroke. The through hole 653 is a UV laser and uses the same φ condition (output: 3 to 10 W, frequency: 30 to 60 kHz) other than the above-described conditions except for the 56 stroke. Further, the through hole 63 0 is not formed so as to correspond to only all of the power supply connection pads 262 shown in FIG. 13 (that is, corresponding to the power supply connection pad 2 62y ), and the through hole 653 is formed. It is not formed so as to correspond to only the corresponding portion (that is, the grounding connection pad 26 ly) so as to correspond to all of the grounding connection pads 26 1 shown in FIG. Thereafter, 1 7 (TC was dried and hardened for 3 hours to completely harden it. Next, the catalyst was attached to the surface of the substrate and subjected to a usual semi-additive method, and φ was respectively filled with metal to the through holes 651, 652. The through holes 2 62c , 262b , 261b are formed at 65 3 , and the forming segments 267 y , 267 x , 266 y ' are formed on the through holes 262 c 262 b , 261 b and further formed to join the forming segments 267 x and the forming segments 2 67 y Wiring 247 (refer to Fig. 16 (c)). The wiring pattern 32 of the deposition portion 30 and the copper foil 626 (the second layered electrode 242) are connected via the wiring 2々7. The forming section 2 6 6 X and the wiring 2 4 of Fig. 14 are second. Next, the stress relieving sheet 670 is formed (the object of the stress relieving portion 25 of Fig. 13 is formed, and the manufacturing step is referred to the stress relieving sheet 5 of the second embodiment. Lamination of the layer 5 (see Fig. 16 (d)) - 43 - 201116186 Next, a through hole 680 is formed at a position directly above each of the forming sections 267y, 267, and 266y of the stress relieving sheet 670 (refer to Fig. 17 (refer to Fig. 17 ( a)), and carry out roughening, complete hardening, adhesion catalyst, chemical copper, anti- The layer, the electroplated copper, the plating resist peeling, the rapid etching 'fills the metal to each of the through holes 68 0 and forms a joint pad on the filled metal (refer to Fig. 17 (b)). Therefore, it is formed on the forming section 267y. The through hole 262a and the power supply connection pad 262y form a through hole 262a and a power supply connection pad 262x in the molding section 267x, and a through hole 261a and a ground connection pad 261y are formed in the molding section 266y. The through hole 261a and the grounding connection pad 261x (not shown) are formed in the forming section 266x of Fig. 14. Thus, the multilayer printed wiring board 2110 of Fig. 13 can be obtained. Further, the copper foil 622 is equivalent to the first one. The layered electrode 241, the copper foil 626 corresponds to the second layered electrode 242, and the high dielectric layer 624 corresponds to the high dielectric layer 243, and the layered capacitor portion 240 is configured as described above. When the l lx is connected to the grounding connection pad 261 y by any layer (for example, the mounting portion 260 ), the through hole 26 la and the forming portion 2 66x are not required. Similarly, the electrode connecting pad 262x uses any layer (for example, the mounting portion 260). When it is connected to the electrode connection pad 262y, electricity is not required. The through hole 262a, the forming section 267x, and the through hole 2 62b directly under the bonding pad 262x are used. Thus, the through hole and the forming section can be reduced. Thereafter, a solder bump can be formed on each terminal of the mounting portion 260 (formed) The method is as described in the first embodiment. Further, as shown in Fig. 3, when the wafer capacitor 273 is mounted, the connection pads 271 and 272 may be formed in the same manner as in the second embodiment. According to the multilayer printed wiring board 1 1 〇, 201116186 of the embodiment 3 described in detail above, the same effects as those of the above-described first embodiment can be obtained. Further, in the present embodiment, since the layered capacitor portion 240 is not bypassed from the stacking portion 30, the high dielectric sheet 620 is electrically charged from the external power source via the through holes 262c, 262b, and the external power supply can be shortened. The source is used to connect the wiring length of the second layer electrode 20 of the power supply electrode of the layered capacitor portion 240 and the wiring length of the first layer electrode 241 for connecting the ground electrode. Therefore, even if the semiconductor element is driven at a high speed (1C) The mounting of the layered capacitor φ portion 240 in the mounting portion 260' is also less likely to cause insufficient charging. Further, in the present embodiment, the relative area S of the first layered electrode 241 and the second layered electrode 242 is determined such that the electrostatic capacitance C of the layered capacitor portion 24 directly below the module is 0.5 y F. Based on the relative area S, the number and position of the through holes 241a of the first layered electrode 241 and the number and position of the through holes 242a and 242b of the second layered electrode 242 are determined. Here, the relative area S is calculated using C = ε Q ♦ ε r · d / S. That is, since the relative dielectric constant ε^1850 of the high dielectric layer 242 and the thickness d thereof are 1.2/zm, the enthalpy is substituted into the above formula, and the electrostatic φ capacitance C is substituted by 〇. 5 // F. Calculate the relative area S. In addition, ε 〇 is the dielectric constant (fixed number) of the space. Further, in the above manufacturing step, the lamination of the interlayer insulating layer 6 2 8 is performed after the step of the step (c) of FIG. 15 (refer to FIG. 15 (d )), and is formed at a specific position of the interlayer insulating layer 628. The through hole 63 0 (see Fig. 15 (e)), and the through hole 630 is filled with the through hole filling resin 640 and dried (see Fig. 16 (a)), and then filled in the through hole. The through hole 65 1 is formed by the resin 640 (refer to Fig. 16 (b)). However, the method shown below can also be employed. That is, after the step of Fig. 15(c), -45-201116186 attaches a dry film of a commercially available product to the surface of the substrate, and then forms a through hole 262c by a masking method (refer to Fig. 16(c)). The position of the high dielectric sheet 620 is etched away to form an enlarged hole 632 larger than the through hole 262c (refer to FIG. 18(a)), and thereafter, the interlayer insulating layer 628 is laminated on the high dielectric sheet 620, and The enlarged insulating hole 632 which has just been formed by etching is filled with the interlayer insulating layer 628, and then dried (Fig. 18(b)). Next, the step of forming the through holes 651, 652, and 653 of the third embodiment may be carried out thereafter. Therefore, the step of filling the through holes 63 0 may be deleted. [Embodiment 4] The through hole 530 and the through hole 531 of the second embodiment are formed at positions corresponding to all of the power supply connection pads and the ground connection pads. As a result, the electrostatic capacitance of the layered capacitor portion becomes 0.4/ZF. [Example 5] The through hole 63 0 and the through hole 65 3 of the third embodiment were formed at positions corresponding to all of the power supply connection pads and the ground connection pads. As a result, the electrostatic capacitance of the layered capacitor portion was 0.4/i F. [Example 6] The number of repetitions of spin coating/drying/firing in the production step (4) of the high dielectric sheet of Example 2 was changed to 20 times to obtain a high dielectric layer of 0.6/z m. The rest is the same as in Embodiment 2. As a result, the static capacitance of the capacitor portion of the layered -46-201116186 directly under the module becomes 1.0//F. [Example 7] The procedure for producing the high dielectric sheet of Example 3 (z/the number of repetitions of drying/firing was changed to 20 times to obtain 0.6/electrolyte layer. The rest was the same as in Example 3. As a result, The electrostatic capacitance of the module lower capacitor portion was 1.0/z F. [Example 8] The procedure for producing the high dielectric sheet of Example 2 (</drying/firing repetition number was changed to 1 time) The result is 0.03 / electric layer. The rest is the same as in the second embodiment. As a result, the electrostatic capacitance of the capacitor portion of the module is 20/z F. [Example 9] The manufacturing procedure of the high dielectric sheet of Example 3 was carried out. The number of repetitions of the drying/baking was changed to one time to obtain a 0.03/electrolyte layer, and the rest was the same as in the third embodiment. As a result, the electrostatic capacitance of the positive-capacitor portion of the module was 20/z F. [Example 1] The procedure for producing the high dielectric sheet of Example 2 (z/the number of repetitions of drying/firing is changed to 4 times) gives the 〇12Α electric layer. The rest is the same as in the embodiment 2. As a result, the module is directly under ) The spin coating of the high-medium layer of the spin coating, the spin coating of the high-medium layer of the spin coating, the spin coating of the high-medium layer of the spin coating The layer of high dielectric layer -47 - 201116186 The capacitance of the capacitor is 5/zF. [Example 1 1] The high dielectric layer was obtained by changing the number of repetitions of spin coating/drying/firing in the production step (4) of the high dielectric sheet of Example 3 to four times. The rest is the same as in the third embodiment. As a result, the electrostatic capacitance of the layered capacitor portion directly under the module becomes 5/zF. [Example I2] The number of repetitions of spin coating/drying/firing in the production step (4) of the high dielectric sheet of Example 2 was changed to two times to obtain a high dielectric layer of 0.06 / m. The rest is the same as in Embodiment 2. As a result, the electrostatic capacitance directly under the module becomes 10//F. [Example I3] The number of repetitions of spin coating/drying/firing in the production step (4) of the high dielectric sheet of Example 3 was changed to two times to obtain a high dielectric layer of 0.06 #m. The rest is the same as in the third embodiment. As a result, the electrostatic capacitance directly under the module becomes 10/Z F . [Example M] The through hole 530 and the through hole 531 of the eighth embodiment were formed at positions corresponding to all of the power supply connection pads and the ground connection pads. As a result, the electrostatic capacitance is I 6 μ Έ. -48-201116186 [Embodiment 15] The through hole 630 and the through hole 653 of the ninth embodiment are formed at positions corresponding to all of the power supply connection pads and the ground connection pads. As a result, the electrostatic capacitance is 16 6 F. [Example 16] The number of repetitions of spin coating/drying/firing in the production step (4) of the high dielectric sheet of Example 2 was changed to 330 times to obtain a high dielectric layer of 10/zm. The rest is the same as in Embodiment 2. As a result, the electrostatic capacitance directly under the module becomes 0.06 #F. [Example 17] The number of repetitions of spin coating/drying/firing in the production step (4) of the high dielectric sheet of Example 3 was changed to 3 30 times to obtain a high dielectric φ of 1 〇β m Floor. The rest is the same as in the third embodiment. As a result, the electrostatic capacitance immediately below the module became 0.06 " F. [Example 18] The number of repetitions of spin coating/drying/firing in the production step (4) of the high dielectric sheet of Example 2 was changed to 10 times to obtain a high dielectric layer of 〇.3#m. . The rest is the same as in Embodiment 2. As a result, the electrostatic capacitance immediately below the module became 2.0 v F. -49-201116186 [Example 19] The number of repetitions of spin coating/drying/firing in the production step (4) of the high dielectric sheet of Example 3 was changed to 10 times to obtain a high dielectric of 0.3 m. Quality layer. The rest is the same as in the third embodiment. As a result, the electrostatic capacitance directly under the module becomes 2.0 /Z F. [Example 20] The number of repetitions of spin coating/drying/firing in the production step (4) of the high dielectric sheet of Example 2 was changed to 25 times to obtain a high dielectric layer of 0.75 em. The rest is the same as in Embodiment 2. As a result, the static capacitance directly below the module becomes 0.8 β F. [Example 21] The number of repetitions of spin coating/drying/firing in the production step (4) of the high dielectric sheet of Example 3 was changed to 25 times to obtain a high dielectric of 〇_75 //m. Floor. The rest is the same as in the third embodiment. As a result, the static capacitance immediately below the module becomes 0.8#F. [Example 22] A high-dielectric sheet of Example 3 was subjected to a etch processing in advance to remove a portion of the copper foil 626 and the high dielectric layer 624. Thereafter, the high dielectric was utilised by the interlayer insulating layer 610. The sheet is attached to the substrate 600 forming the stacking portion 30. That is, the high dielectric sheet attaching step of the third embodiment and the etching step of the high dielectric sheet are replaced. The subsequent steps are the same as in the third embodiment. -50-201116186 [Example 2 3] A wafer capacitor was mounted on the multilayer printed wiring board of Example 4. [Example 24] A wafer capacitor was mounted on the multilayer printed wiring board of Example 5. [Example 25] The stress relaxing portion 1 50 of Example 2 was replaced with an interlayer insulating layer 5 10 (refer to Fig. 9 (a)). The rest is the same as in Embodiment 2. [Example 26] The stress relaxation portion 250 of Example 3 was replaced with an interlayer insulating layer 610 (refer to Fig. 15 (a)). The rest is the same as in the third embodiment. φ [Examples 27 to 49] In Examples 27 to 49, a multilayer printed wiring board was produced by replacing the stress relaxation portions of Examples 2 to 24 with an interlayer insulating layer. [Comparative Example] The high dielectric sheet of the comparative example was produced by the other production steps of the high dielectric sheet described in Example 2. However, the electrode was formed on the unfired layer after drying without firing. The rest is the same as in Embodiment 2. As a result, the static capacitance directly below the module is 0.001 // F or less. -51 - 201116186 Evaluation Test 1 A 1C wafer having a drive frequency of 3.6 GHz and FSB 1 066 MHz was mounted on the multilayer printed wiring boards of Examples 2 to 49 and Comparative Example, and switching was repeated 100 times, using Pulse Pattern Generator / Error Detector. (Manufactured by ADVANTEST, trade name: D3 1 8 6 / 32 8 6 ), confirm whether there is any wrong operation. [Evaluation Test 2, HAST Test] A voltage of 3.3 V was applied between the first layered electrode and the second layered electrode of the multilayer printed wiring boards of Examples 2 to 49, and placed at 85 ° C X 8 5 %. The environment test machine was 50 hours. In the meantime, discharge was performed every 2 hours. After that, install the drive frequency 3.6〇1^,? 3810661^1^1 (: wafer, switching is performed 100 times at the same time, and the above-mentioned Pulse Pattern Generator/Error Detector is used to confirm the presence or absence of an erroneous operation. [Evaluation Test 3, HAST Test] In the same manner as Evaluation Test 2, A voltage of 3.3 V was applied between the first layered electrode and the second layered electrode of the multilayer printed wiring board after the evaluation test 2 was completed, and placed in an environmental tester at 85 ° C X 8 5 % for 50 hours. The discharge was performed every 2 hours. Then, a 1C wafer having a drive frequency of 3.6 GHz and FSB 1 066 MHz was mounted, and switching was repeated 100 times, and the pulse pattern generator / Error Detector was used to confirm the presence or absence of an erroneous operation. -52- 201116186 [Evaluation Test 4, Thermal Cycle Test] The following thermal cycle tests were carried out on the multilayer printed wiring boards of Examples 2 to 26. Thermal cycle test conditions: 100 times or 500 times - 55 ° C X 30 minutes, 1251 and 30 minutes later Install a 1C chip with a drive frequency of 3.6〇112 and ?3810661^1^ and repeat the switch of 1〇〇 times. Use the Pulse Pattern Generator / Error Detector to confirm the presence or absence. [Evaluation test 5] Install the drive frequency of 5.7〇112, [381066]^1121 (: wafer instead of the 1C wafer of the test frequency of 3.6 GHz, FSB 1 066 MHz, and the same test as the evaluation test 1 As a result, the multilayer printed wiring board having a static capacitance of 1.0 VF or more directly under the module does not malfunction. φ [Evaluation result] Table 1 is the result of evaluating the tests 1 to 4. When no malfunction is observed, 〇, when the erroneous action is observed, it is X. Further, Table 1 does not disclose the electrostatic capacitance immediately below the modules of Examples 27 to 49 and the evaluation results of the evaluation tests 1 to 3, however, the results are the same as those of Examples 2 to 24, respectively. -53- 201116186 Table 1 TH number of the corresponding terminal TH film high dielectric layer film thickness (//m) Capacitor directly below the module (#F) 崁1 C/C installation presence evaluation test results 1 2 3 4*2 5*3 Example 2 Part 1.2 0.5 IIM 〇〇X 〇X Example 3 Part 1.2 0.5 /far ΤΐιΓ j\\\ 〇〇X 〇X Example 4 All 1.2 0.4 ifrrt im: yns 〇XX 〇X Example 5 All 1.2 0.4 /frTf. ΤΠΤ y»\N 〇XX 〇X Example 6 0.6 1.0 /fnr. ΤΠΓ 〇〇〇〇〇 Example 7 Part 0.6 1.0 4ττγ. illl: 〇〇〇〇〇 Example 8 Part 0.03 20 fnT- mt: y\\\ 〇— 〇X Example 9 Part 0.03 20 /fnt- 1111: J\\\ 〇— 〇X Example 10 Part 0.12 5 -fm: Mi!: V, 〇〇〇〇〇Example 11 Part 0.12 5 /fnr ΤΤΤΠ 〇〇 〇〇〇Example 12 Part 0.06 10 ΤΤΓΓ />\N 〇〇X 〇X Example 13 Part 0.06 10 Ι1ΙΓ y\\\ 〇〇X 〇X Example 14 All 0.03 16 4rrr. IiH: y\ \\ 〇XX 〇X Example 15 All 0.03 16 ifrrr lilt! 〇XX 〇X Example 16 Part 10 0.06 irrr ΠιΤΤ 〇XX 〇X Example 部份 Part 10 0.06 4rrr TtrT 〇XX 〇X Example 18 Part 0.3 2.0 AnL ιιΙΓ j\\\ 〇〇〇〇〇 Example 19 Part 0.3 2.0 4πτ. tilt 〇〇〇〇〇 Example 20 Part 0.75 0.8 /fnr Tttr 〇〇〇〇〇 Example 21 Part 0.75 0.8 Inn J\\\ 〇〇〇〇〇Example 22 Part 1.2 0.3 >fnt- ΤΤΤΠ 〇 — —〇X Example 23 All 1.2 0.4 〇〇〇〇〇 Example 24 All 1.2 0.4 〇〇〇〇〇 Example 25 Part 1.2 0.5 4γγγ wr /»\\ 〇 - 一〇X Example 26 Part 1.2 0.5 / Frrr ΤΤΓΓ 〇 - 〇X Comparative Example 1 Part 5 <0.01 4γττ τΓΓΓ jw\ X — — X — ※lc/c=Wafer Capacitor ※100 cycles after ※3 500 cycles

-54- 201116186 It can be seen from the results of the evaluation test 1 that, in addition to the deposition portion, the ceramic is formed by firing of a high dielectric material and used as a high dielectric layer, and has a high dielectric constant. As a result, It can suppress the instantaneous decrease of the potential. Further, as a result of the evaluation test 4, it was found that the comparative example could not instantaneously lower the potential of the 1C wafer after the 100-cycle. Although the reason is unknown, however, it is estimated that the bonding between the high dielectric particles is weak, so that cracks are generated therefrom, and the function of the capacitor is lost. Φ In addition, the thermal cycle test was carried out on Example 22 in which a high dielectric sheet forming circuit was applied before being attached to the deposition portion, and the potential transient of the 1C wafer could not be lowered. Although the reason is not clear, it is estimated that the pressure concentration portion at the time of lamination may be cracked due to the heat cycle test. Further, in the examples 25 and 26 in which the stress relieving portion was not provided, the thermal cycle test was carried out, and the potential of the 1C wafer could not be instantaneously lowered. Although the reason is unknown, however, it is estimated that there is no stress relaxation portion, and the stress caused by the difference in thermal expansion coefficient between the 1C wafer and the multilayer printed wiring board causes φ to cause cracking or cracking of the high dielectric layer. The starting point. Since the starting point of the crack occurs due to the thermal cycle test, the particle displacement may cause cracking at this time because the high dielectric layer is repeatedly charged and discharged during the simultaneous switching test. Further, when the electrostatic capacitance immediately below the module is 0.4 // F or less, in the case of the fourth and fifth embodiments, after the evaluation test 2 is performed, the potential of the 1C chip cannot be instantaneously lowered. Although the reason is unknown, it is estimated that the hast test may cause deterioration of the high dielectric layer, and the relative dielectric constant may be lowered to obtain a sufficient decoupling effect. In addition, when the static capacitance directly under the module is 0.5 - 55 - 201116186 / / F or less, after the evaluation test 2 is carried out, the potential of the IC chip cannot be instantaneously lowered. In contrast, the same mode as in the fourth and fifth embodiments is obtained. Embodiments 23 and 24 of the electrostatic capacitance immediately below the group do not cause problems. The reason for this is unknown. However, it is estimated that the potential of the 1C wafer can be instantaneously lowered by performing power supply using the wafer capacitor. Further, after performing the evaluation test 2 on the embodiments 14 and 15 in which the electrostatic capacitance is large, the potential of the 1C wafer cannot be instantaneously lowered. Although the reason is unknown, however, it is estimated that the electrostatic capacitance is large and it is more susceptible to the HAST test, so the dielectric degradation or insulation breakdown occurs in the high dielectric layer. In Examples 12 to 15 in which the electrostatic capacitance was large, the result of the evaluation test 4s5 3 was X. It is inferred that the dielectric displacement occurs during repeated charging and discharging of the dielectric, and the stress accumulated during thermal cycling is added to the stress caused by the displacement, so that the relative dielectric constant of the high dielectric layer is degraded. X. Further, the evaluation test 4 58 3 of Examples 2 to 5, 16 and 17 in which the electrostatic capacitance was relatively small was also X. It is inferred that the thermal cycle test causes the dielectric to expand and contract, so that the relative dielectric constant of the high dielectric layer is degraded and the electrostatic capacitance directly under the module is reduced to X. It can be seen from the results of Table 1 that if the static capacitance directly under the module is 0.8~5 #F, the instantaneous voltage of the transistor corresponding to 1C can be reduced after the environmental test, and the HAST test and the thermal cycle test will not If there is a problem, it has excellent insulation reliability and connection reliability. Further, in all of the embodiments, the first layered electrode is used as the ground and the second layered electrode is used as the power source. However, the reverse may be applied. The multilayer printed wiring board of the present invention can be used to mount a semiconductor device such as a semiconductor chip of a 1C wafer, for example, and can be applied to an electric related industry and a communication-related industry, etc. [FIG. 1] FIG. A plan view of the multilayer printed wiring board 10. Fig. 2 is a longitudinal sectional view of a multilayer printed wiring board (only the left side of the center line is shown). Fig. 3 is a schematic perspective view of the layered capacitor portion 40. Fig. 4 is an explanatory view showing a manufacturing procedure of the multilayer printed wiring board. Fig. 5 is an explanatory view showing a manufacturing procedure of the multilayer printed wiring board 10. Fig. 6 is an explanatory view showing a manufacturing procedure of the multilayer printed wiring board 1 . Fig. 7 is an explanatory view showing a manufacturing procedure of the multilayer printed wiring board 10; Fig. 8 is a longitudinal sectional view showing a multilayer printed wiring board of the second embodiment. Fig. 9 is an explanatory view showing a manufacturing procedure of the multilayer printed wiring board 1 1 . Fig. 1 is an explanatory view showing a manufacturing procedure of the multilayer printed wiring board 110. Fig. 11 is an explanatory view showing a manufacturing procedure of the multilayer printed wiring board 110. Fig. 12 is an explanatory view of a high dielectric sheet 520 having corners. Fig. 13 is a longitudinal sectional view showing a multilayer printed wiring board 210 of the third embodiment. Fig. 14 is a schematic perspective view of the layered capacitor portion 240. Fig. 15 is an explanatory view showing a manufacturing procedure of the multilayer printed wiring board 210. Fig. 16 is an explanatory view showing a manufacturing procedure of the multilayer printed wiring board 210. Fig. 17 is an explanatory view showing a manufacturing procedure of the multilayer printed wiring board 210. Fig. 18 is a description of the manufacturing steps of other multilayer printed wiring boards 2 - 10 - 201116186 [Description of main components] 1 0 : multilayer printed wiring board 2 0 : core substrate 2 1 : core substrate body 2 2 : wiring Pattern 24: through-hole conductor 30: deposition portion 3 2 : wiring pattern 3 4 : via hole 3 6 : resin insulating layer 40 : layered capacitor portion 41 : first layered electrode 4 1 a : through hole 42 : second layer Electrode 4 2 a : through hole 43 : high dielectric layer 60 : mounting portion 6 1 : grounding connection pad 6 1 a : through hole 6 2 a : through hole 6 2 b : through hole 62 : power supply connection Pad 63: Signal connection pad - 58 - 201116186 70 : Wafer capacitor arrangement area 71 : Ground connection pad 72 : Power supply connection pad 7 3 : Wafer capacitor 1 1 0 : Multilayer printed wiring board 1 2 0 : Interlayer insulation layer 140 : layered capacitor portion 141 : first layered electrode 1 4 1 a : through hole 1 4 2 : second layered electrode 1 4 2 a : through hole 143 : high dielectric layer 1 50 : stress relieving portion 1 6 0 : Mounting part 1 6 1 : Grounding connection pad 1 6 1 a : Through hole 1 6 2 a : Through hole 1 6 2 b : Through hole 162 : Power supply connection pad 163 : Signal connection pad 170 : Crystal Capacitor arrangement area 1 7 1 : Ground connection pad 172 : Power supply connection pad 173 : Wafer capacitor - 59 201116186 2 1 0 : Multilayer printed wiring board 2 2 0 : Interlayer insulating layer 240 : Layered capacitor part 241 : 1st layer Electrode 2 4 1 a : through hole 242 : 2nd layered electrode 2 42a : through hole 242b : through hole 243 : high dielectric layer 2 4 5 : interlayer insulating layer 246 : wiring 247 : wiring 2 5 0 : stress Relaxing portion 260: mounting portion 261: grounding connection pad 261x: grounding connection pad 2 6 1 y : grounding connection pad 2 6 1 a : through hole 2 6 1 b : through hole 2 6 2 a : through hole 262b: Through hole 2 6 2 c : Through hole 262 : Power supply connection pad 262x : Power supply connection pad - 60 - 201116186 262y : Power supply connection pad 263 : Signal connection pad 266x : Forming section 266y : Forming section 267x : Forming section 2 6 7 y : forming section 2 6 8 : forming section 270 : wafer capacitor arrangement area 2 7 1 : grounding connection pad 272 : power supply connection pad 2 7 3 : wafer capacitor 4 1 0 : interlayer insulating layer 420 : high dielectric Sheet 422: Copper foil 424: High dielectric layer 426: Upper metal layer 43 0: Dry film 440: Dry film 45 0 : Interlayer filling resin 452 : high dielectric interlayer filling layer 4 5 4 : through hole 456 : electroless copper plating film 460 : dry film 462 : through hole -61 - 201116186 464 : electrolytic copper film 470 : resin insulating sheet 472 : through hole 474 : copper plating film 500 : substrate 5 1 0 : interlayer insulating layer 520 : high dielectric sheet 522 : copper foil 524 : high dielectric layer 526 : copper foil 5 3 0 : through hole 5 3 0a : through hole 5 3 1 : through hole 5 3 1 a : through hole 5 3 2 : through hole filling resin 540 : electroless copper film 541 : plating resist 542 : electrolytic copper plating film 5 4 3 : upper electrode 544 : forming section 5 5 0: stress relaxation sheet 5 6 0 : through hole 5 62 : conductor 6 0 0 : substrate - 62 - 201116186 6 1 0 : interlayer insulating layer 620 : high dielectric sheet 622 : copper foil 624 : high dielectric layer 6 2 6 a : forming section 626 : copper foil 6 2 8 : interlayer insulating layer • 63 0 : through hole 63 2 : enlarged hole 640 : through hole filling resin 6 5 1 : through hole 6 5 2 : through hole 6 5 3: through hole 670: stress relieving sheet 6 8 0 : through hole - 63

Claims (1)

201116186 VII. Patent application scope: 1 . The method for manufacturing a multilayer printed wiring board is a method for manufacturing a multilayer wiring board having a deposition portion, a mounting portion, and a layered capacitor portion; the deposition portion is by the foregoing a through hole in the insulating layer is electrically connected to a plurality of wiring patterns interposed by a resin insulating layer, and the mounting portion is a semiconductor element electrically connected to the wiring pattern. Mounted to the surface: the layered capacitor portion has a ceramic high dielectric layer and first and second layers sandwiching the high dielectric layer between the deposition portion and the mounting portion In the electrode, one of the first and second layered electrodes is connected to the power supply line of the semiconductor element and the other is connected to the ground line; and the method includes: forming a high dielectric on the metal foil as the first layered electrode a thin film of an electroless material, the high dielectric layer is formed by firing the high dielectric material, and a high dielectric layer is formed on the high dielectric layer by forming a metal layer as the second layer electrode Engineering of an electric sheet; preparation of a core substrate on which the above-mentioned deposition portion has been formed; and bonding of the high dielectric sheet to the deposition portion. 2. A method of manufacturing a multilayer printed wiring board for manufacturing a multilayer wiring board including a deposition portion, a mounting portion, and a layered capacitor portion; the deposition portion is formed by a through hole in the insulating layer A wiring pattern in which a plurality of layers are laminated via a resin insulating layer is electrically connected to each other, and is formed on both surfaces of the core substrate: the mounting portion is a semiconductor element electrically connected to the wiring pattern, and is mounted to The layered capacitor portion has a ceramic high-64-201116186 dielectric layer between the deposition portion and the mounting portion, and first and second layers sandwiching the high dielectric layer a layered electrode, wherein one of the first and second layered electrodes is connected to a power supply line of the semiconductor element and the other is connected to a ground line; and the method includes: forming a metal foil as the first layered electrode a thin film of a high dielectric material, wherein the high dielectric layer is formed by firing the high dielectric material, and a high dielectric layer is formed on the high dielectric layer by forming a metal layer as the second layer electrode Engineering of the electro-chemical sheet; φ Preparation of a core substrate on which the deposition portion is formed on both surfaces; and a process of joining the high-dielectric sheet to the surface on the opposite side of the core substrate in the deposition portion. The method for producing a multilayer printed wiring board according to claim 1 or 2, wherein the high dielectric material contains bismuth titanate (BaTi〇3), barium titanate (SrTi03), and oxidation.钽(Ta03,Ta203), lead chromite titanate (PZT), lead zirconate titanate (PLZT), lead zirconate titanate (ΡΝΖΤ), lead zirconate titanate (PCZT), lead bismuth chromite titanate (φ A raw material of one or more metal oxides selected from the group consisting of PSZT). -65-