JP3272831B2 - Multilayer wiring board and semiconductor device using the same - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a multilayer wiring board and a semiconductor device using the same.

[0002]

2. Description of the Related Art In a high-speed system such as a computer or a communication device, it is necessary to shorten the wiring distance as much as possible and mount the device at a high density in order to reduce a signal delay between chips. Conventionally, packages containing semiconductor chips one by one have been individually mounted on a printed circuit board. However, the package size tends to increase with the increase in the degree of integration and the number of pins of semiconductor elements. Then we could not cope.

For example, at present, large packages exceeding 400 pins and 5 cm square have been put to practical use. When such a package is mounted on a printed circuit board, the wiring distance between the chips becomes longer, which causes a wiring delay. Also,
In order to increase the number of accommodated wirings and achieve high-density mounting, it is necessary to miniaturize wirings, but there is a limit in forming fine wirings on a printed circuit board.

Therefore, in recent years, a multi-chip module as shown in FIG. 14 has attracted attention as a wiring board for a high-speed system. In the multi-chip module 30, an organic thin-film multilayer wiring 32 is formed on a surface of a multilayer wiring board 31, and a semiconductor element 33 has bonding wires 34 thereon.
Has been implemented by A heat radiation fin 35 is provided on the rear surface of the multilayer wiring board 31, and a cap 36 and an I / O terminal 37 for hermetic sealing are attached. The multilayer wiring board 31 on which the semiconductor element 33 is mounted is mounted on a printed board 38. As described above, since a plurality of semiconductor elements are mounted on the wiring board close to each other and housed in one package, the size can be significantly reduced as compared with the conventional mounting method.

[0005] As a wiring board of this multi-chip module, a multilayer wiring board using a ceramic material is used. Ceramic materials generally have good insulating properties, and metallization of wiring is easy. Further, since it is excellent in mechanical strength and heat dissipation, and can be attached with leads and pins, it is a useful material as a package material.

An organic thin-film multilayer wiring using a low-dielectric-constant organic polymer material has a small delay due to a high signal propagation speed, and has excellent electrical characteristics as a wiring board for a high-speed system. Since this organic thin-film multilayer wiring is formed by using photolithography technology, it is possible to form fine wiring of several tens μm or less with high precision.

Therefore, if a ceramic multilayer wiring substrate having excellent characteristics as a package material is used as a support and an organic thin film multilayer wiring capable of forming fine wiring and transmitting signals at high speed is formed on the surface thereof, it is ideal. A wiring board for a high-speed system can be realized.

However, wiring boards for high-speed systems,
In particular, in a wiring board where the clock frequency reaches 100 MHz or more, various kinds of noise generated on the transmission line together with the signal delay become a problem. A large noise exceeding the logic level causes a malfunction of the system. Therefore, it is necessary to take measures to minimize the generation of the noise.

The noise includes, for example, reflection noise, crosstalk noise, switching noise, and the like. In recent years, as CMOS (complementary metal oxide semiconductor) devices are frequently used, switching noise has become a problem. The switching noise (ΔV) is expressed as a product of the inductance (L) of the package or the wiring board and the time change (dI / dt) of the current as expressed by the equation (1).

ΔV = L · dI / dt (1) CMOS is easily integrated and has low static power consumption. However, when a plurality of output buffers operate simultaneously,
A large current transiently flows between the power supply and the ground, causing switching noise. Therefore, it is necessary to reduce the inductance of the substrate in order to reduce the switching noise. The inductance is deeply related to the wiring board and the structure, and is, for example, a complex combination of individual inductances of elements constituting a line such as a wiring, a land, and a via, and varies depending on a wiring method.

In order to reduce the inductance of the wiring board, it is desirable to provide as many power supply / ground vias as possible. However, in a conventional multilayer wiring board, a sufficient number of power supply and ground vias are provided for the following reasons. -It was difficult to set up ground vias.

In general, a ceramic substrate shrinks by firing, but it is difficult to completely control the shrinkage, so that the positions of vias on the fired substrate deviate from design values. Therefore, in order to absorb the positional deviation of the via of the ceramic substrate, one having a large correcting electrode is used.
A metallized layer (matching layer) of the layer is provided directly above the ceramic substrate, and the via of the ceramic layer and the via of the thin film layer are connected by this correction electrode.

Since the correction electrode is formed to have a size capable of absorbing the maximum displacement, the interval between the vias is inevitably increased, and the number of vias that can be installed is limited. Also,
A technique of using a capacitor to escape high-frequency components included in switching noise has been used, but has caused other adverse effects.

[0014]

As described above, the conventional multilayer wiring board has a risk of causing switching noise due to large inductance and causing malfunction in a high-speed system. In addition, since a capacitor of a chip component is used to reduce switching noise, there is a problem that a chip mountable area is narrowed.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a multilayer wiring board in which switching noise is suppressed by reducing inductance, and a semiconductor device using the same.

[0016]

In order to solve the above-mentioned problems, the present invention provides a plurality of insulating layers made of a ceramic material.
And a plurality of wiring layers made of a conductive material are alternately laminated.
A multilayer wiring board formed by the method, wherein the wiring layer
Includes a first power supply layer and a second power supply layer via an insulating layer.
A plurality of first vias connected to the first power supply layer;
And a plurality of second vias connected to the second power supply layer.
Reaching at least one of the front and back surfaces of the layer wiring board
Make up a group of vias that are arranged alternately over the entire area of the surface
Between each power layer and the surface of the board where the vias reach
Formed through the existing insulating layer, the vias reach
A correction electrode corresponding to the via is provided on the surface,
The correction electrode is smaller at the center of the substrate than at the periphery of the substrate.
To provide a multilayer wiring board, wherein the decoction.

[0017]

[0018]

In the multilayer wiring board according to the present invention, a group of vias having an interval at the center portion smaller than an interval at the peripheral portion is formed over the entire surface of the substrate. Due to shrinkage of the substrate during firing, the actual finished dimensions slightly deviate from the design values. The ratio between the shift amount and the design dimension is called dimensional accuracy, and the position of the via is also shifted according to the dimensional accuracy. Since the amount of deviation of the via is the product of the distance from the center of the substrate and the dimensional accuracy, the amount of deviation increases as the via is located farther from the center of the substrate.

On the other hand, the thin film layer formed on the surface of the ceramic substrate can be formed with extremely high precision.
The position of the via in the thin film layer is considered to be almost unchanged. As described above, the vias of the ceramic substrate may be misaligned. To electrically connect the vias of the substrate and the vias of the thin film layer, an electrode having a size covering the range of the misalignment is required. Need to be placed. If the thin film layer is designed to match the dimensional accuracy of each ceramic substrate, it is not necessary to form such a large electrode,
It is not a realistic method in terms of economics such as design time and mask cost.

Therefore, when the interval at the central portion of the substrate is reduced as in the present invention, vias can be formed efficiently, and the number of vias can be increased as compared with a conventional multilayer wiring substrate in which vias are arranged at uniform intervals. Power supply vias can be installed. By forming an electrode of an appropriate size corresponding to the via interval formed in this way, it is possible to cover a deviation error and prevent contact between adjacent electrodes. As a result, it is possible to reduce the inductance of the power supply system of the entire substrate and suppress the switching noise.

The via group formed on the substrate surface is alternately connected to the first power supply layer and the second power supply layer. Therefore, it is not necessary to route the wiring in the thin film layer from the power supply layer to the power supply terminal of the chip, and the power supply can be taken out from immediately below the chip for a short distance. That is, the degree of freedom in extracting power from the thin film layer formed on the substrate can be increased, and the thin film layer having various patterns can be easily connected. Therefore, the voltage drop of the power supply is reduced, and a more stable power supply can be provided.

The multilayer wiring board of the present invention can be standardized with the pattern of the multilayer wiring board as a standard, so that the multilayer wiring board can be realized at a lower cost. Further, a first power supply layer and a second power supply layer are provided in the multilayer wiring board of the present invention.
Since the capacitor including the insulating layer is formed during this period, the mounting density on the substrate surface can be improved.

[0023]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below in detail with reference to the drawings. FIG. 1 shows a partially cutaway view of the multilayer wiring board of the present invention. In FIG. 1, a multilayer wiring board 1 includes:
It is made by laminating and sintering a plurality of ceramic sheets on which a wiring pattern is formed by screen printing. As a material of the ceramic sheet, aluminum nitride having high thermal conductivity is used in addition to alumina and the like.

On the multilayer wiring board 1, a first power supply layer 2 and a second power supply layer 3 are provided via an insulating layer 5.
The power supply layer 2 and the power supply layer 3 serve as a reference plane for power supply and constitute a capacitor using the insulating layer 5 interposed therebetween as a dielectric material, and thus can be used as a decoupling capacitor.

In general, the capacitance C of a parallel plate capacitor
(F) shows the electrode area S (cm ² ) and the dielectric thickness d (c)
m) and the dielectric constant ε are expressed as in equation (2). C = ε · S / 3.6π · d × 10 ⁻¹² (2) From equation (2), it can be seen that the capacitance of the capacitor can be increased by decreasing the distance between the layers and increasing the facing area. . Therefore, it is preferable that the power supply layer 2 and the power supply layer 3 have a solid surface so that an effective facing area can be obtained.

For example, the insulator is made of aluminum nitride (ε =
When 9.0) is used, the distance between the layers is 100 μm, and the facing area is 64 cm ² , a capacitance of about 5000 pF can be obtained.

Since the multilayer wiring board of the present invention incorporates the capacitor inside the board as described above, the mounting area of the chip can be increased as compared with the case where the conventional chip capacitor is mounted on the printed board. The mounting density is improved.

It is preferable that the insulating layer 5 be formed thinner than the other insulating layers 4 and 6, because the capacity of the capacitor can be increased and the thickness of the entire substrate can be maintained to maintain the substrate strength. Further, as a material of the insulating layer 5,
Even if a material having a higher dielectric constant than other insulating layers is used, the capacitance of the capacitor can be increased.

The first power supply layer 2 and the second power supply layer 3 are formed with vias 7a and 7b which are electrically connected to each other and penetrate through the insulating layer to reach the substrate surface. I have.

An organic thin-film multilayer wiring can be formed on the front surface of the multilayer wiring board 1, and external I / Os can be formed from the rear surface.
When O is extracted from the back surface, a thin metallized layer is formed as an electrode of the I / O lead. Since flatness of the substrate is required in order to form a high-precision and high-quality thin film pattern, it is preferable to polish the surface of the multilayer wiring substrate 1 or both the front and back surfaces.

When a thin film layer is formed, a matching layer (not shown) for electrically connecting the ceramic layer and the thin film layer is formed immediately above the surface of the multilayer wiring board 1. In this matching layer, the vias of the ceramic layer and the vias of the thin film layer are connected by electrodes placed at positions corresponding to the vias of the ceramic layer, and further connected to the electrode terminals of the chip.

FIG. 2 is a plan view of the multilayer wiring board 1 of the present invention. Vias reaching the substrate surface from the first and second power supply layers form a via group 7. As shown in FIG. 2, the via groups at the substrate central portion 1a are arranged in a lattice at smaller intervals than the via groups at the substrate peripheral portion 1b. The interval between the via groups can be appropriately selected according to the degree of shrinkage of the ceramic sheet during sintering, and can be determined as follows, for example.

Generally, the minimum via interval Pv that can be set is:
It is obtained from equation (3). Pv = Ls + D + k · x (3) where Ls is a space between electrodes, D is a via diameter, k is dimensional accuracy, and x is a distance from the center of the substrate. For example, on a substrate having one side of (2 × Lsub), the via group at the center is arranged at the via interval Pv1, and the via group at the peripheral portion is arranged at the via interval Pv1.
When arranged in v2, the distance x from the substrate center and the via interval Pv are represented as shown in FIG. FIG. 4 shows a plan view of a substrate on which vias are arranged at such intervals.

As shown in FIG. 4, the difference between the number of vias when a group of vias is installed on the substrate and the number of vias when the vias are installed at a constant pitch in accordance with the conventional outermost via is ΔN.
ΔN is represented by equation (4).

ΔN = (2 × / Pv1) ² − (2 × / Pv2) ² (4) Here, Pv1 = Ls + D + k × Pv2 = Ls + D + k × Lsub.

FIG. 3 (b) shows the relationship of equation (4). As shown in FIG. 3B, since .DELTA.N takes the maximum value at x = x1, the number of vias can be maximized by changing the via interval at this distance. That is, the via interval may be determined based on x1 determined as described above.

The arrangement of the via groups is not limited to this, and may be formed as shown in FIG. 5 and FIG. FIG. 5 shows an example of a multi-layer wiring board in which vias 7 are formed in a grid pattern with continuously changing intervals. FIG. 6 shows a case where the vias are radially arranged so that the interval increases continuously from the center to the periphery of the substrate. By forming in this way, a larger number of vias 7 can be provided, so that the inductance of the substrate can be further reduced. In addition, even when the interval of the via is continuously changed,
The distance from the center can be determined as described above.

FIG. 7 shows a case where one multilayer wiring board of the present invention is cut into a plurality of pieces 8 and used.
Even where the vias can be installed, there may be areas where no vias are placed or where no vias are placed as necessary. As shown in FIG. 7, in some cases, it is preferable that no via is provided at a margin at the time of dicing.

The multilayer wiring board of the present invention may have three or more power supply layers as shown in FIG. By increasing the number of power supply layers, the area of the opposing electrodes can be increased, so that the capacitance of the capacitor can be increased. Further, even when the power supply of the chip requires more than two power supplies, the required number of power supply layers can be provided.

FIG. 9 shows the structure of a multilayer wiring board in which a multilayer wiring board and an organic thin-film multilayer wiring are combined. On the surface of the multilayer wiring board 1, an organic thin film multilayer wiring 10 formed by sequentially laminating an organic polymer insulating material such as polyimide and a conductive material such as copper is formed. The organic thin-film multilayer wiring 10 is mainly used for connection between chips that require high-speed signal transmission.

FIG. 10 shows another example in which a multilayer wiring board and an organic thin film multilayer wiring are combined. In the multilayer wiring board 1, a via 11 which is connected to each of the power supply layers 2 and 3 and reaches the front surface of the substrate, and a via 12 which penetrates from the back surface to the front surface without being electrically connected to each power supply layer is formed. Have been. The via 11 is connected to a power supply outside the substrate to supply power to each of the power supply layers in the substrate, and is also connected to the power supply layer of the thin film layer. On the other hand, the via 12 is connected to a signal line outside the substrate and connected to a signal wiring of a thin film layer.

Further, vias (not shown) which are electrically connected to the respective power supply layers may be provided near the vias 12. By forming a via connected to an arbitrary power supply layer, the via 12 can be used freely according to the purpose in the thin film layer. For example, it may be used as a signal line, or may be connected to a power supply layer with a matching layer or a thin film layer and used for power supply reinforcement.

FIG. 11 is a sectional view showing an example of the semiconductor device of the present invention. As shown in FIG. 11, a plurality of semiconductor elements 14 can be mounted on the organic thin-film multilayer wiring 10 formed on the surface of the above-described multilayer wiring board 1 via the bumps 15 by a flip-chip method. Furthermore, it is air-tightly sealed with a cap 16, and an I / O terminal 17 is attached.
The semiconductor device 18 of the present invention is obtained. Also, as shown in FIG.
The semiconductor device 20 of the present invention can also be obtained by airtight sealing with the cap 16 and attaching the I / O terminal 17 in the same manner except that the semiconductor device 4 is mounted on the organic thin film multilayer wiring 10.

As shown in FIGS. 11 and 12, the spacing between the vias in the multilayer wiring board 1 of the present invention is provided to be smaller at the center than at the periphery. Therefore, the via can be efficiently formed on the entire surface of the substrate, and the inductance can be reduced.

Next, the present invention will be described in more detail with reference to specific examples of the present invention. The present invention was applied by considering the shrinkage ratio during firing of a ceramic substrate having a side of 100 mm with a via having a size of 0.2 mm formed thereon. Normal,
Dimensional accuracy on ceramic substrate is ± 0.3 to 1.0%
Therefore, in the case of this substrate, the outermost via located at 50 mm from the center of the substrate is shifted by about ± 0.5 mm at the maximum. Therefore, in consideration of the size of the via and the like, the size of the electrode needs to be about 1.2 mm.
Further, when it is considered that the distance between the electrodes is 0.3 mm, the distance between the vias that can be arranged at the outermost line is 1.5 mm at a minimum. On the other hand, a similar calculation for vias located at a distance of 25 mm from the center of the substrate shows that the vias can be arranged at 1.0 mm intervals.

Therefore, vias are arranged at an interval of 1.0 mm up to a distance of 25 mm from the center of the substrate, and vias are arranged at an interval of 1.5 mm outside the center. And FIG. 13 shows a cross-sectional view of the multilayer wiring board of the present invention on which electrodes are formed. Note that FIG.
2 also shows a plan view of the electrodes. As shown in FIG. 13, in the ceramic substrate 1 having the power supply layers 2 and 3, the via displacement during sintering is represented by D ₁ and D ₂ at the substrate center 1a and the substrate peripheral 1b, respectively. The positional deviation in consideration of the interval L ₁ via 12a at the central portion 1a is arranged to be smaller than the distance L ₂ of the via 12b in the peripheral portion 1b. Note that electrodes 13a and 13b whose sizes are determined in consideration of the respective positional deviations are formed in the central via 12a and the peripheral via 12b.

When the vias are arranged as described above, the number of vias that can be formed on the above-described substrate is about 5,700. In the conventional substrate in which vias are arranged at a constant interval of 1.5 mm, the number of vias that can be formed is about 4400. Therefore, by applying the present invention, the number of vias that can be formed is about It turns out that it increased about 30%. Furthermore, the wiring board of the present invention is more effective because the larger the board size, the more the number of vias that can be installed can be increased.

In general, a chip having a large current consumption is:
It is often mounted in the center of the board, but by using the board of the present invention, power is supplied to the chip at a closer distance from the power supply via densely formed in the center and through more vias can do. Therefore, in this case, not only the inductance can be reduced, but also the voltage drop can be reduced.

[0049]

As described above, according to the present invention,
Since a wiring board having a small inductance can be provided, generation of switching noise can be suppressed. Also,
Since the capacitor is formed in the wiring board, a multilayer wiring board with an improved mounting density can be obtained.

[Brief description of the drawings]

FIG. 1 is a perspective view showing an example of a multilayer wiring board of the present invention.

FIG. 2 is a plan view showing an example of the multilayer wiring board of the present invention.

FIG. 3 is a diagram showing a relationship between a distance from a substrate center and a via interval, and a relationship between a distance from the substrate center and a difference in the number of vias.

FIG. 4 is a plan view showing an example of an arrangement of vias in the multilayer wiring board of the present invention.

FIG. 5 is a plan view showing another example of the multilayer wiring board of the present invention.

FIG. 6 is a plan view showing another example of the multilayer wiring board of the present invention.

FIG. 7 is a plan view showing another example of the multilayer wiring board of the present invention.

FIG. 8 is a sectional view showing another example of the multilayer wiring board of the present invention.

FIG. 9 is a perspective view showing another example of the multilayer wiring board of the present invention.

FIG. 10 is a sectional view showing another example of the multilayer wiring board of the present invention.

FIG. 11 is a cross-sectional view illustrating an example of a semiconductor device of the present invention.

FIG. 12 is a sectional view showing another example of the semiconductor device of the present invention.

FIG. 13 is a sectional view showing an example of the multilayer wiring board of the present invention.

FIG. 14 is a sectional view showing a conventional multichip module.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Multilayer wiring board, 2 ... Power supply layer, 3 ... Power supply layer, 4 ... Insulating layer, 5 ... Insulating layer 6 ... Insulating layer, 7 ... Via, 8 ... Fragment of multilayer wiring board, 9 ...
Multilayer wiring board 10: Organic thin film multilayer wiring, 11: Via, 12: Via, 1
3 ... electrode 14 ... semiconductor element, 15 ... bump, 16 ... cap, 1
Reference Signs List 7 I / O terminal 18 Semiconductor device 19 Semiconductor device 20 Semiconductor device 30 Multi-chip module 31 Multi-layer wiring board 32 Organic thin-film multilayer wiring 33 Semiconductor device 34 Bonding wire 35 Heat radiation Fins, 36 caps, 37 I / O terminals, 38 printed circuit boards.

──────────────────────────────────────────────────続 き Continuation of the front page (72) Inventor Hiromi Fuchida 1 Toshiba-cho, Komukai, Koyuki-ku, Kawasaki-shi, Kanagawa Prefecture Toshiba R & D Center Co., Ltd. (56) References JP-A-4-64281 (JP, A) JP-A-63-257255 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) H01L 23/12 H05K 3/46

Claims (2)

(57) [Claims] A plurality of insulating layers made of a ceramic material
And a plurality of wiring layers made of a conductive material are alternately laminated.
A multilayer wiring board formed by the method, wherein the wiring layer
Includes a first power supply layer and a second power supply layer via an insulating layer.
A plurality of first vias connected to the first power supply layer;
And a plurality of second vias connected to the second power supply layer.
Reaching at least one of the front and back surfaces of the layer wiring board
Make up a group of vias that are arranged alternately over the entire area of the surface
Between each power layer and the surface of the board where the vias reach
Formed through the existing insulating layer, the vias reach
A correction electrode corresponding to the via is provided on the surface,
The correction electrode is smaller at the center of the substrate than at the periphery of the substrate.
Multi-layer wiring board, wherein the decoction. 2. The method according to claim 1, wherein the via group is located at a central portion of the substrate.
The density of the via group is higher than the density of the via group at the periphery of the board.
2. The multilayer wiring board according to claim 1, wherein the wiring board is large .