JPS62118549A - Low capacitance package - Google Patents
Low capacitance packageInfo
- Publication number
- JPS62118549A JPS62118549A JP25906685A JP25906685A JPS62118549A JP S62118549 A JPS62118549 A JP S62118549A JP 25906685 A JP25906685 A JP 25906685A JP 25906685 A JP25906685 A JP 25906685A JP S62118549 A JPS62118549 A JP S62118549A
- Authority
- JP
- Japan
- Prior art keywords
- substrate
- insulating layer
- dielectric constant
- layer
- silicon carbide
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
- H01L23/64—Impedance arrangements
- H01L23/642—Capacitive arrangements
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/161—Cap
- H01L2924/1615—Shape
- H01L2924/16152—Cap comprising a cavity for hosting the device, e.g. U-shaped cap
Abstract
Description
【発明の詳細な説明】
〔概要〕
高密度フリップチップ素子等の素子と熱膨張差の少ない
シリコンカーバイト基板に、導体メタライズ層と絶縁層
を重層し、その上に素子搭載用のパターンと基板内接Ｉ
ＶＩＡを形成して低容量パッケージを可能にする。[Detailed Description of the Invention] [Summary] A conductive metallized layer and an insulating layer are layered on a silicon carbide substrate, which has a small difference in thermal expansion from devices such as high-density flip chip devices, and a pattern for mounting the device and a substrate are formed on top of the silicon carbide substrate. Inscribed I
Forming VIAs to enable low capacitance packaging.
本発明は素子を搭載するパッケージの基板に関するもの
である。The present invention relates to a substrate for a package on which elements are mounted.
特に高密度化のフリップチップ素子を搭載するパッケー
ジにおいて、熱膨張差の少ない基板を使用した低容量パ
ッケージが要求されている。In particular, in packages mounting high-density flip-chip elements, there is a demand for low-capacity packages that use substrates with little difference in thermal expansion.
従来、高密度のフリップチップ素子１を搭載した低容量
パンケージは第２図に示すように、高密度素子と熱膨張
差が大きいアルミナセラミックの基板２°の基板内接続
ＶＩＡ５１を設け、表面に入出力端子接続バッド５３と
回路パターン（図示せず）を形成し、バンプ半田５２で
前記高密度フリップチップ素子１を実装しキャップ６で
密封した構造となっている。Conventionally, as shown in Fig. 2, a low-capacity pancage equipped with a high-density flip-chip device 1 is provided with an in-substrate connection VIA 51 of 2 degrees to the substrate made of alumina ceramic, which has a large thermal expansion difference with the high-density device. It has a structure in which an output terminal connection pad 53 and a circuit pattern (not shown) are formed, the high-density flip chip element 1 is mounted with bump solder 52, and the cap 6 is sealed.
以−１−説明の従来の低容量パッケージで問題となるの
は、フリップチップ素子が更に高密度化、大型多端子化
すると、素子とアルミナセラミックの基板との熱１１ｔ
、ｌ張差が大きくなり、基板との接続信頼度が悪くなる
。The problem with the conventional low-capacity package described below in 1-1 is that as flip-chip devices become more dense and have larger numbers of terminals, the heat generated between the device and the alumina ceramic substrate increases by 11 tons.
, l The tension difference increases, and the reliability of the connection with the board deteriorates.
又、素子と熱膨張差が少ないシリコンカーバイトを基板
に使用した場合、その誘電率はアルミナセラミックに対
し４倍以−１−も高く基板配線パターン及び、基板内接
続ＶＩＡの各容量も約４倍となり、この面密度の超高速
素子を使用した装置においては容置増加によりパンケー
ジ単体のディレィが大と４「るか、信号の反射が大きく
なる。In addition, when silicon carbide, which has a small difference in thermal expansion from the element, is used for the substrate, its dielectric constant is more than 4 times higher than that of alumina ceramic, and the capacitance of the substrate wiring pattern and the vias connected within the substrate are also approximately 4 In a device using ultra-high-speed elements with this areal density, the delay of a single pancage increases by 4' due to the increase in capacity, or the signal reflection increases.
本発明は１）１１−のような状況から素子との熱膨張差
が少なく、１１つパッケージの容量が低い基板構造を有
し２だ低容量パッケージの擢供を目的としたものである
。The present invention aims to provide a low capacitance package having a substrate structure with a small difference in thermal expansion from the element and a low capacitance of the package due to the situation 1) 11-.
ｈ記問題点は、第１図に示すようにシリコンカーバイト
製基板２の基板内接続ＶＩＡ５１（以下ＶＩＡと云う）
の穴を加工後、前記基板２の所定表面に導体メタうイズ
層３を施工し、更にその上に低誘電率の絶縁層４を薄く
重層してＶ Ｉ Ａ５１を設け、前記絶縁層４の表面に
フリップチップ素子１（以下素子と云う）の接続用入出
力端子接続パッド５３と回路パターン（図示せず）とを
形成した基板２を使用する、本発明の低容量パッケージ
により解決される。The problem in item h is the internal connection VIA 51 (hereinafter referred to as VIA) of the silicon carbide substrate 2, as shown in FIG.
After drilling the hole, a conductive metallization layer 3 is formed on a predetermined surface of the substrate 2, and a thin insulating layer 4 with a low dielectric constant is layered thereon to provide a VIA 51, and the insulating layer 4 is This problem is solved by the low capacitance package of the present invention, which uses a substrate 2 on which are formed an input/output terminal connection pad 53 for connecting a flip chip element 1 (hereinafter referred to as an element) and a circuit pattern (not shown).
即ら本発明においてはシリコンカーバイト製基板２に、
十記高誘電率の導体メタライズ層３と低誘電率の絶縁層
４を重層することによりシリコンカーバイト全体が導体
メタライズ層３によ１体と見做ずことができ、絶縁層４
の一■−に形成した回路パターン（図示−Ｕず）とＶＩ
Ａ５１の容量は絶縁層４の低誘電率の４．４１’ｌによ
って決定され、シリコーンセラミック自体の高誘電率に
は関係なく低容量となる。That is, in the present invention, on the silicon carbide substrate 2,
By overlaying the conductive metallized layer 3 with a high dielectric constant and the insulating layer 4 with a low dielectric constant, the entire silicon carbide can be regarded as one body with the conductive metallized layer 3, and the insulating layer 4
The circuit pattern (shown in the diagram) formed on one part of the diagram and the VI
The capacitance of A51 is determined by the low dielectric constant of 4.41'l of the insulating layer 4, and has a low capacitance regardless of the high dielectric constant of the silicone ceramic itself.
又、素子１の実装及び、稼動時間順となる基板２との熱
膨張差は、導体メタライズ層３と絶縁層４の被膜層が薄
いため、素子１と熱膨張差の少ないシリコンカーバイｉ
・基板２の熱膨張率に左右され、素子１と基板２とのハ
ンプ半［ｎ５２の信頼度向上が可能となる。In addition, the difference in thermal expansion between the element 1 and the substrate 2 in order of mounting and operating time is due to the thin film layers of the conductor metallized layer 3 and the insulating layer 4.
- Depending on the coefficient of thermal expansion of the substrate 2, it is possible to improve the reliability of the hump half [n52] between the element 1 and the substrate 2.
以下図面にもとづいて本発明の一実施例を説明する。 An embodiment of the present invention will be described below based on the drawings.
第１図は本実施例による低容量パッケージの断面図を示
す。FIG. 1 shows a sectional view of a low capacity package according to this embodiment.
シリコンカーバイトで出来た所定外観寸法の４角形で平
行な表裏平面を有する回路基板２のＶＩＡ５１の位置即
ち、素子１の電極に一致した位置に所定の大きざの穴を
例えば、レーザビーム加工で多数穿孔し、専用治具を使
用して表裏両面の回路パターン（図示せず）とＶＩＡ５
１の形成に必要な部分の表面と、前記ＶＩＡ５１を形成
する穴の内側に対し導体メタライズ層３例えば、銅を４
〜６ミクロンの厚みに真空蒸着により蒸着する。A hole of a predetermined size is formed, for example, by laser beam machining, at the position of the VIA 51 of the circuit board 2, which is made of silicon carbide and has a rectangular shape with a predetermined external dimension and has parallel front and back planes, that is, at a position corresponding to the electrode of the element 1. A large number of holes are drilled, and a circuit pattern (not shown) on both the front and back sides and VIA5 are formed using a special jig.
A conductive metallized layer 3, for example, copper 4, is applied to the surface of the portion necessary for forming the VIA 51 and the inside of the hole where the VIA 51 is formed.
Deposited by vacuum evaporation to a thickness of ~6 microns.
つづいて前記必要部分以外の場所を塗布専用冶具を用い
てマスキングし、前記導体メタライズ層３を施工した表
面及び、多数の穴内面を、低誘電率で高ｉＪ熱性を有す
る絶縁層４例えば、４０〜６０ミクロン程度の膜をポリ
イミド系の樹脂の電着塗布焼き付は又は、酸化シリコン
系ガラスを蒸着で密着する。Next, areas other than the necessary areas are masked using a special coating jig, and the surface on which the conductive metallized layer 3 has been applied and the inner surfaces of the numerous holes are coated with an insulating layer 4 having a low dielectric constant and high iJ thermal properties, for example, 40 A film of about 60 microns is adhered by electrodeposition and baking of polyimide resin, or by vapor deposition of silicon oxide glass.
以上の絶縁層４の被膜生成を完了した部分に無電解メッ
キにより数ミクロンの銅メッキを施し、更に電解メッキ
により数十ミクロンの銅メッキを施してその上にエツチ
ングレジストを塗布し、それに所要パターンを焼き付け
、ホトエツチングにより前記回路パターンと入出力端子
接続パッド５３及び、ＶＩＡ５１を有したシリコンカー
バイトの基板２を形成する。Copper plating of several microns is applied by electroless plating on the part where the film formation of the insulating layer 4 has been completed, followed by copper plating of several tens of microns by electrolytic plating, an etching resist is applied thereon, and the required pattern is applied. A silicon carbide substrate 2 having the circuit pattern, input/output terminal connection pads 53, and vias 51 is formed by baking and photoetching.
上記説明のシリコンカーバイト基板２の入出力端子接続
パッド５３の上に素子１をポンディング治具で位置決め
し、前記素子１の電極に具備された半田をベルト・リフ
ロー炉により再溶融して実装を行った後キャップ６で封
止する。The element 1 is positioned on the input/output terminal connection pad 53 of the silicon carbide substrate 2 described above using a pounding jig, and the solder provided on the electrodes of the element 1 is remelted in a belt reflow oven and mounted. After doing this, it is sealed with a cap 6.
以」二により素子１の発熱に対し接続の信頼度が高い低
容量パッケージが得られる。As a result of the above, a low capacitance package with high connection reliability against heat generation of the element 1 can be obtained.
尚、素−７−１はフリップチップ素子だ番ノでなくワイ
ヤボンド、ＴＡＢ方式の素子にも適用される。Note that element-7-1 is applicable not only to flip-chip devices but also to wire-bond and TAB type devices.
以上説明したよ・うに本発明によれば極めて簡単な構造
の基板で、１ｒ１１密度素了搭載の１？続信頼度の向上
および、パンケージが低容量となる等著しい品質的の効
果が期待でき実用的には極めて有用である。As explained above, according to the present invention, the board has an extremely simple structure and is equipped with 1r11 density. It is expected to have significant quality effects such as improved connection reliability and reduced capacity of the pancage, and is extremely useful in practice.
第１図は本発明の一実施例による低容鼠パソゲージを示
す図、
第２図は従来の低容量バノノノ°−ジを示す図である。
図において、
１はフリップチップ素子、
２．２゛は基手反、
３は導体メタライズ層、
４は絶縁層、
５１は基１反内接続ＶＩＡ、
５２４；ｔバンプ半田、
５３１Ｊ入出力端子接続バンド、
〔ｊは−１−ヤソプ、
を示ず。FIG. 1 is a view showing a low volume mouse gauge according to an embodiment of the present invention, and FIG. 2 is a view showing a conventional low capacity mouse gauge. In the figure, 1 is a flip chip element, 2.2 is a base plate, 3 is a conductor metallized layer, 4 is an insulating layer, 51 is a base 1 inner connection VIA, 524 is a t-bump solder, 531 is an input/output terminal connection band , [j is -1-Yasop, does not indicate.
Claims (1)
に高誘電率の導体メタライズ層（３）と低誘電率の絶縁
層（４）を重層し、前記絶縁層（４）の上に該高密度素
子（１）の搭載用回路パターンと、基板内接ＶＩＡ（５
１）を形成した基板（２）を備えてなることを特徴とす
る低容量パッケージ。In a package in which a high-density element (1) is mounted, a high-permittivity conductive metallized layer (3) and a low-permittivity insulating layer (4) are layered on the surface, and the high-density Circuit pattern for mounting element (1) and VIA (5
A low-capacity package characterized by comprising a substrate (2) on which 1) is formed.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP25906685A JPS62118549A (en) | 1985-11-18 | 1985-11-18 | Low capacitance package |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP25906685A JPS62118549A (en) | 1985-11-18 | 1985-11-18 | Low capacitance package |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS62118549A true JPS62118549A (en) | 1987-05-29 |
Family
ID=17328847
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP25906685A Pending JPS62118549A (en) | 1985-11-18 | 1985-11-18 | Low capacitance package |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS62118549A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100253335B1 (en) * | 1997-10-20 | 2000-04-15 | 김영환 | Micro ball grid array package and manufacturing method thereof |
-
1985
- 1985-11-18 JP JP25906685A patent/JPS62118549A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100253335B1 (en) * | 1997-10-20 | 2000-04-15 | 김영환 | Micro ball grid array package and manufacturing method thereof |
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