JP2006049427A - Method for manufacturing semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a highly reliable semiconductor device wherein any space can be prevented from being produced between a ball base film and a passivation film in a flip-chip ball grid array. <P>SOLUTION: A barrier metal 112 is dry-etched by using an etching gas containing carbon and halogen gases such as fluorine or the like. Therefore, the surface of the barrier metal 112 becomes uneven, which can increase the roughness of the surface and improve the adhesive force between the barrier metal 112 and a polyimide film 105. As a result, the generation of side etching can be prevented during wet-etching of the barrier metal 112, and any space can be prevented from being produced between a UBM 104 and the polyimide film 105. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a method for manufacturing a semiconductor device.

  In response to recent demands for miniaturization of LSIs, the solder balls are fixed to a plurality of electrode pads on the LSI, and the solder balls are directly connected to the electrodes of the corresponding wiring board, thereby electrically connecting the LSI to the wiring board. Flip chip ball grid arrays that are mechanically coupled are also known.

JP 2003-45877 A

  However, the prior art described in the above literature has room for improvement in the following points.

  In the case of a flip chip structure, there is an interface between a metal UBM (Under Bump Metal / Under Ball Metal), which is an interface with relatively low adhesion, and a resin such as polyimide. In the conventional manufacturing process, when the uppermost barrier metal is removed by wet etching, a space may be generated between a resin such as polyimide and UBM due to side etching of wet etching. Here, the side etching means that the barrier metal is eroded from the exposed surface of the uppermost barrier metal. The side-etched space becomes the starting point of the stress center when a reliability test such as a temperature cycle test is performed, and the stress sometimes concentrates near the opening of a resin such as polyimide. Therefore, there remains room for improvement in that cracks are generated in the bump starting from the stress concentration point.

  According to the present invention, a semiconductor device including an electrode pad including a first barrier film, a ball base film, and a second barrier film formed on a semiconductor substrate, and a bump formed on the electrode pad is manufactured. A method of sequentially forming an insulating film and a protective film on a semiconductor substrate; a step of forming a first opening penetrating the insulating film and the protective film; and a surface along the first opening; Forming a first barrier film on the protective film, forming a ball base film on the first barrier film, forming a second barrier film on the ball base film, and forming a second barrier film on the second barrier film A step of performing a surface treatment, a step of forming a passivation film on the second barrier film, a step of selectively removing the passivation film to form a second opening, and a second barrier film subjected to the surface treatment Selectively removing the ball underlayer to expose the ball underlayer; The method of manufacturing a semiconductor device which comprises a step of forming a bump in contact with the issued balls base film and a side surface facing the second opening of the passivation film is provided.

  According to the present invention, the surface treatment is performed on the second barrier film to change the composition of the second barrier film surface, and the roughness of the second barrier film surface is improved to improve the second barrier film and the passivation film. The adhesion between the two can be improved. For this reason, it can suppress that a space arises between a ball | bowl base film and a passivation film. Therefore, a highly reliable semiconductor device can be provided.

  According to the present invention, a highly reliable semiconductor device is provided.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. In all the drawings, the same reference numerals are given to the same components, and the description will be omitted as appropriate.

  FIG. 1 shows the structure of a semiconductor device 100 according to this embodiment.

  The semiconductor device 100 includes a semiconductor substrate 120, a metal wiring layer 101 formed on the semiconductor substrate 120, an insulating film 102 covering the metal wiring layer 101, a protective film 103 covering the insulating film 102, and a metal wiring layer 101 in contact with the metal wiring layer 101. A first barrier metal 110 that is a first barrier film, a UBM 104 that is a ball base film formed on the first barrier metal 110, a second barrier metal 112 that is a second barrier film formed on the UBM 104, and a passivation film It has a polyimide film 105 having a function and a bump 106 that is in contact with the UBM 104 and is used for electrical connection with the outside.

  The metal wiring layer 101 is made of aluminum or the like, and is formed on the semiconductor substrate 120 by a sputtering method or the like.

The insulating film 102 is composed of a SiO ₂ film or the like and has a function of insulating the metal wiring layer 101.

  The protective film 103 is composed of a SiON film or the like and has a function of protecting the insulating film 102.

  The UBM 104 is made of Cu, Ni, or the like, and is electrically connected to the metal wiring layer 101 through the first barrier metal 110.

  The first barrier metal 110 is made of TiW and has a function of suppressing diffusion of metal components from the UBM 104 to the metal wiring layer 101.

  In the present embodiment, the second barrier metal 112 is made of TiW or the like, and has a function of suppressing diffusion of metal components from the UBM 104 to the polyimide film 105.

  The surface of the second barrier metal 112 is subjected to dry etching using an etching gas containing carbon and a halogen gas such as fluorine, whereby uneven portions are generated. For this reason, the surface roughness of the second barrier metal 112 is increased, and the adhesion between the second barrier metal 112 and the polyimide film 105 can be improved. Further, the composition ratio of tungsten in the component composition near the surface of the second barrier metal 112 is about 2/3 or less as compared with the conventional barrier metal. Furthermore, the surface of the second barrier metal 112 is oxidized by performing plasma processing using oxygen plasma. Therefore, the adhesion between the second barrier metal 112 and the polyimide film 105 can be improved.

  The bump 106 is made of lead-free solder or the like and is used for electrical connection with the outside.

  Hereinafter, the manufacturing process of the semiconductor device 100 will be described with reference to FIGS.

First, a metal layer made of aluminum or the like is formed on a semiconductor substrate (not shown) using a sputtering method or the like, and the metal wiring layer 101 that is the uppermost layer wiring is formed by etching using a photolithography technique. Next, the SiO ₂ film 122 and the SiON film 124 are formed in this order from the bottom using the CVD method or the like (FIG. 2A).

Next, the SiO ₂ film 122 and the SiON film 124 are etched using a photolithography technique, and the insulating film 102 and the protective film 103 are sequentially formed on a semiconductor substrate (not shown). Next, a via hole 126 that is a first opening penetrating the insulating film 102 and the protective film 103 is formed to expose the metal wiring layer 101 (FIG. 2B).

  Next, the first barrier metal 110 is formed on the surface along the via hole 126 that is the first opening and on the protective film 103 by film formation by sputtering or the like. Subsequently, the UBM 104 that is a ball base film is formed on the first barrier metal 110 by using an electrolytic plating technique or the like. Further, the second barrier metal 112 is formed on the UBM 104 by sputtering or the like (FIG. 2C).

  Next, a roughening process is performed on the second barrier metal 112 as a surface treatment. Here, as the surface treatment (roughening treatment), for example, the second barrier metal 112 can be dry-etched using an etching gas containing carbon and a halogen gas such as fluorine. In addition, oxygen plasma treatment or the like can be performed (FIG. 2D). By performing a dry etching process as a surface treatment (roughening process), the number of irregularities on the surface of the second barrier metal 112 increases, so that the surface roughness increases by about 3 to 5 nm. Therefore, the adhesion between the UBM 104 and the polyimide film 105 is improved. Further, in the composition of the second barrier metal 112, the composition ratio of tungsten is reduced to about 2/3 and the composition ratio of titanium is increased about twice as compared with the conventional barrier metal. Furthermore, as a surface treatment (roughening treatment), by performing oxygen plasma treatment, the titanium component increased by the above-described dry etching treatment is oxidized, thereby increasing the contact angle of the titanium component. Therefore, the adhesion between the UBM 104 and the polyimide film 105 is improved. Further, the oxidation degree of titanium and tungsten is increased by about 2.5 times, and the composition ratio of oxygen is increased by about 1.5 times.

  Next, a polyimide film 105 as a passivation film is formed on the second barrier metal. That is, the photosensitive polyimide film 105 that is a passivation film is formed so as to cover the outer edge portion of the second barrier metal 112 and the exposed surfaces of the UBM 104, the first barrier metal 110, and the protective film 103. Next, the polyimide film 105 is selectively removed by exposing and developing a predetermined pattern on the polyimide film 105. That is, a second opening 128 having a predetermined size is formed in a predetermined portion of the polyimide film 105, and the central portion of the second barrier metal 112 is exposed from the second opening 128 (FIG. 3A).

  Next, the exposed central portion of the second barrier metal 112 is selectively removed using wet etching or the like to expose the UBM 104 (FIG. 3B).

  Next, the bump 106 is formed in the second opening 128. At this time, the bump 106 is formed so as to be in contact with the side wall and upper surface of the UBM 104, the side wall of the second barrier metal 112, and the side surface of the polyimide film 105 facing the second opening 128 (FIG. 3C). ).

  The semiconductor device 100 is formed by the above process.

  Hereinafter, effects of the method for manufacturing the semiconductor device 100 will be described.

  In the manufacturing process of the semiconductor device 100 according to the present embodiment, dry etching is performed on the second barrier metal 112 using an etching gas containing carbon and a halogen gas such as fluorine. For this reason, the number of uneven portions on the surface of the second barrier metal 112 increases. Accordingly, the surface roughness is increased and the adhesion between the second barrier metal 112 and the polyimide film 105 can be improved. As a result, generation of side etching when the second barrier metal 112 is wet-etched can be suppressed, and generation of a space between the UBM 104 and the polyimide film 105 can be suppressed.

  In the present embodiment, as the surface treatment (roughening treatment), oxygen plasma treatment is performed on the second barrier metal 112 together with the dry etching treatment. Here, by the dry etching process described above, the composition ratio of tungsten in the vicinity of the surface layer of the second barrier metal 112 is reduced by about 2/3, and the composition ratio of titanium is increased approximately twice. Therefore, by performing oxygen plasma treatment after the dry etching process, the titanium component increased by the dry etching is oxidized, so that the contact angle of the titanium component on the surface of the second barrier metal 112 is increased. Therefore, the adhesion between the second barrier metal 112 and the polyimide film 105 can be improved. As a result, generation of side etching when the second barrier metal 112 is wet-etched can be suppressed, and generation of a space between the UBM 104 and the polyimide film 105 can be suppressed.

  As mentioned above, although embodiment of this invention was described with reference to drawings, these are the illustrations of this invention, Various structures other than the above are also employable.

  For example, in the above-described embodiment, the embodiment in which the dry etching treatment and the oxygen plasma treatment are performed as the surface treatment (roughening treatment) has been described. However, when another surface treatment (roughening treatment) method is used. Even so, it is only required that the adhesion between the second barrier metal 112 and the polyimide film 105 can be improved and the generation of a space between the UBM 104 and the polyimide film 105 can be suppressed.

  Moreover, in the said embodiment, in the process of surface-treating the 2nd barrier metal 112, the dry etching process and the oxygen plasma process are performed together, However, Each can also be performed independently. Even in this case, the surface of the second barrier metal 112 can be processed to improve the adhesion between the UBM 104 and the polyimide film 105, and the generation of a space between the UBM 104 and the polyimide film 105 is suppressed. it can.

It is sectional drawing which showed typically the structure of the semiconductor device which concerns on embodiment. It is sectional drawing which showed typically the manufacturing process of the semiconductor device which concerns on embodiment. It is sectional drawing which showed typically the manufacturing process of the semiconductor device which concerns on embodiment.

Explanation of symbols

DESCRIPTION OF SYMBOLS 100 Semiconductor device 101 Metal wiring layer 102 Insulating film 103 Protective film 104 UBM
105 polyimide film 106 bump 110 first barrier metal 112 second barrier metal 120 semiconductor substrate 122 SiO ₂ film 124 SiON film 126 via hole 128 second opening

Claims (5)

A method of manufacturing a semiconductor device comprising an electrode pad including a first barrier film, a ball base film, and a second barrier film formed on a semiconductor substrate, and a bump formed on the electrode pad,
Forming an insulating film and a protective film in order on the semiconductor substrate;
Forming a first opening that penetrates the insulating film and the protective film;
Forming the first barrier film on the surface along the first opening and on the protective film;
Forming the ball base film on the first barrier film;
Forming the second barrier film on the ball base film;
Applying a surface treatment to the second barrier film;
Forming a passivation film on the second barrier film;
Selectively removing the passivation film and forming a second opening;
Selectively removing the second barrier film subjected to the surface treatment to expose the ball base film;
Forming the bump so as to contact the exposed ball base film and a side surface of the passivation film facing the second opening;
A method for manufacturing a semiconductor device, comprising: In the manufacturing method of the semiconductor device according to claim 1,
The method for manufacturing a semiconductor device is characterized in that the surface treatment is a surface roughening treatment. In the manufacturing method of the semiconductor device according to claim 2,
The step of performing the surface roughening treatment is a step of etching the second barrier film using a gas containing carbon and halogen. In the manufacturing method of the semiconductor device according to claim 3,
A method of manufacturing a semiconductor device, wherein the halogen is fluorine. In the manufacturing method of the semiconductor device according to claim 2,
A method of manufacturing a semiconductor device, wherein the step of roughening the second barrier film is a step of performing oxygen plasma treatment on the second barrier film.

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