JP2006270031A - Semiconductor device and its manufacturing method - Google Patents

Semiconductor device and its manufacturing method Download PDF

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JP2006270031A
JP2006270031A JP2005275631A JP2005275631A JP2006270031A JP 2006270031 A JP2006270031 A JP 2006270031A JP 2005275631 A JP2005275631 A JP 2005275631A JP 2005275631 A JP2005275631 A JP 2005275631A JP 2006270031 A JP2006270031 A JP 2006270031A
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layer
protective film
semiconductor device
altered
opening
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Ichiro Kono
一郎 河野
Osamu Okada
修 岡田
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Casio Computer Co Ltd
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Casio Computer Co Ltd
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Priority to JP2005275631A priority Critical patent/JP2006270031A/en
Priority to US11/524,455 priority patent/US20070085224A1/en
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/11Manufacturing methods
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01006Carbon [C]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01018Argon [Ar]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013Alloys
    • H01L2924/014Solder alloys

Abstract

<P>PROBLEM TO BE SOLVED: To prevent a bad influence due to change in quality from being caused even when a top surface layer of a protective film changes in quality during manufacturing of a semiconductor device in which the protective film made of polyimide, etc. is formed on a silicon substrate. <P>SOLUTION: When an opening 6 is formed in the protective film 5 made of polyimide, etc., residue comprising polyimide, etc. may be left on the top surface of a connection pad 2 exposed through the opening 6 of the protective film 5. Consequently, the residue is removed by oxygen plasma ashing in the next place. In this case, a quality-changed layer A having an uneven structure is formed on the top surface side of the protective film 5. Then a natural oxide film formed on the top surface of the connection pad 2 exposed through openings 4 and 6 is removed by argon plasma etching. In this case, the quality-changed layer A further changes in quality to form a quality-changed layer C having a mesh structure. Then a first base metal layer 7 comprising titanium, etc. is formed. In this case, since the first base metal layer 7 is formed on the top surface of the quality-changed layer C having the mesh structure, adhesion force at the interface is high. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

この発明は半導体装置およびその製造方法に関する。   The present invention relates to a semiconductor device and a manufacturing method thereof.

従来の半導体装置には、半導体基板上にアルミニウムなどからなる複数の接続パッド、酸化シリコンなどからなる絶縁膜、ポリイミドからなる保護膜が設けられ、接続パッドが絶縁膜および保護膜に設けられた開口部を介して露出され、この露出された接続パッドの上面およびその近傍の保護膜の上面にチタン−タングステン合金からなる第1の下地金属層、金からなる第2の下地金属層および金からなるバンプ電極が設けられたものがある(例えば、特許文献1参照)。   In a conventional semiconductor device, a plurality of connection pads made of aluminum or the like on a semiconductor substrate, an insulating film made of silicon oxide or the like, a protective film made of polyimide, and an opening in which the connection pads are provided in the insulating film and the protective film The first base metal layer made of titanium-tungsten alloy, the second base metal layer made of gold, and gold are exposed on the upper surface of the exposed connection pad and the protective film in the vicinity thereof. Some bump electrodes are provided (for example, see Patent Document 1).

特許第2698827号公報Japanese Patent No. 2698827

そして、上記従来の半導体装置の製造方法では、第1の下地金属層を成膜する前に、アルミニウムなどからなる接続パッドの上面に形成された自然酸化膜をアルゴンイオンエッチングにより除去している。この場合、ポリイミドからなる保護膜の上面層がアルゴンイオンの影響を受けて変質し、保護膜の絶縁抵抗が低下し、最終的にはリーク不良を生じてしまうことがある。そこで、第1、第2の下地金属層およびバンプ電極を形成した後に、保護膜の少なくとも変質層を酸素プラズマエッチングにより除去している。   In the conventional method for manufacturing a semiconductor device, the natural oxide film formed on the upper surface of the connection pad made of aluminum or the like is removed by argon ion etching before forming the first base metal layer. In this case, the upper surface layer of the protective film made of polyimide may be affected by the influence of argon ions, the insulation resistance of the protective film may be lowered, and eventually a leak failure may occur. Therefore, after forming the first and second base metal layers and the bump electrodes, at least the altered layer of the protective film is removed by oxygen plasma etching.

ところで、ポリイミドからなる保護膜に開口部を形成したとき、保護膜の開口部を介して露出された接続パッドの上面にスカムと呼ばれるポリイミドの残渣が残存する場合がある。そこで、この残渣を酸素プラズマエッチングにより除去することがある。この場合、ポリイミドからなる保護膜の上面層が酸素プラズマの影響を受けて変質し、変質層(以下、この変質層を変質層Aという)が形成される。   By the way, when an opening is formed in the protective film made of polyimide, a polyimide residue called scum may remain on the upper surface of the connection pad exposed through the opening of the protective film. Therefore, this residue may be removed by oxygen plasma etching. In this case, the upper surface layer of the protective film made of polyimide is altered by the influence of oxygen plasma, and an altered layer (hereinafter, this altered layer is referred to as altered layer A) is formed.

そして、次に、絶縁膜および保護膜の開口部を介して露出された接続パッドの上面に形成された自然酸化膜を除去するため、アルゴンイオンエッチングを行なうと、このエッチングがイオンガン方式であれば、保護膜上の変質層Aがさらに変質して別の変質層(以下、この変質層を変質層Bという)が形成される。しかしながら、変質層Bは、後で説明するが、チタンなどからなる第1の下地金属層との密着力が低く、その界面で剥離が生じやすくなってしまうという問題がある。   Then, when argon ion etching is performed to remove the natural oxide film formed on the upper surface of the connection pad exposed through the openings of the insulating film and the protective film, if this etching is an ion gun method, The altered layer A on the protective film is further altered to form another altered layer (hereinafter, this altered layer is referred to as altered layer B). However, as will be described later, the deteriorated layer B has a problem that adhesion with the first base metal layer made of titanium or the like is low, and peeling easily occurs at the interface.

そこで、この発明は、保護膜の上面側に形成された変質層の下地金属層に対する密着力を向上させることができる半導体装置およびその製造方法を提供することを目的とする。   In view of the above, an object of the present invention is to provide a semiconductor device capable of improving the adhesion of an altered layer formed on the upper surface side of a protective film to a base metal layer and a method for manufacturing the same.

この発明は、上記目的を達成するため、上面に複数の接続パッドを有する半導体基板と、前記半導体基板上に設けられ、且つ、前記接続パッドに対応する部分に開口部を有する樹脂からなる保護膜と、前記保護膜の上面側にパターン形成された網目構造の変質層と、前記保護膜の開口部を介して露出された前記接続パッドの上面および前記変質層の上面に設けられた下地金属層とを備えていることを特徴とするものである。   In order to achieve the above object, the present invention provides a semiconductor substrate having a plurality of connection pads on the upper surface, and a protective film provided on the semiconductor substrate and made of a resin having openings at portions corresponding to the connection pads. An alteration layer having a network structure patterned on the upper surface side of the protective film, an upper surface of the connection pad exposed through the opening of the protective film, and a base metal layer provided on the upper surface of the alteration layer It is characterized by having.

この発明によれば、保護膜の上面側に変質層Bとは異なる網目構造の変質層を形成すると、この網目構造の変質層の下地金属層に対する密着力を向上させることができる。   According to the present invention, when an altered layer having a network structure different from the altered layer B is formed on the upper surface side of the protective film, the adhesion of the altered layer having the network structure to the underlying metal layer can be improved.

図1はこの発明の一実施形態としての半導体装置の断面図を示す。この半導体装置は、一般的にはCSP(chip size package)と呼ばれるものであり、シリコン基板(半導体基板)1を備えている。シリコン基板1の上面には所定の機能の集積回路(図示せず)が設けられ、上面周辺部にはアルミニウムやアルミニウム合金などのアルミニウム系金属からなる複数の接続パッド2が集積回路に接続されて設けられている。   FIG. 1 is a sectional view of a semiconductor device as an embodiment of the present invention. This semiconductor device is generally called a CSP (chip size package) and includes a silicon substrate (semiconductor substrate) 1. An integrated circuit (not shown) having a predetermined function is provided on the upper surface of the silicon substrate 1, and a plurality of connection pads 2 made of aluminum-based metal such as aluminum or aluminum alloy are connected to the integrated circuit around the upper surface. Is provided.

接続パッド2の中央部を除くシリコン基板1の上面には酸化シリコン、窒化シリコン、テオスなどからなる絶縁膜3が設けられ、接続パッド2の中央部は絶縁膜3に設けられた開口部4を介して露出されている。絶縁膜3の上面にはポリイミドやポリベンゾオキサイド(PBO)などからなる保護膜5が設けられている。この場合、保護膜5の上面側において後述する第1の下地金属層7下には、後で説明するように、変質層(以下、この変質層を変質層Cという)がパターン形成されている。また、絶縁膜3の開口部4に対応する部分における変質層Cを含む保護膜5には、絶縁膜3の開口部4よりもやや大きめの開口部6が設けられている。   An insulating film 3 made of silicon oxide, silicon nitride, Teos, or the like is provided on the upper surface of the silicon substrate 1 excluding the central portion of the connection pad 2, and the opening 4 provided in the insulating film 3 is provided in the central portion of the connection pad 2. Is exposed through. A protective film 5 made of polyimide, polybenzooxide (PBO) or the like is provided on the upper surface of the insulating film 3. In this case, an altered layer (hereinafter, this altered layer is referred to as an altered layer C) is patterned on the upper surface side of the protective film 5 below the first base metal layer 7 to be described later. . The protective film 5 including the altered layer C in a portion corresponding to the opening 4 of the insulating film 3 is provided with an opening 6 that is slightly larger than the opening 4 of the insulating film 3.

絶縁膜3および変質層Cを含む保護膜5の開口部4、6内および変質層Cの上面全体にはチタンやクロムなどからなる第1の下地金属層7が設けられている。第1の下地金属層7の上面全体には銅からなる第2の下地金属層8が設けられている。第2の下地金属層8の上面全体には銅からなる配線9が設けられている。第1、第2の下地金属層7、8を含む配線9の一端部は、絶縁膜3および変質層Cを含む保護膜5の開口部4、6を介して接続パッド2に接続されている。   A first base metal layer 7 made of titanium, chromium, or the like is provided in the openings 4 and 6 of the protective film 5 including the insulating film 3 and the altered layer C and on the entire upper surface of the altered layer C. A second base metal layer 8 made of copper is provided on the entire top surface of the first base metal layer 7. A wiring 9 made of copper is provided on the entire upper surface of the second base metal layer 8. One end of the wiring 9 including the first and second base metal layers 7 and 8 is connected to the connection pad 2 via the openings 4 and 6 of the protective film 5 including the insulating film 3 and the altered layer C. .

配線9の接続パッド部上面には銅からなる柱状電極10が設けられている。配線9を含む保護膜5の上面にはエポキシ系樹脂やフェノール系樹脂などからなる封止膜11がその上面が柱状電極10の上面と面一となるように設けられている。柱状電極10の上面には半田ボール12が設けられている。   A columnar electrode 10 made of copper is provided on the upper surface of the connection pad portion of the wiring 9. A sealing film 11 made of an epoxy resin, a phenol resin, or the like is provided on the upper surface of the protective film 5 including the wiring 9 so that the upper surface is flush with the upper surface of the columnar electrode 10. A solder ball 12 is provided on the upper surface of the columnar electrode 10.

次に、この半導体装置の製造方法の一例について説明する。まず、図2に示すように、ウエハ状態のシリコン1(半導体基板)上にアルミニウム系金属からなる複数の接続パッド2および酸化シリコンなどからなる絶縁膜3が設けられ、接続パッド2の中央部が絶縁膜3に形成された開口部4を介して露出されたものを用意する。この場合、ウエハ状態のシリコン基板1には、各半導体装置が形成される領域に所定の機能の集積回路(図示せず)が形成され、接続パッド2は、それぞれ、対応する領域に形成された集積回路に電気的に接続されている。   Next, an example of a method for manufacturing this semiconductor device will be described. First, as shown in FIG. 2, a plurality of connection pads 2 made of an aluminum-based metal and an insulating film 3 made of silicon oxide or the like are provided on silicon 1 (semiconductor substrate) in a wafer state. What is exposed through the opening 4 formed in the insulating film 3 is prepared. In this case, on the silicon substrate 1 in the wafer state, an integrated circuit (not shown) having a predetermined function is formed in a region where each semiconductor device is formed, and the connection pads 2 are formed in the corresponding regions. It is electrically connected to the integrated circuit.

次に、図3に示すように、絶縁膜3の開口部4を介して露出された接続パッド2の上面を含む絶縁膜3の上面全体に、スクリーン印刷法やスピンコート法などにより、ポリイミドやPBOなどからなる保護膜5を形成する。次に、フォトリソグラフィ法により、絶縁膜3の開口部3に対応する部分における保護膜5に、絶縁膜3の開口部4よりもやや大きめの開口部6を形成する。   Next, as shown in FIG. 3, the entire upper surface of the insulating film 3 including the upper surface of the connection pad 2 exposed through the opening 4 of the insulating film 3 is coated with polyimide or the like by screen printing or spin coating. A protective film 5 made of PBO or the like is formed. Next, an opening 6 that is slightly larger than the opening 4 of the insulating film 3 is formed in the protective film 5 at a portion corresponding to the opening 3 of the insulating film 3 by photolithography.

ここで、ポリイミドやPBOなどの樹脂からなる保護膜5に開口部6を形成したとき、保護膜5の開口部6を介して露出された接続パッド2の上面にスカムと呼ばれるポリイミドやPBOなどの樹脂からなる残渣(図示せず)が残存する場合がある。そこで、次に、この残渣を酸素プラズマアッシングにより除去する。この場合、図4に示すように、保護膜5の上面層が酸素プラズマの影響を受けて変質し、変質層Aが形成される。   Here, when the opening 6 is formed in the protective film 5 made of resin such as polyimide or PBO, polyimide or PBO called scum is formed on the upper surface of the connection pad 2 exposed through the opening 6 of the protective film 5. Residues (not shown) made of resin may remain. Therefore, next, this residue is removed by oxygen plasma ashing. In this case, as shown in FIG. 4, the upper surface layer of the protective film 5 is altered by the influence of oxygen plasma, and the altered layer A is formed.

次に、絶縁膜3および変質層Aを含む保護膜5の開口部4、6を介して露出されたアルミニウム系金属からなる接続パッド2の上面に形成された自然酸化膜(図示せず)をアルゴンガスなどの不活性ガスを用いたプラズマエッチングにより除去する。このようなプラズマエッチングにより、変質層Aがさらに変質して変質層Cが形成される。不活性ガスを用いたプラズマエッチングの方式としては、1周波励起または2周波励起の反応性イオンエッチング(RIE)、ヘリコン波励起型反応性高密度プラズマ、2周波励起の誘導結合型プラズマ(ICP、inductively coupled plasma)、ISM(inductively super magneron)などがあり、特に、2周波励起のICP、ISMを用いたプラズマエッチングが好ましい。   Next, a natural oxide film (not shown) formed on the upper surface of the connection pad 2 made of an aluminum-based metal exposed through the openings 4 and 6 of the protective film 5 including the insulating film 3 and the altered layer A is formed. Removal is performed by plasma etching using an inert gas such as argon gas. By such plasma etching, the altered layer A is further altered, and the altered layer C is formed. As a plasma etching method using an inert gas, reactive ion etching (RIE) excited by one frequency or two frequencies, reactive high-density plasma excited by helicon wave, two-frequency excited inductively coupled plasma (ICP, Inductively coupled plasma), ISM (inductively super magneron), and the like, and plasma etching using ICP or ISM excited by two frequencies is particularly preferable.

ここで、図3に示す保護膜5の上面のSEM(走査型電子顕微鏡)写真である図12(A)を見ると、上面がほぼ平坦であり、変質層は形成されていない。次に、変質層Aの上面のSEM写真である図12(B)を見ると、上面が10〜100nmの凸凹構造となっており、変質層Aが形成されている。次に、変質層Cの上面のSEM写真である図12(C)を見ると、変質層Aよりも表面粗さが粗い網目構造となっており、変質層Cが形成されている。   Here, referring to FIG. 12A, which is an SEM (scanning electron microscope) photograph of the upper surface of the protective film 5 shown in FIG. 3, the upper surface is almost flat, and the altered layer is not formed. Next, when FIG. 12B, which is an SEM photograph of the upper surface of the altered layer A, is seen, the upper surface has an uneven structure with a thickness of 10 to 100 nm, and the altered layer A is formed. Next, referring to FIG. 12C, which is an SEM photograph of the upper surface of the altered layer C, a network structure having a rougher surface roughness than the altered layer A is formed, and the altered layer C is formed.

この場合、変質層Cの網目の直径は10〜500nm、網の太さは10〜200nm、層厚は10〜1000nmである。また、保護膜5の材料であるポリイミドあるいはPBOの構成元素が炭素、酸素、窒素、水素であるので、変質層Cの構成元素は炭素、酸素、窒素、水素、不活性ガスとなる。この場合、変質層Cに含まれる不活性ガスは、不活性ガスとしてアルゴンガスを用いたプラズマエッチング処理ではアルゴンガスである。なお、変質層Aの構成元素は、保護膜5と同じで、炭素、酸素、窒素、水素である。   In this case, the modified layer C has a mesh diameter of 10 to 500 nm, a mesh thickness of 10 to 200 nm, and a layer thickness of 10 to 1000 nm. Further, since the constituent elements of polyimide or PBO, which is the material of the protective film 5, are carbon, oxygen, nitrogen, and hydrogen, the constituent elements of the altered layer C are carbon, oxygen, nitrogen, hydrogen, and an inert gas. In this case, the inert gas contained in the altered layer C is argon gas in the plasma etching process using argon gas as the inert gas. The constituent elements of the altered layer A are the same as those of the protective film 5 and are carbon, oxygen, nitrogen, and hydrogen.

ところで、接続パッド2の上面の自然酸化膜を除去するために、アルゴンガスを用いたプラズマエッチングの代わりに、イオンガン方式によるアルゴンイオンエッチングを行なった場合には、保護膜5の上面側に、変質層Cではなく、変質層Bが形成される。そして、変質層Bの上面のSEM写真である図12(D)を見ると、図12(B)に示す変質層Aで見られた凸凹が減少して、図12(A)に示す保護膜5の上面に近い状態となっている。   By the way, in order to remove the natural oxide film on the upper surface of the connection pad 2, instead of plasma etching using argon gas, when argon ion etching is performed by an ion gun method, the alteration is caused on the upper surface side of the protective film 5. Not the layer C but the altered layer B is formed. 12 (D) which is an SEM photograph of the upper surface of the altered layer B, the unevenness seen in the altered layer A shown in FIG. 12 (B) is reduced, and the protective film shown in FIG. 12 (A). 5 is close to the upper surface.

次に、図5に示すように、絶縁膜3および変質層Cを含む保護膜5の開口部4、6を介して露出された接続パッド2の上面を含む変質層Cの上面全体に、スパッタ法などにより、チタンやクロムなどからなる第1の下地金属層7および銅からなる第2の下地金属層8を連続して成膜する。この場合、第1の下地金属層7は変質層Cの上面に成膜されるため、後で説明するように、その界面の密着力は高い。なお、下地金属層は、接着機能とバリア機能を有するものであれば1層とすることもできる。   Next, as shown in FIG. 5, the entire upper surface of the altered layer C including the upper surface of the connection pad 2 exposed through the openings 4 and 6 of the protective film 5 including the insulating film 3 and the altered layer C is sputtered. The first base metal layer 7 made of titanium or chromium and the second base metal layer 8 made of copper are successively formed by a method or the like. In this case, since the first base metal layer 7 is formed on the upper surface of the altered layer C, the adhesion at the interface is high as will be described later. The base metal layer may be a single layer as long as it has an adhesion function and a barrier function.

次に、第2の下地金属層8の上面にメッキレジスト膜21をパターン形成する。この場合、配線9形成領域に対応する部分におけるメッキレジスト膜21には開口部22が形成されている。次に、第1、第2の下地金属層7、8をメッキ電流路として銅の電解メッキを行なうことにより、メッキレジスト膜21の開口部22内の第2の下地金属層8の上面に配線9を形成する。次に、メッキレジスト膜21を剥離する。なお、下地金属層を厚く形成することにより下地金属層のみからなる配線とすることも可能である。   Next, a plating resist film 21 is pattern-formed on the upper surface of the second base metal layer 8. In this case, an opening 22 is formed in the plating resist film 21 in a portion corresponding to the wiring 9 formation region. Next, by performing copper electroplating using the first and second base metal layers 7 and 8 as plating current paths, wiring is formed on the upper surface of the second base metal layer 8 in the opening 22 of the plating resist film 21. 9 is formed. Next, the plating resist film 21 is peeled off. Note that it is also possible to form a wiring composed of only the base metal layer by forming the base metal layer thick.

次に、図6に示すように、配線9を含む第2の下地金属層8の上面にメッキレジスト膜23をパターン形成する。この場合、柱状電極10形成領域に対応する部分におけるメッキレジスト膜23には開口部24が形成されている。次に、第1、第2の下地金属層7、8をメッキ電流路として銅の電解メッキを行なうことにより、メッキレジスト膜23の開口部24内の配線9の接続パッド部上面に柱状電極10を形成する。   Next, as shown in FIG. 6, a plating resist film 23 is patterned on the upper surface of the second base metal layer 8 including the wiring 9. In this case, an opening 24 is formed in the plating resist film 23 in a portion corresponding to the columnar electrode 10 formation region. Next, by performing copper electroplating using the first and second base metal layers 7 and 8 as plating current paths, the columnar electrode 10 is formed on the upper surface of the connection pad portion of the wiring 9 in the opening 24 of the plating resist film 23. Form.

次に、メッキレジスト膜23を剥離し、次いで、配線9をマスクとして第1、第2の下地金属層7、8の不要な部分をエッチングして除去すると、図7に示すように、配線9下にのみ第1、第2の下地金属層7、8が残存される。   Next, the plating resist film 23 is peeled off, and then unnecessary portions of the first and second base metal layers 7 and 8 are removed by etching using the wiring 9 as a mask. As shown in FIG. The first and second base metal layers 7 and 8 remain only below.

この状態では、第1の下地金属層7下以外の領域における保護膜5の上面にも変質層Cが形成されている。変質層Cは導電性を有するため、このままでは、配線9間でショートが生じてしまう。そこで、次に、第1の下地金属層7下以外の領域における変質層Cを酸素プラズマアッシングにより除去すると、図8に示すように、第1の下地金属層7下にのみ変質層Cが残存される。   In this state, the altered layer C is also formed on the upper surface of the protective film 5 in a region other than the region under the first base metal layer 7. Since the deteriorated layer C has conductivity, a short circuit occurs between the wirings 9 as it is. Therefore, next, when the altered layer C in the region other than under the first base metal layer 7 is removed by oxygen plasma ashing, the altered layer C remains only under the first base metal layer 7 as shown in FIG. Is done.

この場合の酸素プラズマアッシングとしては、ICP(Inductively Coupled Plasma)タイプのプラズマアッシング装置を用い、ウエハ1枚に対して、酸素量200〜500sccm、プラズマパワー500〜1000W、圧力20〜133Pa、ステージ温度40〜80℃、処理時間10〜60secの条件で行なった。   As oxygen plasma ashing in this case, an ICP (Inductively Coupled Plasma) type plasma ashing apparatus is used. The oxygen amount is 200 to 500 sccm, the plasma power is 500 to 1000 W, the pressure is 20 to 133 Pa, and the stage temperature is 40 for one wafer. It was carried out under conditions of ˜80 ° C. and treatment time of 10 to 60 seconds.

すると、オーバーアッシングとなり、第1の下地金属層7下以外の領域における保護膜の上面側の一部も除去され、第1の下地金属層7下以外の領域における変質層Cが完全に除去された。この場合、第1の下地金属層7下以外の領域における保護膜5の上面層が酸素プラズマの影響を受けて変質し、変質層Aが形成されるが、別に支障はない。   Then, overashing occurs, and a part of the upper surface side of the protective film in a region other than the region under the first base metal layer 7 is also removed, and the altered layer C in a region other than the region under the first base metal layer 7 is completely removed. It was. In this case, the upper surface layer of the protective film 5 in a region other than the region under the first base metal layer 7 is altered by the influence of oxygen plasma to form the altered layer A, but there is no problem.

次に、図9に示すように、柱状電極10および配線9を含む保護膜5の上面全体に、スクリーン印刷法やスピンコート法などにより、エポキシ系樹脂などからなる封止膜11をその厚さが柱状電極10の高さよりも厚くなるように形成する。したがって、この状態では、柱状電極10の上面は封止膜11によって覆われている。   Next, as shown in FIG. 9, the sealing film 11 made of epoxy resin or the like is formed on the entire upper surface of the protective film 5 including the columnar electrodes 10 and the wirings 9 by screen printing or spin coating. Is formed to be thicker than the height of the columnar electrode 10. Therefore, in this state, the upper surface of the columnar electrode 10 is covered with the sealing film 11.

次に、封止膜11および柱状電極10の上面側を適宜に研磨し、図10に示すように、柱状電極10の上面を露出させ、且つ、この露出された柱状電極10の上面を含む封止膜11の上面を平坦化する。次に、図11に示すように、柱状電極10の上面に半田ボール11を形成する。次に、ダイシング工程を経ると、図1に示す半導体装置が複数個得られる。   Next, the upper surface side of the sealing film 11 and the columnar electrode 10 is appropriately polished, and the upper surface of the columnar electrode 10 is exposed as shown in FIG. 10, and the sealing including the exposed upper surface of the columnar electrode 10 is performed. The upper surface of the stop film 11 is flattened. Next, as shown in FIG. 11, solder balls 11 are formed on the upper surface of the columnar electrode 10. Next, through a dicing process, a plurality of semiconductor devices shown in FIG. 1 are obtained.

このようにして得られた半導体装置では、ポリイミドやPBOなどからなる保護膜5の上面側に、変質層Bではなく、網目構造の変質層Cを形成しているので、この網目構造の変質層Cのチタンやクロムなどからなる第1の下地金属層7に対する密着力を、次に説明するように、向上させることができる。   In the semiconductor device thus obtained, the modified layer C having a network structure is formed instead of the modified layer B on the upper surface side of the protective film 5 made of polyimide, PBO or the like. The adhesion of C to the first base metal layer 7 made of titanium, chromium, or the like can be improved as described below.

次に、上記製造方法により製造された半導体装置のプレッシャークッカーテスト(PCT)によるシェア強度試験について説明する。この場合、図13に示す本発明品を用意した。この本発明品は、シリコン基板1の上面にポリイミドからなる保護膜5が形成され、保護膜5の上面に変質層Cが形成され、変質層Cの上面に平面円形状のチタンからなる第1の下地金属層7、銅からなる第2の下地金属層8および銅からなる柱状電極10が形成された構造となっている。また、比較のために、図13に示す本発明品と同じ構造であるが、保護膜5の上面に変質層Bが形成された比較品を用意した。   Next, the shear strength test by the pressure cooker test (PCT) of the semiconductor device manufactured by the above manufacturing method will be described. In this case, the product of the present invention shown in FIG. 13 was prepared. In the product of the present invention, a protective film 5 made of polyimide is formed on the upper surface of the silicon substrate 1, an altered layer C is formed on the upper surface of the protective film 5, and a first layer made of planar circular titanium is formed on the upper surface of the altered layer C. The base metal layer 7, the second base metal layer 8 made of copper, and the columnar electrode 10 made of copper are formed. For comparison, a comparative product having the same structure as the product of the present invention shown in FIG. 13 but having an altered layer B formed on the upper surface of the protective film 5 was prepared.

そして、本発明品および比較品について、シリコン基板1を固定した状態で、柱状電極10の側面にシェア測定治具(図示せず)を押し付けて、第1の下地金属層7が変質層C(B)から剥離したときの強度(g)を求めた。この場合、本発明品および比較品共に、環境試験投入前のシェア強度を1とし、PCTの飽和(温度121℃、湿度100%Rh、2気圧)に500時間放置した後でのシェア強度を求めた。   Then, for the product of the present invention and the comparative product, with the silicon substrate 1 fixed, a shear measurement jig (not shown) is pressed against the side surface of the columnar electrode 10 so that the first base metal layer 7 becomes the altered layer C ( The strength (g) when peeled from B) was determined. In this case, both the present invention product and the comparative product have a shear strength of 1 before the environmental test, and determine the shear strength after standing for 500 hours in PCT saturation (temperature 121 ° C., humidity 100% Rh, 2 atm). It was.

すると、比較品の場合には、環境試験投入前のシェア強度を1としたとき、PCTの飽和に500時間放置した後でのシェア強度は0.1まで低下した。これに対し、本発明品の場合には、環境試験投入前のシェア強度を1としたとき、PCTの飽和に500時間放置した後でのシェア強度は0.68まで低下したが、比較品の6.8倍であり、界面密着力が向上したと言える。   Then, in the case of the comparative product, when the shear strength before the environmental test was set to 1, the shear strength after leaving for 500 hours in the saturation of the PCT decreased to 0.1. On the other hand, in the case of the product of the present invention, when the shear strength before the environmental test was set to 1, the shear strength after leaving for 500 hours at the saturation of PCT decreased to 0.68. It was 6.8 times, and it can be said that the interfacial adhesion was improved.

なお、この発明は、CSPと呼ばれる半導体装置に限らず、例えば、上記従来例の如く、半導体基板上に複数の接続パッド、絶縁膜、保護膜が設けられ、接続パッドが絶縁膜および保護膜に設けられた開口部を介して露出され、この露出された接続パッドの上面およびその近傍の保護膜の上面に第1、第2の下地金属層およびバンプ電極が設けられたものにも適用することができる。   The present invention is not limited to a semiconductor device called a CSP. For example, as in the above-described conventional example, a plurality of connection pads, insulating films, and protective films are provided on a semiconductor substrate, and the connection pads are formed as insulating films and protective films. The present invention is also applicable to the case where the first and second base metal layers and the bump electrode are provided on the upper surface of the exposed connection pad and the protective film in the vicinity thereof exposed through the provided opening. Can do.

この発明の一実施形態としての半導体装置の断面図。1 is a cross-sectional view of a semiconductor device as an embodiment of the present invention. 図1に示す半導体装置の製造方法の一例において、当初用意したものの断面図。Sectional drawing of what was prepared initially in an example of the manufacturing method of the semiconductor device shown in FIG. 図2に続く工程の断面図。Sectional drawing of the process following FIG. 図3に続く工程の断面図。Sectional drawing of the process following FIG. 図4に続く工程の断面図。Sectional drawing of the process following FIG. 図5に続く工程の断面図。Sectional drawing of the process following FIG. 図6に続く工程の断面図。Sectional drawing of the process following FIG. 図7に続く工程の断面図。Sectional drawing of the process following FIG. 図8に続く工程の断面図。FIG. 9 is a cross-sectional view of the process following FIG. 8. 図9に続く工程の断面図。Sectional drawing of the process following FIG. 図10に続く工程の断面図。Sectional drawing of the process following FIG. (A)〜(D)はそれぞれ保護膜、変質層A、変質層Cおよび変質層Bの各上面のSEM写真を示す図。(A)-(D) is a figure which shows the SEM photograph of each upper surface of a protective film, the altered layer A, the altered layer C, and the altered layer B, respectively. シェア強度試験に用いた本発明品の斜視図。The perspective view of this invention product used for the shear strength test.

符号の説明Explanation of symbols

1 シリコン基板
2 接続パッド
3 絶縁膜
4 開口部
5 保護膜
6 開口部
7 第1の下地金属層
8 第2の下地金属層
9 配線
10 柱状電極
11 封止膜
12 半田ボール
A 変質層A
B 変質層B
C 変質層C
DESCRIPTION OF SYMBOLS 1 Silicon substrate 2 Connection pad 3 Insulating film 4 Opening part 5 Protective film 6 Opening part 7 1st base metal layer 8 2nd base metal layer 9 Wiring 10 Columnar electrode 11 Sealing film 12 Solder ball A Alteration layer A
B Altered layer B
C Altered layer C

Claims (13)

上面に複数の接続パッドを有する半導体基板と、前記半導体基板上に設けられ、且つ、前記接続パッドに対応する部分に開口部を有する樹脂からなる保護膜と、前記保護膜の上面側にパターン形成された網目構造の変質層と、前記保護膜の開口部を介して露出された前記接続パッドの上面および前記変質層の上面に設けられた金属層とを備えていることを特徴とする半導体装置。   A semiconductor substrate having a plurality of connection pads on the upper surface, a protective film formed on the semiconductor substrate and having an opening in a portion corresponding to the connection pads, and pattern formation on the upper surface side of the protective film And a metal layer provided on the upper surface of the connection pad exposed through the opening of the protective film and on the upper surface of the deteriorated layer. . 請求項1に記載の発明において、前記保護膜は炭素、酸素、窒素、水素を含む樹脂からなることを特徴とする半導体装置。   2. The semiconductor device according to claim 1, wherein the protective film is made of a resin containing carbon, oxygen, nitrogen, and hydrogen. 請求項2に記載の発明において、前記変質層は炭素、酸素、窒素、水素、アルゴンを含むものからなることを特徴とする半導体装置。   3. The semiconductor device according to claim 2, wherein the altered layer includes carbon, oxygen, nitrogen, hydrogen, and argon. 請求項1に記載の発明において、前記変質層の網目構造は、網目の直径が10〜500nm、網の太さが10〜200nm、層厚が10〜1000nmであることを特徴とする半導体装置。   2. The semiconductor device according to claim 1, wherein the network structure of the altered layer has a mesh diameter of 10 to 500 nm, a mesh thickness of 10 to 200 nm, and a layer thickness of 10 to 1000 nm. 請求項1に記載の発明において、前記金属層上に配線が設けられていることを特徴とする半導体装置。   2. The semiconductor device according to claim 1, wherein wiring is provided on the metal layer. 請求項5に記載の発明において、前記配線の接続パッド部上に柱状電極が設けられていることを特徴とする半導体装置。   6. The semiconductor device according to claim 5, wherein a columnar electrode is provided on a connection pad portion of the wiring. 請求項6に記載の発明において、前記柱状電極の周囲に封止膜が設けられ、前記柱状電極上に半田ボールが設けられていることを特徴とする半導体装置。   7. The semiconductor device according to claim 6, wherein a sealing film is provided around the columnar electrode, and a solder ball is provided on the columnar electrode. 上面に複数の接続パッドを有する半導体基板上に、前記接続パッドに対応する部分に開口部を有する樹脂からなる保護膜を形成する工程と、
前記保護膜の開口部を介して露出された前記接続パッドの上面に残存された前記保護膜の残渣を酸素プラズマアッシングにより除去し、当該酸素プラズマアッシングにより前記保護膜の上面層が変質された変質層Aが形成される工程と、
前記保護膜の開口部を介して露出された前記接続パッドの上面に形成された酸化膜を、不活性ガスを用いたプラズマエッチングにより除去し、当該プラズマエッチングにより前記変質層Aが変質され、当該変質層よりも表面粗さが粗い変質層Cが形成される工程と、
前記保護膜の開口部を介して露出された前記接続パッドの上面および前記変質層Cの上面に金属層をパターン形成する工程と、
前記金属層下以外の領域における前記変質層Cを酸素プラズマアッシングにより除去する工程と、
を有することを特徴とする半導体装置の製造方法。
Forming a protective film made of a resin having an opening in a portion corresponding to the connection pad on a semiconductor substrate having a plurality of connection pads on the upper surface;
Deterioration in which the residue of the protective film remaining on the upper surface of the connection pad exposed through the opening of the protective film is removed by oxygen plasma ashing, and the upper surface layer of the protective film is altered by the oxygen plasma ashing The step of forming layer A;
The oxide film formed on the upper surface of the connection pad exposed through the opening of the protective film is removed by plasma etching using an inert gas, and the altered layer A is altered by the plasma etching. A step of forming a modified layer C having a rougher surface roughness than the modified layer;
Patterning a metal layer on the upper surface of the connection pad and the upper surface of the altered layer C exposed through the opening of the protective film;
Removing the altered layer C in a region other than under the metal layer by oxygen plasma ashing;
A method for manufacturing a semiconductor device, comprising:
請求項8に記載の発明において、前記変質層Cを除去する工程は前記金属層下以外の領域における前記保護膜の上面側の一部を含んで除去することを特徴とする半導体装置の製造方法。   9. The method of manufacturing a semiconductor device according to claim 8, wherein the step of removing the deteriorated layer C includes a part on the upper surface side of the protective film in a region other than under the metal layer. . 請求項8に記載の発明において、前記変質層Cは、網目構造を有することを特徴とする半導体装置の製造方法。   9. The method of manufacturing a semiconductor device according to claim 8, wherein the altered layer C has a network structure. 請求項10に記載の発明において、前記変質層の網目構造は、網目の直径が10〜500nm、網の太さが10〜200nm、層厚が10〜1000nmであることを特徴とする半導体装置の製造方法。   11. The semiconductor device according to claim 10, wherein the network structure of the altered layer has a mesh diameter of 10 to 500 nm, a mesh thickness of 10 to 200 nm, and a layer thickness of 10 to 1000 nm. Production method. 請求項8に記載の発明において、前記保護膜は炭素、酸素、窒素、水素を含む樹脂によって形成することを特徴とする半導体装置の製造方法。   9. The method of manufacturing a semiconductor device according to claim 8, wherein the protective film is formed of a resin containing carbon, oxygen, nitrogen, and hydrogen. 請求項12に記載の発明において、前記不活性ガスはアルゴンガスであり、前記変質層Cは炭素、酸素、窒素、水素、アルゴンを含むものからなることを特徴とする半導体装置の製造方法。   13. The method of manufacturing a semiconductor device according to claim 12, wherein the inert gas is an argon gas, and the altered layer C includes carbon, oxygen, nitrogen, hydrogen, and argon.
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US10163817B2 (en) 2015-12-16 2018-12-25 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor device structure comprising a plurality of metal oxide fibers and method for forming the same
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US10224293B2 (en) 2015-12-16 2019-03-05 Taiwan Semiconductor Manufacturing Company, Ltd. Package structure and method for forming the same
US10636748B2 (en) 2015-12-16 2020-04-28 Taiwan Semiconductor Manufacturing Co., Ltd. Package structure
US10943873B2 (en) 2015-12-16 2021-03-09 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor device structure comprising a plurality of metal oxide fibers and method for forming the same

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