CN104465574B - It is a kind of that the bump packaging structure for connecing layer is used as using FeP alloys - Google Patents
It is a kind of that the bump packaging structure for connecing layer is used as using FeP alloys Download PDFInfo
- Publication number
- CN104465574B CN104465574B CN201310416014.7A CN201310416014A CN104465574B CN 104465574 B CN104465574 B CN 104465574B CN 201310416014 A CN201310416014 A CN 201310416014A CN 104465574 B CN104465574 B CN 104465574B
- Authority
- CN
- China
- Prior art keywords
- layer
- bump
- packaging structure
- connect
- metal seed
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 238000004806 packaging method and process Methods 0.000 title claims abstract description 26
- 239000000956 alloy Substances 0.000 title claims abstract description 21
- 229910045601 alloy Inorganic materials 0.000 title claims abstract description 17
- 229910000679 solder Inorganic materials 0.000 claims abstract description 30
- 229910052751 metal Inorganic materials 0.000 claims abstract description 26
- 239000002184 metal Substances 0.000 claims abstract description 26
- 239000004065 semiconductor Substances 0.000 claims abstract description 13
- 239000000758 substrate Substances 0.000 claims abstract description 12
- 239000010949 copper Substances 0.000 claims abstract description 10
- 229910052802 copper Inorganic materials 0.000 claims abstract description 9
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical group [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims abstract description 8
- 229910000881 Cu alloy Inorganic materials 0.000 claims abstract description 6
- 239000000463 material Substances 0.000 claims abstract description 6
- 229910001128 Sn alloy Inorganic materials 0.000 claims abstract description 5
- 229910001069 Ti alloy Inorganic materials 0.000 claims abstract description 5
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 claims abstract description 5
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 claims abstract description 5
- 229910001080 W alloy Inorganic materials 0.000 claims abstract description 5
- 239000010936 titanium Substances 0.000 claims abstract description 5
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 claims abstract description 5
- 239000010937 tungsten Substances 0.000 claims abstract description 5
- 238000002161 passivation Methods 0.000 claims description 18
- 239000000203 mixture Substances 0.000 claims description 6
- 239000000126 substance Substances 0.000 claims description 5
- 239000012535 impurity Substances 0.000 claims description 4
- 238000001465 metallisation Methods 0.000 claims description 3
- 238000000034 method Methods 0.000 abstract description 13
- 230000005611 electricity Effects 0.000 abstract description 3
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 7
- 238000010406 interfacial reaction Methods 0.000 description 7
- 229910000765 intermetallic Inorganic materials 0.000 description 5
- XEEYBQQBJWHFJM-UHFFFAOYSA-N iron Substances [Fe] XEEYBQQBJWHFJM-UHFFFAOYSA-N 0.000 description 5
- 230000008569 process Effects 0.000 description 5
- 229910005382 FeSn Inorganic materials 0.000 description 4
- 230000008901 benefit Effects 0.000 description 4
- 229910005391 FeSn2 Inorganic materials 0.000 description 3
- 150000001875 compounds Chemical class 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 3
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 3
- 239000010931 gold Substances 0.000 description 3
- 229910052737 gold Inorganic materials 0.000 description 3
- 229910052759 nickel Inorganic materials 0.000 description 3
- 238000005240 physical vapour deposition Methods 0.000 description 3
- 238000007747 plating Methods 0.000 description 3
- 229910003306 Ni3Sn4 Inorganic materials 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 239000000919 ceramic Substances 0.000 description 2
- 230000008859 change Effects 0.000 description 2
- 230000007547 defect Effects 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 238000010992 reflux Methods 0.000 description 2
- 229910001316 Ag alloy Inorganic materials 0.000 description 1
- 229910018471 Cu6Sn5 Inorganic materials 0.000 description 1
- 229910002555 FeNi Inorganic materials 0.000 description 1
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 229910007116 SnPb Inorganic materials 0.000 description 1
- 238000005275 alloying Methods 0.000 description 1
- 239000004411 aluminium Substances 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 238000013459 approach Methods 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 238000005538 encapsulation Methods 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 229910052742 iron Inorganic materials 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 238000004377 microelectronic Methods 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 238000001259 photo etching Methods 0.000 description 1
- 230000002035 prolonged effect Effects 0.000 description 1
- 230000001681 protective effect Effects 0.000 description 1
- 230000036632 reaction speed Effects 0.000 description 1
- 238000011160 research Methods 0.000 description 1
- 238000012827 research and development Methods 0.000 description 1
- 238000007650 screen-printing Methods 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- -1 sn-ag alloy Chemical compound 0.000 description 1
- 238000005476 soldering Methods 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
- 230000007704 transition Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
Landscapes
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Wire Bonding (AREA)
Abstract
The invention discloses a kind of using FeP alloys as the bump packaging structure for connecing layer, belong to semiconductor device packaging technique field.The bump packaging structure includes Semiconductor substrate, enclosure cavity structure and solder bump, and the enclosure cavity structure includes metal seed layer and connects layer；Wherein：The layer that connects is ferrophosphor(us) material, and the solder bump is tin or tin alloy material, and the metal seed layer is copper, titanium, tungsten or copper alloy.Excellent solderability, the slow-footed characteristic of interface layer growth that the present invention has using FeP alloys, connect layer, so as to improve the mechanics of mutual disjunctor, electricity, thermal property and service reliability and reduce packaging cost as bump packaging structure.
Description
Technical field
The present invention relates to semiconductor device packaging technique field, and in particular to a kind of using FeP alloys as connecing the convex of layer
Point encapsulating structure.
Background technology
In recent years, because the production of integrated circuits of chip develops to high integration, its chip package is also needed to high power, height
Density, the frivolous direction with microminiaturization are developed.Bump packaging structure has turned into one of current most widely used encapsulating structure, its
Interconnection process is：Solder bump is made on chip first, chip bump is then directed at metallized ceramic or multi-layer ceramics base
Metallized pads on plate, in carrying out Reflow Soldering under protective atmosphere and suitable temperature.Existing bump packaging structure is typically used
Copper or nickel are as connecing layer, but with the increasingly raising of packaging density, and the size of soldered ball becomes less and less on salient point, interface gold
Influence of the fragility of compound to mutual disjunctor reliability also becomes increasingly severe between category.Though copper has electricity as interfacial reaction layer
The advantages such as high and excellent between the solder wetability of conductance, can be achieved good metallurgical binding, but also there is such as interface simultaneously
Too fast, Cu layers of layer growth consumes the defects such as too fast and easy formation Kirkendall holes.Nickel can be effective as interfacial reaction layer
Barrier metal Seed Layer Cu diffusion, but still make in the presence of such as black pad, Kirkendall holes and boundary layer fast-growth
The defects such as solder joint embrittlement.In addition SnPb solders are significantly faster than that using the reaction speed between high Sn lead-free solders and Ni, with height
The extensive use of Sn lead-free solders, the fast-growth of interface compound can similarly reduce the service reliability of Ni base UBM structures.
The exploration of interfacial reaction layer with more dominance energy has turned into one of hot issue of Current electronic encapsulation field research, such as domestic
Outer many scholars are intended to improve existing NiP layers of property by adding other alloying elements with the approach for forming binary or multi-element layers
Energy.But the various novel alloy coating researched and developed at present, such as FeNi, NiV production cost is higher, extensively should it can not yet obtain at present
With.
The intermetallic compound FeSn of interfacial reaction generation between Fe and Sn2, and FeSn2It is slow, fine and close with the speed of growth
The advantages of having spent, therefore Fe bases UBM research and development obtain the extensive concerns of many microelectronics Packaging enterprises in recent years.But because Fe is easy
In oxidation, cause its wetability very poor, report is had no using Fe always as the UBM work for connecing layer.
The content of the invention
It is an object of the invention to the excellent solderability having using FeP alloys, the slow-footed characteristic of interface layer growth, carry
For a kind of using FeP alloys as the bump packaging structure for connecing layer, mechanics, electricity, thermal property and the military service of mutual disjunctor are improved
Reliability simultaneously reduces packaging cost.
To achieve the above object, the technical scheme is that：
It is a kind of using FeP alloys as the bump packaging structure for connecing layer, including Semiconductor substrate, enclosure cavity
(UBM) structure and solder bump, enclosure cavity (UBM) structure include metal seed layer and connect layer；Wherein：Institute
State and connect layer for ferrophosphor(us) material, the solder bump is tin or tin alloy material, the metal seed layer is copper, titanium, tungsten
Or copper alloy.
It is described to connect layer its chemical composition is calculated as by atomic percentage conc with ferrophosphor(us)：Ferro element：85-99%, remaining is
P elements and inevitable impurity.
The thickness for connecing layer is 1-5 μm adjustable, the thickness of the metal seed layer between 100 angstroms to 10000 angstroms it
Between, a diameter of 20-300 μm of the solder bump.
Above-mentioned bump packaging structure also includes pad and passivation layer, and the pad and passivation layer are located at the Semiconductor substrate
Upper surface, the passivation layer is overlying on the upper surface beyond Semiconductor substrate bonding pad opening；Provided with gold above the bonding pad opening
Belong to provided with layer is connect above Seed Layer, the metal seed layer, described connect is provided with solder bump above layer.
Compared with prior art, the beneficial effects of the invention are as follows：
1st, under proper condition, FeP alloy-layers have good wettability, and FeP gives birth to Sn parent metals interfacial reaction
Into intermetallic compound FeSn2Have the advantages that the speed of growth is slow, good compactness.Cu, Ni and NiP are replaced from FeP alloys
Alloy can suppress the fast-growth of interfacial reaction layer and connect the quick consumption of layer, increase substantially salient point as layer is connect
The service life of encapsulating structure.
2nd, because cost of material is relatively low, the more existing other alloys of cost for preparing UBM structures using FeP alloys, which have, relatively to be shown
The advantage of work.
Brief description of the drawings
Fig. 1 is a kind of structural representation of bump packaging structure of the invention.
Fig. 2 is a kind of embodiment flow chart of bump packaging structure of the invention.
Fig. 3 is FeSn on FeP/Sn interfaces2The growth kinetics curve of intermetallic compound.
In figure：1- Semiconductor substrates；2- pads；3- passivation layers；4- metal seed layers；5- connects layer；6- solder bumps.
Embodiment
The present invention is described in further detail below in conjunction with the accompanying drawings.
Fig. 1 is the schematic diagram of bump packaging structure of the present invention, and the bump packaging structure includes Semiconductor substrate 1, salient point
Lower metallization structure, solder bump 6, pad 2 and passivation layer 3, the enclosure cavity structure include metal seed layer 4
With connect layer 5；The pad 2 and passivation layer 3 are located at the upper surface of the Semiconductor substrate 1, and the passivation layer 3 is overlying on semiconductor
Upper surface beyond the pad 2 of substrate 1 opening；The overthe openings of pad 2 are provided with metal seed layer 4, the metal seed layer 4
Side is provided with solder bump 6 provided with layer 5, the top of layer 5 that connects is connect.
The layer 5 that connects is ferrophosphor(us) material, and the solder bump 6 is tin or tin alloy material, the seed metallization
Layer 4 is copper, titanium, tungsten or copper alloy.The thickness for connecing layer 5 is 1-5 μm adjustable, the thickness of the metal seed layer 4 between
Between 100 angstroms to 10000 angstroms, a diameter of 20-300 μm of the solder bump 6.
It is described to connect layer 5 its chemical composition is calculated as by atomic percentage conc with ferrophosphor(us)：Ferro element：85-99%, remaining
For P elements and inevitable impurity.
Fig. 2 is the process chart for preparing above-mentioned bump packaging structure, and the technique is first in chip（Semiconductor substrate）On
Surface forms pad and passivation layer, and passivation layer is overlying on the upper surface beyond chip bonding pad opening；Then gold is formed on pad
Belong to Seed Layer；Formed on metal seed layer and connect layer；Solder bump is formed on layer connecing；Finally remove solder bump surface
Oxide, and reflux solder salient point.The technique detailed process is as follows：First in chip upper surface formation pad and passivation layer,
Pad is typically formed by copper, aluminium, copper alloy or other conductive materials, is mainly used in joint technology so that each integrated in chip
Circuit and external component connection.Passivation layer is formed by the materials such as silica, silicon nitride, silicon oxynitride or their mixture, is used
Circuit in protection chip.It is general that passivation layer is first formed on chip and pad, photoetching process and etch process are recycled, will be blunt
Change pattern layers to form exposed pad opening.It should be noted that the pad and passivation layer of the chip can be chips
Initial pad and initial passivation or transition pad and passivation layer according to formed by needing routing layout design.
Metal seed layer is formed on pad, forming method includes physical vapour deposition (PVD) (PVD) or sputtering；Metal kind
Sublayer is generally copper, titanium, tungsten or copper alloy；The thickness of metal seed layer is typically in the range of between 100 angstroms to 10000 angstroms.
Then formed on the metal seed layer in above-mentioned bonding pad opening and connect layer, the layer that connects is ferrophosphor(us), its
Chemical composition is that iron atom percentage composition is 85-99% adjustable, and remaining is phosphorus and inevitable impurity.Concrete technology can pass through
With plating or the mode of chemical plating, FeP alloys are plated directly on metal seed layer.FeSn can be formed after backflow on interface2Metal
Between compound, rather than common Cu6Sn5Or Ni3Sn4Intermetallic compound.Due to FeSn2The speed of growth it is slow, it is ensured that
Solder layer in salient point is difficult that the weld metal zone brittle intermetallic thing of thickness is quickly consumed and formed during prolonged use,
So as to improve the reliability for encapsulating mutual disjunctor.Fig. 3 is FeSn on FeP/SnAgCu interfaces2The growth of intermetallic compound is moved
Force diagram, it can be seen that its speed of growth is far below NiP/SnAgCu interfaces Ni3Sn4The speed of growth.
Then solder bump is formed on interfacial reaction layer, the method for forming solder bump can be using plating, screen printing
Brush plants the modes such as ball.The solder used is pure tin or tin alloy, such as sn-ag alloy, gun-metal, SAC.
Finally, the oxide on solder bump surface, and reflux solder salient point are removed, bump packaging structure of the present invention is formed.
Examples provided above is only the mode illustrated, is not considered as limiting the scope of the present invention, appoints
What technique according to the invention scheme and its inventive concept are subject to equivalent substitution or the method for change, should all cover the present invention's
Within protection domain.
Claims (3)
1. a kind of be used as the bump packaging structure for connecing layer using FeP alloys, it is characterised in that：The bump packaging structure includes partly leading
Body substrate, enclosure cavity structure and solder bump, the enclosure cavity structure include metal seed layer and connect
Layer；Wherein：The layer that connects is ferrophosphor(us) material, and the solder bump is tin or tin alloy material, the seed metallization
Layer is copper, titanium, tungsten or copper alloy；It is described to connect layer its chemical composition is calculated as by atomic percentage conc with ferrophosphor(us)：Ferro element：
85-99%, remaining is P elements and inevitable impurity.
2. according to claim 1 be used as the bump packaging structure for connecing layer using FeP alloys, it is characterised in that：It is described to connect
The thickness of layer is 1-5 μm adjustable, and the thickness of the metal seed layer is between 100 angstroms to 10000 angstroms, the solder bump
A diameter of 20-300 μm.
3. according to claim 1 be used as the bump packaging structure for connecing layer using FeP alloys, it is characterised in that：It is described convex
Point encapsulating structure also includes pad and passivation layer, and the pad and passivation layer are located at the upper surface of the Semiconductor substrate, described
Passivation layer is overlying on the upper surface beyond Semiconductor substrate bonding pad opening；Metal seed layer is provided with above the bonding pad opening, it is described
Provided with layer is connect above metal seed layer, described connect is provided with solder bump above layer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310416014.7A CN104465574B (en) | 2013-09-12 | 2013-09-12 | It is a kind of that the bump packaging structure for connecing layer is used as using FeP alloys |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310416014.7A CN104465574B (en) | 2013-09-12 | 2013-09-12 | It is a kind of that the bump packaging structure for connecing layer is used as using FeP alloys |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN104465574A CN104465574A (en) | 2015-03-25 |
| CN104465574B true CN104465574B (en) | 2017-09-26 |
Family
ID=52911392
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201310416014.7A Active CN104465574B (en) | 2013-09-12 | 2013-09-12 | It is a kind of that the bump packaging structure for connecing layer is used as using FeP alloys |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN104465574B (en) |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5422161A (en) * | 1977-07-20 | 1979-02-19 | Toshiba Corp | Semiconductor device |
| CN101090099A (en) * | 2006-06-12 | 2007-12-19 | 中芯国际集成电路制造(上海)有限公司 | Solder lug and manufacturing method thereof |
| CN101211878A (en) * | 2006-12-28 | 2008-07-02 | 国际商业机器公司 | Interconnection structure and its forming method |
| CN101425489A (en) * | 2007-10-31 | 2009-05-06 | 中国科学院金属研究所 | Solder convex point connected metal layer in microelectronic package and use thereof |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2012054359A (en) * | 2010-08-31 | 2012-03-15 | Toshiba Corp | Semiconductor device and manufacturing method of semiconductor device |
-
2013
- 2013-09-12 CN CN201310416014.7A patent/CN104465574B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5422161A (en) * | 1977-07-20 | 1979-02-19 | Toshiba Corp | Semiconductor device |
| CN101090099A (en) * | 2006-06-12 | 2007-12-19 | 中芯国际集成电路制造(上海)有限公司 | Solder lug and manufacturing method thereof |
| CN101211878A (en) * | 2006-12-28 | 2008-07-02 | 国际商业机器公司 | Interconnection structure and its forming method |
| CN101425489A (en) * | 2007-10-31 | 2009-05-06 | 中国科学院金属研究所 | Solder convex point connected metal layer in microelectronic package and use thereof |
Non-Patent Citations (1)
| Title |
|---|
| 锌铁磷合金电镀的发展现状;张昭，李劲风，舒余德，张鉴清，曹楚南;《电镀与涂饰》;20001031;第19卷(第5期);第32-37页 * |
Also Published As
| Publication number | Publication date |
|---|---|
| CN104465574A (en) | 2015-03-25 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US8314500B2 (en) | Interconnections for flip-chip using lead-free solders and having improved reaction barrier layers | |
| US9607936B2 (en) | Copper bump joint structures with improved crack resistance | |
| TWI440106B (en) | Flip-chip interconnect structure | |
| CN102222647B (en) | Semiconductor die and method of manufacturing semiconductor feature | |
| US9373596B2 (en) | Passivated copper chip pads | |
| EP1148548A2 (en) | Method of forming lead-free bump interconnections | |
| US20110101519A1 (en) | Robust Joint Structure for Flip-Chip Bonding | |
| US20050017376A1 (en) | IC chip with improved pillar bumps | |
| CN102237317A (en) | Integrated circuit element and packaging component | |
| TW201133748A (en) | Integrated circuit devices and flip-chip assemblies | |
| CN101241889A (en) | Under bump metallurgy structure of a package and method of making same | |
| JP2003338517A (en) | Method of forming lead-free solder alloy on substrate | |
| US11121101B2 (en) | Flip chip packaging rework | |
| CN104465573B (en) | It is a kind of that the cylindrical bump packaging structure of reaction interface layer is used as using FeNi alloys or FeNiP alloys | |
| CN101194361A (en) | Layer sequence and method of manufacturing a layer sequence | |
| TWI220308B (en) | Under bump metallurgic layer | |
| JP5476926B2 (en) | Manufacturing method of semiconductor device | |
| JP2007123577A (en) | Semiconductor device | |
| CN104465574B (en) | It is a kind of that the bump packaging structure for connecing layer is used as using FeP alloys | |
| CN203434149U (en) | Cylindrical salient-point packaging structure having FeNi alloy or FeNiP alloy-based reaction interface layer | |
| TW201225209A (en) | Semiconductor device and method of confining conductive bump material with solder mask patch | |
| TWI502706B (en) | Robust joint structure for flip-chip bonding | |
| TW200419748A (en) | Under bump metallurgy and flip chip | |
| Arshad et al. | Under bump metallurgy (UBM)-A technology review for flip chip packaging | |
| KR101313690B1 (en) | Method for fabricating bonding structure of semiconductor device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |