CN203434149U - Cylindrical salient-point packaging structure having FeNi alloy or FeNiP alloy-based reaction interface layer - Google Patents
Cylindrical salient-point packaging structure having FeNi alloy or FeNiP alloy-based reaction interface layer Download PDFInfo
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- CN203434149U CN203434149U CN201320567736.8U CN201320567736U CN203434149U CN 203434149 U CN203434149 U CN 203434149U CN 201320567736 U CN201320567736 U CN 201320567736U CN 203434149 U CN203434149 U CN 203434149U
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- alloy
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- interface layer
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
Abstract
The utility model, which belongs to the semiconductor device packaging field, discloses a cylindrical salient-point packaging structure having a FeNi alloy or FeNiP alloy-based reaction interface layer. The packaging structure comprises a semiconductor substrate, conductive metal columns, an oxide layer, a reaction interface layer and solder salient points. A welding plate and a passivation layer are arranged at the upper surface of the semiconductor substrate; the conductive metal columns are arranged above the welding plate opening and are made of copper or copper alloy; the sides of the conductive metal columns are coated with the oxide layer; the reaction interface layer are arranged above the conductive metal columns and are made of FeNi alloy or FeNiP alloy; and the solder salient points are arranged above the reaction interface layer and are made of tin or tin alloy. Because of utilization of the FeNi alloy or FeNiP alloy, characteristics of good weldability, slow interface layer growing speed, and changeable thermal expansion coefficient based on alloy component adjustment can be realized, thereby improving mechanical, electrical and thermal properties and service reliability of a mutual connector.
Description
Technical field
The utility model relates to semiconductor device packaging technique field, is specifically related to a kind of FeNi of usining alloy or FeNiP alloy as the cylindrical bump packaging structure of reaction interface layer.
Background technology
In recent years, due to the encapsulation of the chip future development to high power, high density, frivolous and microminiaturization, bump packaging structure has become current most widely used encapsulating structure.The interconnection process of bump packaging structure is generally: first on chip, make solder bump, then chip bump is aimed to the metallized pads on metallized ceramic or multilayer ceramic substrate, carry out Reflow Soldering under protective atmosphere and suitable temperature.Existing bump packaging structure generally adopts copper and mickel as interfacial reaction layer, but along with the raising day by day of packaging density, the size of soldered ball becomes more and more less, and between interface metal, the fragility of compound also becomes more and more serious to the impact of interconnection body reliability.Though copper as interfacial reaction layer have conductivity high and and scolder between excellent advantages such as wetability, can realize good metallurgical binding, but also exist simultaneously, Cu layer too fast such as boundary layer growth consume too fast, easily form Kirkendall hole and owing to causing the large defects such as stress with not mating of chip chamber thermal coefficient of expansion.Nickel can effectively stop the diffusion of Cu as interfacial reaction layer, and there is the advantages such as simple to operate, cost is low, but still have the defects such as thermal stress that make solder joint embrittlement and produce with chip chamber thermal expansion coefficient difference such as black pad, Kirkendall hole, boundary layer Fast Growth.Having the more exploration of the interfacial reaction layer of dominance energy has become one of hot issue of current Electronic Packaging area research, as domestic and international many scholar's wishs are improved the performance of existing NiP layer by adding other alloying element to form the approach of binary or multi-element layers.
Utility model content
The purpose of this utility model is the good solderability of utilizing FeNi alloy or FeNiP alloy to have, the characteristic that the boundary layer speed of growth is slow and alloy thermal coefficient of expansion can change by alloying component adjustment, a kind of FeNi of usining alloy or the FeNiP alloy cylindrical bump packaging structure as interfacial reaction layer is provided, improves mechanics, electricity, thermal property and the service reliability of interconnection body.
For achieving the above object, the technical scheme that the utility model adopts is as follows:
A kind ofly using FeNi alloy or the FeNiP alloy cylindrical bump packaging structure as reaction interface layer, this cylindrical bump packaging structure comprises Semiconductor substrate, conducting metal post, oxide layer, reaction interface layer and solder bump, the upper surface of described Semiconductor substrate is provided with pad and passivation layer, and described passivation layer is overlying on the upper surface beyond bonding pad opening in Semiconductor substrate; Described bonding pad opening top is provided with metal seed layer, and metal seed layer is provided with conducting metal post, and the material of described conducting metal post is copper or copper alloy; The top of described conducting metal post is provided with reaction interface layer, and the material of reaction interface layer is iron-nickel alloy or alloy of iron, nickel, phosphorus; Described reaction interface layer top is provided with solder bump, and the material of solder bump is tin or ashbury metal.
The chemical composition of described iron-nickel alloy is counted by atomic percentage conc: ferro element is that 25-85% is adjustable, and all the other are nickel element and inevitable impurity.
The chemical composition of described alloy of iron, nickel, phosphorus is counted by atomic percentage conc: ferro element is that 25-85% is adjustable, and nickel element is that 14%-74% is adjustable, and iron, both atomic percentage conc sums of nickel are 85%-99%, and all the other are P elements and inevitable impurity.
The thickness of described reaction interface layer is that 1-5 μ m is adjustable.
The thickness of described conducting metal post is that 30-70 μ m is adjustable.
The side of described conducting metal post can also be coated oxide layer.
Between described conducting metal post and reaction interface layer, can also be embedded with transition zone, described transition zone is nickel dam, and the thickness of described nickel dam is that 0.5-1.5 μ m is adjustable.
Described seed metallization layer material is copper or titanium, the thickness of metal seed layer between 100 dusts between 10000 dusts.
The diameter of described solder bump is 10-300 μ m.
Compared with prior art, the beneficial effects of the utility model are:
1, between FeNi alloy or FeNiP alloy and Sn base lead-free solder, there is good wettability.The intermetallic compound FeSn that FeNi alloy or FeNiP alloy and Sn parent metal interfacial reaction generate
2there is the advantages such as the speed of growth is slow, good compactness.Select FeNi alloy or FeNiP alloy to replace in conventional art Cu, Ni or NiP alloy as reaction interface layer, can suppress the Fast Growth of the intermetallic compounds layer that interfacial reaction produces and connect the quick consumption of layer, increase substantially the service life of cylindrical bump packaging structure.
2, the thermal coefficient of expansion of FeNi alloy or FeNiP alloy can be adjusted by changing alloying component, thereby reduces the thermal mismatching of interconnect package cylindrical bump packaging structure, reduces thermal stress, improves the reliability of cylindrical bump packaging structure.
Accompanying drawing explanation
Fig. 1 is the structural representation of a kind of cylindrical bump packaging structure of the utility model.
Fig. 2 is the structural representation of a kind of cylindrical bump packaging structure of the utility model.
Fig. 3 is the embodiment flow chart of a kind of cylindrical bump packaging structure of the utility model.
Fig. 4 is the stereoscan photograph at Fe30Ni/Sn3.5Ag0.7Cu interface.
Fig. 5 is the relation curve of heterogeneity FeNi alloy and Sn3.5Ag0.7Cu interface formation intermetallic compound IMC thickness and aging time.
Fig. 6 is FeSn on FeNiP/Sn3.8Ag0.7Cu interface
2the growth kinetics curve of intermetallic compound.
In figure: 1-Semiconductor substrate; 2-pad; 3-passivation layer; 4-metal seed layer; 5-conducting metal post; 6-transition zone; 7-reaction interface layer; 8-solder bump; 9-oxide layer.
Embodiment
Below in conjunction with drawings and Examples, the utility model is described in further detail.
Fig. 1 is a preferred version of a kind of cylindrical bump packaging structure of the utility model, this cylindrical bump packaging structure comprises Semiconductor substrate 1, conducting metal post 5, oxide layer 9, reaction interface layer 7 and solder bump 8, the upper surface of described Semiconductor substrate 1 is provided with pad 2 and passivation layer 3, and described passivation layer 3 is overlying on the upper surface beyond pad 2 openings in Semiconductor substrate 1; Described pad 2 opening tops are provided with metal seed layer 4, and metal seed layer 4 materials are copper or titanium; Metal seed layer 4 is provided with conducting metal post 5, and the material of described conducting metal post 5 is copper or copper alloy; The top of described conducting metal post 5 is provided with reaction interface layer 7, and the material of reaction interface layer 7 is iron-nickel alloy or alloy of iron, nickel, phosphorus; Described reaction interface layer 7 top are provided with solder bump 8, and the material of solder bump 8 is tin or ashbury metal; The side of described conducting metal post 5 can also be coated oxide layer 9.
The chemical composition of described iron-nickel alloy is counted by atomic percentage conc: ferro element is that 25-85% is adjustable, and all the other are nickel element and inevitable impurity.The chemical composition of described alloy of iron, nickel, phosphorus is counted by atomic percentage conc: ferro element is that 25-85% is adjustable, and nickel element is that 14%-74% is adjustable, and iron, both atomic percentage conc sums of nickel are 85%-99%, and all the other are P elements and inevitable impurity.
The thickness of described reaction interface layer 7 is that 1-5 μ m is adjustable, and the thickness of described conducting metal post 5 is that 30-70 μ m is adjustable, and the thickness of described metal seed layer 4 is between 100 dusts between 10000 dusts, and the diameter of described solder bump 8 is 10-300 μ m.
Fig. 2 is another preferred version of a kind of cylindrical bump packaging structure of the utility model, be with the difference of scheme shown in Fig. 1, between described conducting metal post 5 and reaction interface layer 7, be embedded with transition zone 6, described transition zone 6 is nickel dam, and the thickness of described nickel dam is that 0.5-1.5 μ m is adjustable.
Fig. 3 is preparation technology's flow chart of the above-mentioned cylindrical bump packaging structure of the utility model, and first this technique form pad and passivation layer at chip (Semiconductor substrate) upper surface, and passivation layer is overlying on the upper surface beyond chip bonding pad opening; Then on pad, form metal seed layer; On metal seed layer, form conducting metal post; Then on conducting metal post, form interfacial reaction layer, between conducting metal post and interfacial reaction layer, can be embedded with transition zone; On interfacial reaction layer, form solder bump; In exposed conducting metal post outside, form oxide layer; Finally remove the oxide on solder bump surface, and reflux solder salient point.
For further illustrating the advantage of the utility model encapsulating structure, with method for packing in the present embodiment, the utility model encapsulating structure is described further.
First at chip upper surface, form pad and passivation layer, pad is generally formed by copper, aluminium, copper alloy or other electric conducting materials, be mainly used in joint technology so that separately the integrated circuit in chip be connected with external component.Passivation layer is formed by the materials such as silica, silicon nitride, silicon oxynitride or their mixture, for the protection of the circuit in chip.General first on chip and pad, form passivation layer, recycling photoetching process and etch process, by passivation layer pattern to form exposed pad opening.It should be noted that, the pad of described chip and passivation layer can be initial pad and the initial passivation of chip, and can be also needs according to circuit layout-design the transition pad and the passivation layer that form.
On pad, form metal seed layer, formation method comprises physical vapour deposition (PVD) (PVD) or sputter; Metal seed layer is copper or titanium; The thickness of metal seed layer between 100 dusts between 10000 dusts.
Then on the metal seed layer in above-mentioned bonding pad opening, form conducting metal post, concrete technology can be electroplated or the mode of chemical plating by use.The material of conducting metal post is copper or copper alloy, and the alloy that for example can be comprised of copper and chromium forms.The thickness of conducting metal post is generally between 30 μ m-70 μ m.
Then on conducting metal post, form transition zone, described transition zone is nickel dam, and the thickness of nickel dam is 0.5-1.5 μ m.The suitable nickel transition zone of thickness can be strengthened the bond strength between iron-nickel alloy interfacial reaction layer and conducting metal post, while can stop the copper in conducting metal post when temperature is higher, to pass iron-nickel alloy interfacial reaction layer directly and solder reaction forms thick CuSn intermetallic compound, affects properties of product.
Then on transition zone, form interfacial reaction layer, can also not adopt transition zone, directly on conducting metal post, form interfacial reaction layer.Described reaction interface layer is iron-nickel alloy or alloy of iron, nickel, phosphorus, and in iron-nickel alloy, iron atom percentage composition is 25-85%; In alloy of iron, nickel, phosphorus, iron atom percentage composition is 25-85%, and nickle atom percentage composition is 14-74%, and iron and nickel atomic percentage conc sum are 85%-99%, and all the other are P elements and inevitable impurity.Concrete technology can be electroplated or the mode of chemical plating by use, as: direct chemical plating 55Fe43Ni2P alloy on copper post, or on Ni transition zone, electroplate Fe30Ni alloy.On backflow rear interface, can form FeSn
2intermetallic compound, rather than common Cu
6sn
5or Ni
3sn
4intermetallic compound.Due to FeSn
2the speed of growth slow, guaranteed that the solder layer in salient point is difficult for for a long time in use procedure, being consumed fast and forming compound layer between thick brittle metal, thereby can improve the reliability of packaging interconnection body.Fig. 4 is the stereoscan photograph at Fe30Ni/Sn3.5Ag0.7Cu interface, can find out that the intermetallic compounds layer forming on interface is FeSn
2layer; Fig. 5 is the relation curve of heterogeneity FeNi alloy and Sn3.5Ag0.7Cu interface formation intermetallic compound IMC thickness and aging time, can find out that the speed of growth of compound between FeNi/Sn3.5Ag0.7Cu interface metal is far below Cu/Sn3.5Ag0.7Cu interface.Fig. 6 is FeSn on FeNiP/Sn3.8Ag0.7Cu interface
2the growth kinetics curve of intermetallic compound, can find out that its speed of growth is far below Ni on NiP/Sn3.8Ag0.7Cu interface
3sn
4the speed of growth.
Then on interfacial reaction layer, form solder bump, the method that forms solder bump can adopt plating, silk screen printing or plant the modes such as ball.The scolder adopting is for being pure tin or ashbury metal, as sn-ag alloy, gun-metal, SAC alloy etc.
Then in exposed conducting metal post outside, form oxide layer.The material adopting due to conducting metal post is generally copper and copper alloy, utilizes copper oxidizable characteristic in air, and the mode of toasting by aerobic makes exposed conducting metal post form oxide layer around, makes copper post surface insulation.
Finally, remove the oxide on solder bump surface, and reflux solder salient point, cylindrical bump packaging structure formed.
The embodiment more than providing is only the mode of explaining, and should not think scope of the present invention restriction, anyly according to technical scheme of the present invention and inventive concept thereof, is equal to the method for replacing or changing, within all should being encompassed in protection scope of the present invention.
Claims (6)
1. using FeNi alloy or the FeNiP alloy cylindrical bump packaging structure as reaction interface layer for one kind, it is characterized in that: this cylindrical bump packaging structure comprises Semiconductor substrate, conducting metal post, oxide layer, reaction interface layer and solder bump, the upper surface of described Semiconductor substrate is provided with pad and passivation layer, and described passivation layer is overlying on the upper surface beyond bonding pad opening in Semiconductor substrate; Described bonding pad opening top is provided with metal seed layer, and metal seed layer is provided with conducting metal post, and the material of described conducting metal post is copper or copper alloy; The top of described conducting metal post is provided with reaction interface layer, and the material of reaction interface layer is iron-nickel alloy or alloy of iron, nickel, phosphorus; Described reaction interface layer top is provided with solder bump, and the material of solder bump is tin or ashbury metal.
2. cylindrical bump packaging structure according to claim 1, is characterized in that: the thickness of described reaction interface layer is that 1-5 μ m is adjustable; The thickness of described conducting metal post is that 30-70 μ m is adjustable; The diameter of described solder bump is 10-300 μ m.
3. cylindrical bump packaging structure according to claim 1, is characterized in that: the coated oxide layer in side of described conducting metal post.
4. cylindrical bump packaging structure according to claim 1, is characterized in that: between described conducting metal post and reaction interface layer, be embedded with transition zone, described transition zone is nickel dam.
5. cylindrical bump packaging structure according to claim 4, is characterized in that: the thickness of described nickel dam is that 0.5-1.5 μ m is adjustable.
6. cylindrical bump packaging structure according to claim 1, is characterized in that: described seed metallization layer material is copper or titanium, the thickness of metal seed layer between 100 dusts between 10000 dusts.
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Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN104465573A (en) * | 2013-09-12 | 2015-03-25 | 中国科学院金属研究所 | Columnar bump packaging structure with FeNi alloy or FeNiP alloy acting as reaction interface layer |
CN114649287A (en) * | 2022-05-19 | 2022-06-21 | 甬矽半导体(宁波)有限公司 | Chip manufacturing method, chip connecting method and chip |
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2013
- 2013-09-12 CN CN201320567736.8U patent/CN203434149U/en not_active Expired - Fee Related
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN104465573A (en) * | 2013-09-12 | 2015-03-25 | 中国科学院金属研究所 | Columnar bump packaging structure with FeNi alloy or FeNiP alloy acting as reaction interface layer |
CN114649287A (en) * | 2022-05-19 | 2022-06-21 | 甬矽半导体(宁波)有限公司 | Chip manufacturing method, chip connecting method and chip |
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Granted publication date: 20140212 Termination date: 20190912 |
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CF01 | Termination of patent right due to non-payment of annual fee |