CN207834271U - A kind of encapsulating structure of the golden chip of the wafer level back of the body - Google Patents
A kind of encapsulating structure of the golden chip of the wafer level back of the body Download PDFInfo
- Publication number
- CN207834271U CN207834271U CN201721876680.9U CN201721876680U CN207834271U CN 207834271 U CN207834271 U CN 207834271U CN 201721876680 U CN201721876680 U CN 201721876680U CN 207834271 U CN207834271 U CN 207834271U
- Authority
- CN
- China
- Prior art keywords
- layer
- chip
- silicon substrate
- golden
- gold
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
Abstract
The utility model discloses the encapsulating structures that a kind of wafer level carries on the back golden chip, belong to technical field of semiconductor encapsulation.Its silicon substrate ontology（10）Front be equipped with several chip electrodes（11）, chip insulation layer（14）With front protecting layer（18）, the front protecting layer（18）Cover chip insulation layer（14）And open up front protecting layer opening（181）Exposed chip electrode again（11）, chip electrode（11）Upper surface be arranged metal salient point（20）；The silicon substrate ontology（10）The back side be equipped with back of the body layer gold, which, which passes through, carries on the back golden adhesive layer（43）With silicon substrate ontology（10）Back adhesive connection.Plastic packaging layer（60）Encapsulating back of the body layer gold and silicon substrate ontology（10）Exposed surface, and open up plastic packaging layer opening（601）Expose the back of the body layer gold back side.The encapsulating structure of the utility model is simple, meets the small golden demand of the chip back of the body, meets following development trend of embedded encapsulation.
Description
Technical field
The utility model is related to the encapsulating structures that a kind of wafer level carries on the back golden chip, belong to technical field of semiconductor encapsulation.
Background technology
In recent years, embedded encapsulation Embedded Package are increasingly paid attention to by industry.Embedded encapsulation is often
Have better thermal management and reliable sexual clorminance compared with other encapsulating structures.In this packaging body, the back side of chip usually into
Row is ground and is metallized to realize the heat dissipation performance for reducing power attenuation or hoisting power chip, and is embedded in IC substrates
Middle realization final encapsulation.
In embedded packaging structure, a pole of the metal layer on back as device, it usually needs be resistant to the work of laser ablation
Skill, to the golden thickness of the back of the body, more stringent requirements are proposed for this.
At this stage, chip back of the body gold process mostly uses greatly noble metal structures, the noble metals higher price such as including gold, silver, market
Fluctuation is big, and the cost of the manufacturing is higher.Back of the body gold, because of operational characteristic, has more during vapor deposition in reaction chamber
Metal residual, this more exacerbates the promotion of cost.
In addition, in each application field of semiconductor, highly integrated miniaturization and lightening package requirements constantly propose,
Embedded encapsulation is also such.Small-sized packaging body during the welding process, the lighter in weight of its own, easily in welding process
In because phenomenon of solder rising leads to short-circuit failure, or in embedded high density packaging body, due to displacement and other chips contact
Entire packaging body is caused to be scrapped.
Invention content
Purpose of the utility model is to overcome the above-mentioned shortcomings and provide the encapsulating structures that a kind of wafer level carries on the back golden chip.
A kind of encapsulating structure of the golden chip of the wafer level back of the body of the utility model, the front of silicon substrate ontology is equipped with several chips
Electrode and function induction zone and chip insulation layer, the chip insulation layer covering silicon substrate ontology and exposed chip electrode, simultaneously
The nubbin of the dicing lane of the chip insulation layer covering silicon substrate ontology.The scribing of the chip insulation layer covering silicon substrate ontology
The nubbin in road simultaneously extends outward, forms chip insulation layer extension.
Further include front protecting layer and plastic packaging layer, the front protecting layer covers chip insulation layer and opens up front protecting layer
Be open exposed chip electrode again, metal salient point is arranged in the upper surface of the chip electrode, the metal salient point exposes front
Protective layer,
The golden adhesive layer of the back of the body and layers of copper are set gradually at the back side of the silicon substrate ontology, forms back of the body layer gold, the back of the body gold bonds
The thickness of layer is not more than greatly 2 microns, and the thickness of the back of the body layer gold is more than 5 microns, and the back of the body layer gold is by carrying on the back golden adhesive layer and silicon
The back adhesive of basic body connects,
The exposed surface of the plastic packaging layer encapsulating back of the body layer gold and silicon substrate ontology opens up plastic packaging layer to chip insulation layer extension
Opening, the plastic packaging layer opening partially or fully expose the back of the body layer gold back side, and the exposed surface at the back of the body layer gold back side continues and is embedded in
Other IC in pcb board/substrate are interconnected.
Optionally, the material of the metal salient point is copper, tin, sn-ag alloy or Ni/Au, Ni/Pd/Au composite construction.
Optionally, the back-protective layer I and back-protective layer II be with lithographic features comprising filler or be free of
The high molecular material of filler.
Optionally, the metal salient point height is at 5 microns to 50 microns.
Advantageous effect
1）The encapsulating structure of the utility model is simple, and resin front protecting layer is formed in chip side wall, meets the small chip back of the body
The demand of gold encapsulation meets following development trend of embedded encapsulation；
2）The utility model is used as back of the body layer gold using common metal copper, under the premise of meeting heat dissipation and electrode conduction, in fact
The larger back of the body layer gold of existing thickness, can provide lower power attenuation, can significantly increase conductive and heat-sinking capability, and save material
Cost.
Description of the drawings：
Fig. 1 and Fig. 2 is a kind of schematic diagram of the encapsulating structure embodiment of the golden chip of the wafer level back of the body of the utility model；
In figure：
Chip electrode 11
Dicing lane 12
Chip insulation layer 14
Chip insulation layer extension 141
Back side silicon process face 13
Front protecting layer 18
Front protecting layer opening 181
Metal salient point 20
Back of the body gold adhesive layer 43
Back-protective layer I 51
Back-protective layer II 52
Plastic packaging layer 60
Plastic packaging layer opening 601.
Specific implementation mode
Specific embodiment of the present utility model is described in detail below in conjunction with the accompanying drawings.
Embodiment
A kind of encapsulating structure of the golden chip of back of the body of the utility model, as shown in Figure 1.The front of its silicon substrate ontology 10 is equipped with several
A chip electrode 11 and function induction zone（It is not shown）, chip insulation layer 14 covers silicon substrate ontology 10 and exposed chip electrode 11
Front, while chip insulation layer 14 covers the nubbin of the dicing lane 12 of silicon substrate ontology 10.Front protecting layer 18 covers chip
Insulating layer 14 simultaneously opens up the exposed chip electrode 11 again of front protecting layer opening 181, and the upper surface setting of chip electrode 11 is exposed
The metal salient point 20 of front protecting layer 18, the material of metal salient point 20 are that copper, tin, sn-ag alloy or Ni/Au, Ni/Pd/Au etc. are multiple
Close structure.20 height of metal salient point is at 5 microns to 50 microns.Chip electrode 11 realizes the defeated of electric signal by metal salient point 20
Enter/output function.
The back side of the silicon substrate ontology 10 is equipped with back of the body layer gold, which is chromium-copper composite layer, and layers of copper 40 is thicker, entire back of the body gold
The thickness of layer is more than 5 microns.Wherein layers of chrome is the golden adhesive layer 43 of the back of the body, and thickness is not more than greatly 2 microns.The back of the body layer gold is by carrying on the back gold
Adhesive layer 43 is connect with the back adhesive of silicon substrate ontology 10.
Exposed surface to the chip insulation layer of plastic packaging material encapsulating back of the body layer gold and silicon substrate ontology 10 containing high molecular material extends
Portion 141, and plastic packaging layer opening 601 is opened up, the back of the body layer gold back side, the back of the body layer gold back side are exposed in 601 part of plastic packaging layer opening
Exposed surface continuation interconnected with other IC being embedded in pcb board/substrate, while heat radiation performance.As shown in Figure 1.
Exposed surface to the chip insulation layer of plastic packaging material encapsulating back of the body layer gold and silicon substrate ontology 10 containing high molecular material extends
Portion 141, and plastic packaging layer opening 601 is opened up, the plastic packaging layer opening 601 all exposes the back of the body layer gold back side, the back of the body layer gold back side
Exposed surface continuation interconnected with other IC being embedded in pcb board/substrate, while heat radiation performance.As shown in Figure 2.
Above-described specific implementation mode, to the purpose of this utility model, technical solution and advantageous effect carried out into
It is described in detail to one step, it should be understood that the foregoing is merely specific embodiment of the present utility model, is not used to
Limit the scope of protection of the utility model.Within the spirit and principle of the utility model, any modification for being made equally is replaced
It changes, improve, should be included within the scope of protection of this utility model.
Claims (3)
1. a kind of encapsulating structure of the golden chip of the wafer level back of the body, silicon substrate ontology（10）Front be equipped with several chip electrodes（11）
With function induction zone and chip insulation layer（14）, the chip insulation layer（14）Cover silicon substrate ontology（10）And exposed chip electricity
Pole（11）, which is characterized in that
The chip insulation layer（14）Cover silicon substrate ontology（10）Dicing lane（12）Nubbin and extend outward, formed
Chip insulation layer extension（141）,
It further include front protecting layer（18）With plastic packaging layer（60）, the front protecting layer（18）Cover chip insulation layer（14）And it opens
If front protecting layer is open（181）Exposed chip electrode again（11）, in the chip electrode（11) metal is arranged in upper surface
Salient point（20）, the metal salient point（20）Expose front protecting layer（18）,
In the silicon substrate ontology（10）The back side set gradually the golden adhesive layer of the back of the body（43）And layers of copper（40）, back of the body layer gold is formed, it is described
The golden adhesive layer of the back of the body（43）Thickness greatly be not more than 2 microns, it is described the back of the body layer gold thickness be more than 5 microns, the back of the body layer gold passes through the back of the body
Golden adhesive layer（43）With silicon substrate ontology（10）Back adhesive connection,
The plastic packaging layer（60）Encapsulating back of the body layer gold and silicon substrate ontology（10）Exposed surface to chip insulation layer extension（141）, and
Open up plastic packaging layer opening（601）, the plastic packaging layer opening（601）Partially or fully expose the back of the body layer gold back side, the back of the body layer gold back of the body
The exposed surface continuation in face is interconnected with other IC being embedded in pcb board/substrate.
2. the encapsulating structure of the golden chip of the wafer level back of the body according to claim 1, which is characterized in that the metal salient point（20）
Material be copper, tin, sn-ag alloy or Ni/Au, Ni/Pd/Au composite construction.
3. the encapsulating structure of the golden chip of the wafer level back of the body according to claim 1, which is characterized in that the metal salient point（20）
Height is at 5 microns to 50 microns.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201721876680.9U CN207834271U (en) | 2017-12-28 | 2017-12-28 | A kind of encapsulating structure of the golden chip of the wafer level back of the body |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201721876680.9U CN207834271U (en) | 2017-12-28 | 2017-12-28 | A kind of encapsulating structure of the golden chip of the wafer level back of the body |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN207834271U true CN207834271U (en) | 2018-09-07 |
Family
ID=63390255
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201721876680.9U Active CN207834271U (en) | 2017-12-28 | 2017-12-28 | A kind of encapsulating structure of the golden chip of the wafer level back of the body |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN207834271U (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107910305A (en) * | 2017-12-28 | 2018-04-13 | 江阴长电先进封装有限公司 | A kind of encapsulating structure and its method for packing of the golden chip of the wafer level back of the body |
| CN109904082A (en) * | 2019-03-28 | 2019-06-18 | 中国科学院微电子研究所 | A kind of substrate baried type three-dimensional system level packaging method and structure |
-
2017
- 2017-12-28 CN CN201721876680.9U patent/CN207834271U/en active Active
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107910305A (en) * | 2017-12-28 | 2018-04-13 | 江阴长电先进封装有限公司 | A kind of encapsulating structure and its method for packing of the golden chip of the wafer level back of the body |
| CN107910305B (en) * | 2017-12-28 | 2023-08-29 | 江阴长电先进封装有限公司 | Packaging structure and packaging method of wafer-level back gold chip |
| CN109904082A (en) * | 2019-03-28 | 2019-06-18 | 中国科学院微电子研究所 | A kind of substrate baried type three-dimensional system level packaging method and structure |
| CN109904082B (en) * | 2019-03-28 | 2020-12-22 | 中国科学院微电子研究所 | Substrate embedded type three-dimensional system-in-package method and structure |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| TWI358799B (en) | Semiconductor package substrate and method of form | |
| CN104253105A (en) | Semiconductor device and method of forming low profile 3D fan-out package | |
| CN107910305A (en) | A kind of encapsulating structure and its method for packing of the golden chip of the wafer level back of the body | |
| CN107170720A (en) | A kind of stacked package two-side radiation power model | |
| TW571374B (en) | System in package structures | |
| CN207834271U (en) | A kind of encapsulating structure of the golden chip of the wafer level back of the body | |
| CN101673790A (en) | Light-emitting diode and manufacturing method thereof | |
| CN204179102U (en) | A kind of flip LED chips of high reliability and LED component thereof | |
| CN102610583A (en) | Package carrier and method for manufacturing the same | |
| CN107910307A (en) | The encapsulating structure and its method for packing of a kind of semiconductor chip | |
| CN207765435U (en) | A kind of encapsulating structure of upside-down mounting welding core | |
| CN101546737B (en) | Package structure of compound semiconductor component and manufacturing method thereof | |
| CN111933784A (en) | Ceramic packaging method of laser chip and ceramic packaging chip structure | |
| CN102403236B (en) | The semiconductor device of chip exposed and production method thereof | |
| CN210073809U (en) | Crimping type IGBT internal packaging structure | |
| CN108091646B (en) | Packaging structure of ultraviolet LED antistatic silicon substrate | |
| US20130000712A1 (en) | Solar cell device and packaging method thereof | |
| CN207038508U (en) | A kind of stacked package two-side radiation power model | |
| CN105226040B (en) | A kind of encapsulating structure and its method for packing of silicon substrate module | |
| CN204927275U (en) | Packaging structure of low -cost silica -based module | |
| CN104465573A (en) | Columnar bump packaging structure with FeNi alloy or FeNiP alloy acting as reaction interface layer | |
| CN206789535U (en) | A kind of fan-out package structure of power electronic devices | |
| JP2008010778A (en) | Semiconductor device | |
| CN201066696Y (en) | Encapsulation structure for high-power LED chip and high-power LED lighting part | |
| CN105118817B (en) | A kind of encapsulating structure and its method for packing of inexpensive silicon substrate module |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| GR01 | Patent grant | ||
| GR01 | Patent grant |