JPS5422161A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPS5422161A
JPS5422161A JP8611877A JP8611877A JPS5422161A JP S5422161 A JPS5422161 A JP S5422161A JP 8611877 A JP8611877 A JP 8611877A JP 8611877 A JP8611877 A JP 8611877A JP S5422161 A JPS5422161 A JP S5422161A
Authority
JP
Japan
Prior art keywords
semiconductor device
frilled
wiring
coating
onto
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP8611877A
Other languages
Japanese (ja)
Inventor
Genichi Adachi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP8611877A priority Critical patent/JPS5422161A/en
Publication of JPS5422161A publication Critical patent/JPS5422161A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods

Abstract

PURPOSE: To prevent corrosion of the Al wiring by providing the projection electrode after coating the ethylene fluoride-propylene copolymer film FEP onto the element with an opening frilled.
COPYRIGHT: (C)1979,JPO&Japio
JP8611877A 1977-07-20 1977-07-20 Semiconductor device Pending JPS5422161A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP8611877A JPS5422161A (en) 1977-07-20 1977-07-20 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP8611877A JPS5422161A (en) 1977-07-20 1977-07-20 Semiconductor device

Publications (1)

Publication Number Publication Date
JPS5422161A true JPS5422161A (en) 1979-02-19

Family

ID=13877771

Family Applications (1)

Application Number Title Priority Date Filing Date
JP8611877A Pending JPS5422161A (en) 1977-07-20 1977-07-20 Semiconductor device

Country Status (1)

Country Link
JP (1) JPS5422161A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104465574A (en) * 2013-09-12 2015-03-25 中国科学院金属研究所 Bump packaging structure with FeP alloy acting as soldering layer

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104465574A (en) * 2013-09-12 2015-03-25 中国科学院金属研究所 Bump packaging structure with FeP alloy acting as soldering layer
CN104465574B (en) * 2013-09-12 2017-09-26 中国科学院金属研究所 It is a kind of that the bump packaging structure for connecing layer is used as using FeP alloys

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