CN104616998A - Method for manufacturing wafer level package - Google Patents
Method for manufacturing wafer level package Download PDFInfo
- Publication number
- CN104616998A CN104616998A CN201410839944.8A CN201410839944A CN104616998A CN 104616998 A CN104616998 A CN 104616998A CN 201410839944 A CN201410839944 A CN 201410839944A CN 104616998 A CN104616998 A CN 104616998A
- Authority
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- Prior art keywords
- chip
- layer
- photoresist
- articulamentum
- face
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- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000000034 method Methods 0.000 title claims abstract description 29
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 13
- 229920002120 photoresistant polymer Polymers 0.000 claims abstract description 26
- 238000004806 packaging method and process Methods 0.000 claims abstract description 12
- 239000010410 layer Substances 0.000 claims description 50
- 238000001947 vapour-phase growth Methods 0.000 claims description 12
- 239000011241 protective layer Substances 0.000 claims description 9
- 229910052802 copper Inorganic materials 0.000 claims description 5
- 239000010949 copper Substances 0.000 claims description 5
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 4
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 claims description 4
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 claims description 3
- 229910000881 Cu alloy Inorganic materials 0.000 claims description 2
- YOCUPQPZWBBYIX-UHFFFAOYSA-N copper nickel Chemical compound [Ni].[Cu] YOCUPQPZWBBYIX-UHFFFAOYSA-N 0.000 claims description 2
- 229910052759 nickel Inorganic materials 0.000 claims description 2
- 239000011347 resin Substances 0.000 claims description 2
- 229920005989 resin Polymers 0.000 claims description 2
- 239000002184 metal Substances 0.000 abstract 2
- 238000012858 packaging process Methods 0.000 abstract 1
- 229910000679 solder Inorganic materials 0.000 abstract 1
- 238000010586 diagram Methods 0.000 description 3
- 238000003475 lamination Methods 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 150000001879 copper Chemical class 0.000 description 1
- 238000005538 encapsulation Methods 0.000 description 1
- 238000011900 installation process Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000007747 plating Methods 0.000 description 1
- 230000001681 protective effect Effects 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 238000012163 sequencing technique Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/563—Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16135—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/16145—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
Abstract
The invention relates to a method for manufacturing a wafer level package; the method comprises the steps: forming a first photoresist on a first chip, forming a plurality of first opening parts on the first photoresist and exposing the functional side of the first chip; forming an under-bump metal layer on the functional side exposed at the first opening parts and then removing the first photoresist; connecting functional bumps of a second chip and the under-bump metal layer; forming a filling layer between the first chip and the second chip; forming a connecting layer on the first chip and enabling the top surface of the connecting layer to be higher than the top surface of the second chip; and planting solder balls on the top surface of the connecting layer. The first chip and the second chip are arranged face to face; the connecting layer is formed on the first chip; in the subsequent inverting and packaging process, the formed package structure can be inverted and packaged by utilizing a height difference between the connecting layer on the first chip and the second chip; the package structure is not damaged, that is, the second chip is not damaged during inversion and packaging; and the risk during processing is reduced.
Description
Technical field
The present invention relates to semiconductor making method, particularly relate to a kind of manufacture method of wafer-level packaging.
Background technology
Along with chip functions gets more and more, the requirement for encapsulation is also more and more higher, and upside-down mounting, lamination become trend.While upside-down mounting, lamination, also require that package thickness is as far as possible thin, as far as possible thin when so requiring chip package to a certain extent, thus cause the risk of the course of processing.
Summary of the invention
Provide hereinafter about brief overview of the present invention, to provide about the basic comprehension in some of the present invention.Should be appreciated that this general introduction is not summarize about exhaustive of the present invention.It is not that intention determines key of the present invention or pith, and nor is it intended to limit the scope of the present invention.Its object is only provide some concept in simplified form, in this, as the preorder in greater detail discussed after a while.
The invention provides a kind of manufacture method of wafer-level packaging, the first chip is formed the first photoresist, described first photoresist forms multiple first peristome, expose the functional surfaces of described first chip; Form ubm layer at the functional surfaces exposed from described multiple first peristome, then remove described first photoresist; The function salient point of described second chip is connected with described ubm layer; Packed layer is formed between described first chip and described second chip; Described first chip forms articulamentum, and described articulamentum is layer structure; Plant soldered ball at described articulamentum end face, the end face of described soldered ball is higher than the end face of described second chip.
Compared to prior art, beneficial effect of the present invention at least comprises: the first chip and the second chip are arranged face-to-face, articulamentum is formed again on the first chip, the encapsulating structure formed thus is in follow-up reverse installation process, make use of the difference in height that articulamentum on the first chip and the second chip are formed, just by encapsulating structure upside-down mounting, and can not destroy encapsulating structure, namely can not damage the second chip during upside-down mounting, reduce the risk in the course of processing.
Accompanying drawing explanation
In order to be illustrated more clearly in the embodiment of the present invention or technical scheme of the prior art, be briefly described to the accompanying drawing used required in embodiment or description of the prior art below, apparently, accompanying drawing in the following describes is only some embodiments of the present invention, for those of ordinary skill in the art, under the prerequisite not paying creative work, other accompanying drawing can also be obtained according to these accompanying drawings.
Fig. 1 is the flow chart of the manufacture method of wafer-level packaging of the present invention;
Fig. 2-10 is the substep schematic diagram in the process of the manufacture method adopting wafer-level packaging of the present invention;
Figure 11 is a kind of schematic diagram of the wafer level packaging structure adopting the manufacture method of wafer-level packaging of the present invention to manufacture;
Figure 12 is the another kind of schematic diagram of the wafer level packaging structure adopting the manufacture method of wafer-level packaging of the present invention to manufacture.
Reference numeral:
1-first chip; 2-second chip; 11-ubm layer; 21-function salient point; 3-articulamentum; 4-soldered ball; 5-packed layer; 6-first photoresist; 61-first peristome; 7-second photoresist; 71-second peristome.
Embodiment
For making the object of the embodiment of the present invention, technical scheme and advantage clearly, below in conjunction with the accompanying drawing in the embodiment of the present invention, technical scheme in the embodiment of the present invention is clearly and completely described, obviously, described embodiment is the present invention's part embodiment, instead of whole embodiments.The element described in an accompanying drawing of the present invention or a kind of execution mode and feature can combine with the element shown in one or more other accompanying drawing or execution mode and feature.It should be noted that for purposes of clarity, accompanying drawing and eliminate expression and the description of unrelated to the invention, parts known to persons of ordinary skill in the art and process in illustrating.Based on the embodiment in the present invention, the every other embodiment that those of ordinary skill in the art obtain under the prerequisite not paying creative work, all belongs to the scope of protection of the invention.
In the following embodiment of the present invention, the sequence number of embodiment and/or sequencing are only convenient to describe, and do not represent the quality of embodiment.The description of each embodiment is all emphasized particularly on different fields, in certain embodiment, there is no the part described in detail, can see the associated description of other embodiments.
The present invention discloses a kind of manufacture method of wafer-level packaging, comprise step 10, first chip 1 is formed the first photoresist 6 (as shown in Figure 2), described first photoresist 6 is formed multiple first peristome 61 (see Fig. 3), exposes the functional surfaces of described first chip 1; Step 20, forms ubm layer 11 (as Fig. 4) at the functional surfaces exposed from described multiple first peristome 61, then removes described first photoresist 6 (see Fig. 5); Step 30, is connected the function salient point 21 of described second chip 2 (as shown in Figure 6) with described ubm layer 11; Step 40, see Fig. 7, forms packed layer 5 between described first chip 1 and described second chip 2; Step 50, described first chip 1 forms articulamentum 3, and this articulamentum is layer structure (as shown in FIG. 11 and 12, but not shown layer structure); Step 60, continues see Figure 11 and 12, plants soldered ball 4 at described articulamentum 3 end face, and the end face of soldered ball is higher than the end face of the second chip.
How the articulamentum 3 that the following describes in above-mentioned steps 50 is formed, step 51 can be comprised, form packed layer 5 (as Fig. 7) between described first chip 1 and described second chip 2 after, be made up of described first chip 1, second chip 2 and described packed layer 5 integrally-built above, form vapor phase deposition layer (not shown), described vapor phase deposition layer is formed the second photoresist 7 (as shown in Figure 8), and on described second photoresist 7, form multiple second peristome 71 (as shown in Figure 9), expose described vapor phase deposition layer; Step 52, as shown in Figure 10, the described vapor phase deposition layer exposed forms articulamentum 3; Step 53, removes described second photoresist 7 and exposes described vapor phase deposition layer.
Above-mentioned packed layer 5 is optionally resin material.
In the optional execution mode of one, articulamentum is layer structure, is followed successively by nickel dam, nickel-copper alloy layer and layers of copper from top to bottom.
In the optional execution mode of one, in above-mentioned steps 51, vapor phase deposition layer can not be used, in step 53, certainly also just not need the operation of removing vapor phase deposition layer.
In the optional execution mode of one, with the upper surface of described first chip 1 for datum level, soldered ball end face is 100-120 micron to the distance of this datum level; Second chip 2 end face is less than 60 microns to the distance of datum level.Obviously this is a kind of execution mode of soldered ball end face higher than the second chip end face.
Above-mentioned articulamentum 3 is optionally copper post, and this copper post can adopt the mode of plating to be formed.Connecing soldered ball 4 is optionally tin ball.
In the optional execution mode of one, before the first chip 1 is formed the first photoresist 6, first on described first chip 1, form protective layer, surface forms described first photoresist 6 (not shown) on the protection layer afterwards; Described first peristome 61 exposes the protective layer on described functional surfaces; Ubm layer 11 is formed at the upper surface of the protective layer exposed from described peristome; Here should know, since ubm layer 11 has been formed in the upper surface of protective layer, so this protective surface should conducting ubm layer 11 and the first chip 1.In protective layer upper surface, the part being formed with described ubm layer 11 is Part I, and what do not form described ubm layer 11 is Part II, after removing described photoresist, then removes described Part II.
As shown in figure 12, above-mentioned articulamentum 3 (copper post) has multiple, and multiple described articulamentum 3, around described second chip 2, is formed on the first chip 1.
Before formation soldered ball 4, can first form one deck tin layers at the end face of articulamentum 3, plant ball to facilitate
Although last it is noted that described the present invention and advantage thereof in detail above, be to be understood that and can carry out various change when not exceeding the spirit and scope of the present invention limited by appended claim, substituting and converting.And scope of the present invention is not limited only to the specific embodiment of process, equipment, means, method and step described by specification.One of ordinary skilled in the art will readily appreciate that from disclosure of the present invention, can use perform the function substantially identical with corresponding embodiment described herein or obtain and its substantially identical result, existing and that will be developed in the future process, equipment, means, method or step according to the present invention.Therefore, appended claim is intended to comprise such process, equipment, means, method or step in their scope.
Claims (8)
1. a manufacture method for wafer-level packaging, is characterized in that,
First chip is formed the first photoresist, described first photoresist forms multiple first peristome, expose the functional surfaces of described first chip;
Form ubm layer at the functional surfaces exposed from described multiple first peristome, then remove described first photoresist;
The function salient point of described second chip is connected with described ubm layer;
Packed layer is formed between described first chip and described second chip;
Described first chip forms articulamentum, and described articulamentum is layer structure;
Plant soldered ball at described articulamentum end face, the end face of described soldered ball is higher than the end face of described second chip.
2. method according to claim 1, is characterized in that,
The method forming described articulamentum is:
Form packed layer between described first chip and described second chip after, be made up of described first chip, the second chip and described packed layer integrally-built above, form vapor phase deposition layer, described vapor phase deposition layer forms the second photoresist, and multiple second peristome is formed on described second photoresist, expose described vapor phase deposition layer;
The described vapor phase deposition layer exposed forms articulamentum;
Remove described second photoresist and expose described vapor phase deposition layer.
3. method according to claim 1, is characterized in that,
With the upper surface of described first chip for datum level, the end face of described soldered ball is 100-150 micron to the distance of described datum level;
Described second chip end face is less than 60 microns to the distance of described datum level.
4. method according to claim 1, is characterized in that,
Before first chip is formed the first photoresist, first on described first chip, form protective layer, surface forms described first photoresist on the protection layer afterwards;
Described first peristome exposes the protective layer on described functional surfaces;
Described ubm layer is formed at the upper surface of the protective layer exposed from described peristome;
In described protective layer upper surface, the part being formed with described ubm layer is Part I, and what do not form described ubm layer is Part II, after removing described photoresist, then removes described Part II.
5. the method according to any one of claim 1-4, is characterized in that,
The layer structure of described articulamentum, is followed successively by nickel dam, nickel-copper alloy layer and layers of copper from top to bottom.
6. the method according to any one of claim 1-4, is characterized in that,
The described soldered ball that connects is tin ball.
7. the method according to any one of claim 1-4, is characterized in that,
Described articulamentum has multiple, and multiple described articulamentum, around described second chip, is formed on described first chip.
8. the method according to any one of claim 1-4, is characterized in that,
Described packed layer is resin bed.
Priority Applications (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410839944.8A CN104616998A (en) | 2014-12-30 | 2014-12-30 | Method for manufacturing wafer level package |
| US15/326,401 US10008478B2 (en) | 2014-12-30 | 2015-11-24 | Fabricating method for wafer-level packaging |
| PCT/CN2015/095422 WO2016107336A1 (en) | 2014-12-30 | 2015-11-24 | Method for manufacturing wafer level package |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410839944.8A CN104616998A (en) | 2014-12-30 | 2014-12-30 | Method for manufacturing wafer level package |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN104616998A true CN104616998A (en) | 2015-05-13 |
Family
ID=53151392
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201410839944.8A Pending CN104616998A (en) | 2014-12-30 | 2014-12-30 | Method for manufacturing wafer level package |
Country Status (1)
| Country | Link |
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| CN (1) | CN104616998A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2016107336A1 (en) * | 2014-12-30 | 2016-07-07 | 南通富士通微电子股份有限公司 | Method for manufacturing wafer level package |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5734199A (en) * | 1995-12-18 | 1998-03-31 | Matsushita Electric Industrial Co., Ltd. | Semiconductor device having improved test electrodes |
| US6121682A (en) * | 1998-12-26 | 2000-09-19 | Hyundai Electronics Industries Co., Ltd. | Multi-chip package |
| US20030205826A1 (en) * | 2000-05-19 | 2003-11-06 | Megic Corporation | Multiple chips bonded to packaging structure with low noise and multiple selectable functions |
| CN101266967A (en) * | 2008-05-04 | 2008-09-17 | 日月光半导体制造股份有限公司 | Stacking chip encapsulation structure and its making method |
| CN102446780A (en) * | 2011-12-19 | 2012-05-09 | 南通富士通微电子股份有限公司 | Wafer-level packaging method |
| US20130320518A1 (en) * | 2012-05-31 | 2013-12-05 | Sts Semiconductor & Telecommunications Co., Ltd. | Wafer-level package and method of manufacturing the same |
-
2014
- 2014-12-30 CN CN201410839944.8A patent/CN104616998A/en active Pending
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5734199A (en) * | 1995-12-18 | 1998-03-31 | Matsushita Electric Industrial Co., Ltd. | Semiconductor device having improved test electrodes |
| US6121682A (en) * | 1998-12-26 | 2000-09-19 | Hyundai Electronics Industries Co., Ltd. | Multi-chip package |
| US20030205826A1 (en) * | 2000-05-19 | 2003-11-06 | Megic Corporation | Multiple chips bonded to packaging structure with low noise and multiple selectable functions |
| CN101266967A (en) * | 2008-05-04 | 2008-09-17 | 日月光半导体制造股份有限公司 | Stacking chip encapsulation structure and its making method |
| CN102446780A (en) * | 2011-12-19 | 2012-05-09 | 南通富士通微电子股份有限公司 | Wafer-level packaging method |
| US20130320518A1 (en) * | 2012-05-31 | 2013-12-05 | Sts Semiconductor & Telecommunications Co., Ltd. | Wafer-level package and method of manufacturing the same |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2016107336A1 (en) * | 2014-12-30 | 2016-07-07 | 南通富士通微电子股份有限公司 | Method for manufacturing wafer level package |
| US10008478B2 (en) | 2014-12-30 | 2018-06-26 | Tongfu Microelectronics Co., Ltd. | Fabricating method for wafer-level packaging |
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Address after: 226006 Jiangsu Province, Nantong City Chongchuan District Chongchuan Road No. 288 Applicant after: Tongfu Microelectronics Co., Ltd. Address before: 226006 Jiangsu Province, Nantong City Chongchuan District Chongchuan Road No. 288 Applicant before: Fujitsu Microelectronics Co., Ltd., Nantong |
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Application publication date: 20150513 |
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