CN104900608A - Wafer level packaging structure - Google Patents
Wafer level packaging structure Download PDFInfo
- Publication number
- CN104900608A CN104900608A CN201510260509.4A CN201510260509A CN104900608A CN 104900608 A CN104900608 A CN 104900608A CN 201510260509 A CN201510260509 A CN 201510260509A CN 104900608 A CN104900608 A CN 104900608A
- Authority
- CN
- China
- Prior art keywords
- protective layer
- wafer level
- level packaging
- packaging structure
- metal pad
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
Landscapes
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
The invention relates to a wafer level packaging structure comprising a chip structure with a conductive metal pad. The wafer level packaging structure also comprises a first protective layer which is formed on the chip structure, a second protective layer which is formed on the upper surface of the first protective layer and a re-wiring layer which is formed on the upper surface of the second protective layer. The first protective layer is provided with an opening from which the conductive metal pad exposed. The upper surface of the first protective layer is provided with convex parts and concave parts. The second protective layer is also provided with an opening from which the conductive metal pad exposed. The upper surface of the second protective layer is provided with convex parts and concave parts. The re-wiring layer also covers the exposed conductive metal pad. Surface area is increased and binding force between all the layers is increased by the convex parts and the concave parts formed on the first protective layer and the second protective layer so that stability of the overall structure is facilitated, a problem of layering of the overall structure is solved, and product reliability is enhanced simultaneously.
Description
Technical field
The present invention relates to field of semiconductor package, particularly relate to a kind of wafer level packaging structure.
Background technology
Along with wafer-level packaging chip size area reduces, front road disk surfaces designs simplification, surface more complicated, the area of wire structures increases, and needs multilayer organic substance to protect disk, strengthens planarization.Conventional multilayer organic constitution easily produces the exceptions such as layering, causes reliability not enough.
Summary of the invention
Provide hereinafter about brief overview of the present invention, to provide about the basic comprehension in some of the present invention.Should be appreciated that this general introduction is not summarize about exhaustive of the present invention.It is not that intention determines key of the present invention or pith, and nor is it intended to limit the scope of the present invention.Its object is only provide some concept in simplified form, in this, as the preorder in greater detail discussed after a while.
The invention provides a kind of wafer level packaging structure, comprise the chip structure with conducting metal pad, also comprise: on described chip structure, be formed with the first protective layer, and described first protective layer has the opening exposing described conducting metal pad, the upper surface of described first protective layer is wavy surface; The upper surface of described first protective layer is formed with the second protective layer, and described second protective layer also has the opening exposing described conducting metal pad, and the upper surface of described second protective layer is wavy surface; Wiring layer is again formed at the upper surface of described second protective layer; Wherein, the upper wavy surface of described first protective layer and described second protective layer, has multi-lobe, forms depressed part between two often adjacent lug bosses.
Compared to prior art, the lug boss of the first protective layer and the second protective layer upper surface and depressed part, increase surface area; add the adhesion between each layer; be conducive to integrally-built stable, solve the problem of overall structure layering, improve product reliability simultaneously.
Accompanying drawing explanation
In order to be illustrated more clearly in the embodiment of the present invention or technical scheme of the prior art, be briefly described to the accompanying drawing used required in embodiment or description of the prior art below, apparently, accompanying drawing in the following describes is only some embodiments of the present invention, for those of ordinary skill in the art, under the prerequisite not paying creative work, other accompanying drawing can also be obtained according to these accompanying drawings.
Fig. 1 is the schematic diagram of wafer level packaging structure of the present invention;
Fig. 2 is a kind of lug boss of protective layer and the schematic cross-section of depressed part in the present invention;
Fig. 3 is the lug boss of another kind of protective layer and the schematic cross-section of depressed part in the present invention.
Reference numeral: 101-chip structure; 102-conducting metal pad; 103-first protective layer; 201-second protective layer; 301-is wiring layer again; 401-the 3rd protective layer; 501-bump structure.
Embodiment
For making the object of the embodiment of the present invention, technical scheme and advantage clearly, below in conjunction with the accompanying drawing in the embodiment of the present invention, technical scheme in the embodiment of the present invention is clearly and completely described, obviously, described embodiment is the present invention's part embodiment, instead of whole embodiments.The element described in an accompanying drawing of the present invention or a kind of execution mode and feature can combine with the element shown in one or more other accompanying drawing or execution mode and feature.It should be noted that for purposes of clarity, accompanying drawing and eliminate expression and the description of unrelated to the invention, parts known to persons of ordinary skill in the art and process in illustrating.Based on the embodiment in the present invention, the every other embodiment that those of ordinary skill in the art obtain under the prerequisite not paying creative work, all belongs to the scope of protection of the invention.
In the following embodiment of the present invention, the sequence number of embodiment and/or sequencing are only convenient to describe, and do not represent the quality of embodiment.The description of each embodiment is all emphasized particularly on different fields, in certain embodiment, there is no the part described in detail, can see the associated description of other embodiments.
See Fig. 1, the invention provides a kind of wafer level packaging structure, comprise chip structure 101, chip structure has conducting metal pad 102, chip structure is also formed on the first protective layer 103, first protective layer 103 and has opening, this opening makes conducting metal pad expose, form second protective layer 201, second protective layer 201 at the upper surface of the first protective layer 103 there is opening equally to expose conducting metal pad; Form again wiring layer 301 at the upper surface of the second protective layer 201, and this again wiring layer 301 be also covered on conducting metal pad.The upper surface of the first protective layer 103 mentioned here, and the upper surface of the second protective layer 201 all has lug boss and depressed part.That is, the upper surface of the first protective layer 103 and the second protective layer 201 is all on-plane surface, can increase surface area like this, improve two-layer binding ability.
Optionally, lug boss and depressed part are intervally installed.Namely lug boss then a depressed part circulate successively, as shown in Figure 2, adjacent lug boss and depressed part can link together, also can be as shown in Figure 3, each other from, should be appreciated that, as long as can surface area be increased, improve binding ability, may be used to the present invention.
Optionally, lug boss and depressed part can form wavy surface.Need to understand, here wavy surface can be various structures, for cross section, lug boss can be triangle, also can be trapezoidal, arc, or other shape be also passable, as long as be formed with lug boss, and between adjacent lug boss, there is depressed part, just can play the function increasing two-layer combination row.
When having multiple lug boss and depressed part, the feature such as structure, shape of each lug boss can be different, and each depressed part also can be different.
In the optional execution mode of one, above-mentioned lug boss and the formation of depressed part are formed protective layer exposure by the light of different wave length.Such as after formation first protective layer 103; to the light exposure of the upper surface different wave length of the first protective layer 103; with the light of first wave length, it is exposed; form the top (hereinafter referred to as top) of lug boss; with the light of second wave length, it is exposed; form the bottom (hereinafter referred to as bottom) of depressed part, and adopt the pipeline of wavelength between the first and second wavelength to expose it, form the chamfered portion between top and bottom.Certainly, original height is just kept when not exposing.
Optionally, wiring layer 301 is again formed with the 3rd protective layer 401; 3rd protective layer 401 is formed with opening, wiring layer 301 again described in exposing; Again wiring layer 301 is forming bump structure 501 described in exposing.
In the optional execution mode of one, the second protective layer 201 is covered in the upper surface of the first protective layer completely; Wiring layer 301 is covered in the subregion of the second protective layer 201 upper surface again; The upper surface of wiring layer 301 again described in the 3rd protective layer 401 is formed at, and be formed at the upper surface of the second protective layer exposed from described wiring layer again 301.Like this, can ensure the fixing of the 3rd protective layer 401, it is by being combined with the wavy surface of the second protective layer, thus more not with layering.
Optionally, bump structure 501 and described conducting metal pad in the horizontal direction each other position stagger.
In the optional execution mode of one, the first protective layer, the second protective layer and the 3rd protective layer 401 are for being polyimide covercoat.In chip structure, the first protective layer, the second protective layer, the 3rd protective layer and described bump structure periphery, be enclosed with resin protective layer, and the top of bump structure is exposed from described resin protective layer.
Although last it is noted that described the present invention and advantage thereof in detail above, be to be understood that and can carry out various change when not exceeding the spirit and scope of the present invention limited by appended claim, substituting and converting.And scope of the present invention is not limited only to the specific embodiment of process, equipment, means, method and step described by specification.One of ordinary skilled in the art will readily appreciate that from disclosure of the present invention, can use perform the function substantially identical with corresponding embodiment described herein or obtain and its substantially identical result, existing and that will be developed in the future process, equipment, means, method or step according to the present invention.Therefore, appended claim is intended to comprise such process, equipment, means, method or step in their scope.
Claims (9)
1. a wafer level packaging structure, comprises the chip structure with conducting metal pad, it is characterized in that, also comprise:
Described chip structure is formed with the first protective layer, and described first protective layer has the opening exposing described conducting metal pad, the upper surface of described first protective layer has lug boss, and depressed part;
The upper surface of described first protective layer is formed with the second protective layer, and described second protective layer also has the opening exposing described conducting metal pad, and the upper surface of described second protective layer has lug boss, and depressed part;
Form wiring layer again at the upper surface of described second protective layer, and described wiring layer is more also covered in the described conducting metal pad exposed.
2. wafer level packaging structure according to claim 1, is characterized in that,
Described lug boss and described depressed part are intervally installed.
3. wafer level packaging structure according to claim 1, is characterized in that,
Described lug boss and described depressed part form wavy surface.
4. the wafer level packaging structure according to any one of claim 1-3, is characterized in that,
The lug boss of the described lug boss of described first protective layer and described depressed part, described second protective layer and depressed part, formed by the light exposure of different wave length.
5. the wafer level packaging structure according to any one of claim 1-3, is characterized in that,
Described wiring layer is again formed the 3rd protective layer;
Described 3rd protective layer is formed with opening, wiring layer again described in exposing;
Again wiring layer is forming bump structure described in exposing.
6. wafer level packaging structure according to claim 5, is characterized in that,
Described second protective layer is covered in the upper surface of described first protective layer completely;
Described wiring layer is again covered in the subregion of the second protective layer upper surface;
The upper surface of wiring layer again described in described 3rd protective layer is formed at, and be formed at the upper surface of the second protective layer exposed from described wiring layer again.
7. wafer level packaging structure according to claim 5, is characterized in that,
Described bump structure and described conducting metal pad in the horizontal direction each other position stagger.
8. the wafer level packaging structure according to claim 6 or 7, is characterized in that,
Described first protective layer, the second protective layer and the 3rd protective layer are polyimide covercoat.
9. the wafer level packaging structure according to claim 6 or 7, is characterized in that,
Described chip structure, described first protective layer, described second protective layer, described 3rd protective layer and described bump structure periphery, be enclosed with resin protective layer, and the top of described bump structure is exposed from described resin protective layer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510260509.4A CN104900608B (en) | 2015-05-20 | 2015-05-20 | Wafer level packaging structure |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510260509.4A CN104900608B (en) | 2015-05-20 | 2015-05-20 | Wafer level packaging structure |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN104900608A true CN104900608A (en) | 2015-09-09 |
| CN104900608B CN104900608B (en) | 2017-11-07 |
Family
ID=54033183
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201510260509.4A Active CN104900608B (en) | 2015-05-20 | 2015-05-20 | Wafer level packaging structure |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN104900608B (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2017129697A1 (en) * | 2016-01-29 | 2017-08-03 | Osram Opto Semiconductors Gmbh | Optoelectronic component having side contacts |
| CN113140468A (en) * | 2021-04-22 | 2021-07-20 | 上海华友金裕微电子有限公司 | Integrated circuit wafer front processing technology |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20080174025A1 (en) * | 2007-01-24 | 2008-07-24 | Samsung Electronics Co., Ltd. | Semiconductor chip structure, method of manufacturing the semiconductor chip structure, semiconductor chip package, and method of manufacturing the semiconductor chip package |
| CN101924083A (en) * | 2009-06-09 | 2010-12-22 | 日月光半导体制造股份有限公司 | Packaged semiconductor and production method thereof |
| CN102832181A (en) * | 2011-06-13 | 2012-12-19 | 矽品精密工业股份有限公司 | Chip Scale Package |
-
2015
- 2015-05-20 CN CN201510260509.4A patent/CN104900608B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20080174025A1 (en) * | 2007-01-24 | 2008-07-24 | Samsung Electronics Co., Ltd. | Semiconductor chip structure, method of manufacturing the semiconductor chip structure, semiconductor chip package, and method of manufacturing the semiconductor chip package |
| CN101924083A (en) * | 2009-06-09 | 2010-12-22 | 日月光半导体制造股份有限公司 | Packaged semiconductor and production method thereof |
| CN102832181A (en) * | 2011-06-13 | 2012-12-19 | 矽品精密工业股份有限公司 | Chip Scale Package |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2017129697A1 (en) * | 2016-01-29 | 2017-08-03 | Osram Opto Semiconductors Gmbh | Optoelectronic component having side contacts |
| US10811579B2 (en) | 2016-01-29 | 2020-10-20 | Osram Oled Gmbh | Optoelectronic component having side contacts |
| CN113140468A (en) * | 2021-04-22 | 2021-07-20 | 上海华友金裕微电子有限公司 | Integrated circuit wafer front processing technology |
Also Published As
| Publication number | Publication date |
|---|---|
| CN104900608B (en) | 2017-11-07 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN110444578B (en) | Flexible display panel and manufacturing method thereof | |
| US8987884B2 (en) | Package assembly and methods for forming the same | |
| CN110444549B (en) | Flexible display panel and manufacturing method thereof | |
| CN104332452B (en) | Chip packaging module | |
| CN102217061B (en) | Improved wafer level chip scale packaging | |
| KR20140002457A (en) | Package structures and methods for forming the same | |
| US9214438B2 (en) | Die-die stacking structure and method for making the same | |
| CN104900608A (en) | Wafer level packaging structure | |
| US9583368B2 (en) | Flip chip package and manufacturing method thereof | |
| CN103165481B (en) | Bump manufacture technology and structure thereof | |
| CN105870088A (en) | Semiconductor packaging structure and manufacturing method for the same | |
| CN106328626A (en) | Semiconductor device | |
| US20220384376A1 (en) | Package structure of semiconductor device with improved bonding between the substrates | |
| CN103400845A (en) | Packaging method for image sensor | |
| KR102033788B1 (en) | Embedded package and method of fabricating the same | |
| TWI517318B (en) | Substrate having pillar group and semiconductor package having pillar group | |
| JP6595788B2 (en) | Solid-state imaging device manufacturing method, solid-state imaging device, and camera | |
| US9408313B2 (en) | Packaging substrate and method of fabricating the same | |
| US20150214169A1 (en) | Method of fabricating connection structure for a substrate | |
| CN107146780B (en) | Semiconductor chip and semiconductor device | |
| TWM410659U (en) | Bump structure | |
| CN104992909A (en) | Manufacturing method of wafer level packaging structure | |
| CN108110012B (en) | Flexible electronic device | |
| CN105225975A (en) | Package structure and method for fabricating the same | |
| CN105810649A (en) | Semiconductor device bonding structure and bonding method |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| CB02 | Change of applicant information |
Address after: 226006 Jiangsu Province, Nantong City Chongchuan District Chongchuan Road No. 288 Applicant after: Tongfu Microelectronics Co., Ltd. Address before: 226006 Jiangsu Province, Nantong City Chongchuan District Chongchuan Road No. 288 Applicant before: Fujitsu Microelectronics Co., Ltd., Nantong |
|
| COR | Change of bibliographic data | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |