CN101924083A - Packaged semiconductor and production method thereof - Google Patents
Packaged semiconductor and production method thereof Download PDFInfo
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- CN101924083A CN101924083A CN2009101461540A CN200910146154A CN101924083A CN 101924083 A CN101924083 A CN 101924083A CN 2009101461540 A CN2009101461540 A CN 2009101461540A CN 200910146154 A CN200910146154 A CN 200910146154A CN 101924083 A CN101924083 A CN 101924083A
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 41
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 25
- 238000005520 cutting process Methods 0.000 claims abstract description 8
- 239000010410 layer Substances 0.000 claims description 180
- 238000007789 sealing Methods 0.000 claims description 44
- 238000000034 method Methods 0.000 claims description 30
- 230000015572 biosynthetic process Effects 0.000 claims description 20
- 239000000853 adhesive Substances 0.000 claims description 14
- 230000001070 adhesive effect Effects 0.000 claims description 14
- 239000004744 fabric Substances 0.000 claims description 14
- 230000000694 effects Effects 0.000 claims description 13
- 238000004381 surface treatment Methods 0.000 claims description 10
- 239000011241 protective layer Substances 0.000 claims description 8
- 239000008393 encapsulating agent Substances 0.000 claims description 2
- 239000000565 sealant Substances 0.000 abstract description 9
- 229910000679 solder Inorganic materials 0.000 abstract description 2
- 210000002381 plasma Anatomy 0.000 abstract 2
- 238000005253 cladding Methods 0.000 abstract 1
- 239000012535 impurity Substances 0.000 description 16
- 238000010586 diagram Methods 0.000 description 10
- 239000000463 material Substances 0.000 description 8
- 230000002378 acidificating effect Effects 0.000 description 4
- 239000004020 conductor Substances 0.000 description 3
- 230000005611 electricity Effects 0.000 description 3
- 239000011248 coating agent Substances 0.000 description 2
- 238000000576 coating method Methods 0.000 description 2
- 230000006866 deterioration Effects 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 238000004806 packaging method and process Methods 0.000 description 2
- 239000002245 particle Substances 0.000 description 2
- 238000007788 roughening Methods 0.000 description 2
- 239000004295 calcium sulphite Substances 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 239000002362 mulch Substances 0.000 description 1
- 238000006396 nitration reaction Methods 0.000 description 1
- 150000004767 nitrides Chemical class 0.000 description 1
- 230000001681 protective effect Effects 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/93—Batch processes
- H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L24/96—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/568—Temporary substrate used as encapsulation process aid
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/12105—Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L2224/19—Manufacturing methods of high density interconnect preforms
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- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
Abstract
The invention discloses a packaged semiconductor and a production method thereof. The production method comprises the steps of: firstly, providing a carrier plate; secondly, setting chips on the carrier plate; thirdly, cladding the chips with sealant so as to ensure that the sealant and the chips form a sealant body full of chips; fourthly, removing the carrier plate to expose a chip connection pad of the sealant body full of chips; fifthly, acting the joint pad and the sealant by using plasmas to rough the surface of the joint pad and the sealant; sixthly, forming a first dielectric layer on the surfaces of the joint pad and the sealant; eighthly, acting the surface of the first dielectric layer with the plasmas to rough the surface; ninthly, forming a patterned conductive layer on the surface of the first dielectric layer; tenthly, forming a second dielectric layer on the patterned conductive layer and the first dielectric layer; eleventhly, forming solder balls on the second dielectric layer; and finally, cutting the sealant full of the chip to form a plurality of packaged semiconductors.
Description
Technical field
The invention relates to a kind of semiconductor package part and manufacture method thereof, and particularly relevant for the semiconductor package part and the manufacture method thereof of a kind of employing plasma (plasma) technology.
Background technology
Please refer to Fig. 1, it illustrates the partial sectional view of known semiconductor packaging part.After first dielectric layer 104 of semiconductor package part 100 forms, form patterned conductive layer 102, then form second dielectric layer 108 again.
Yet, in the process that forms patterned conductive layer 102, meeting kish atom on the surface 106 of first dielectric layer 104, after the result forms second dielectric layer 108, those kish atoms (not illustrating) form conductive layer 110 between first dielectric layer 104 and second dielectric layer 108, as shown in Figure 2, it illustrates the enlarged diagram of local A among Fig. 1.Therefore, cause leakage problem, influence the function of semiconductor package part 100.
In addition, before forming first dielectric layer 104, the surface 124 of sealing 122 is for smooth surface and be full of many impurity, therefore influences first dielectric layer 104 of follow-up formation and the associativity on surface 124, acidic gas in air is easily invaded and causes structural deterioration.Similarly, before forming patterned conductive layer 102, the surface 126 (being illustrated in Fig. 1) of first dielectric layer 104 is for smooth surface and be full of many impurity, therefore influence the patterned conductive layer 102 of follow-up formation and the associativity on surface 126, acidic gas in air is easily invaded and cause structural deterioration.
In addition, please refer to Fig. 3, it illustrates the enlarged diagram of local B among Fig. 1.Before forming first dielectric layer 104, the surface 116 of the connection pad 114 of chip 112 can residual many impurity.In follow-up first dielectric layer, 104 forming processes, developer can infiltrate in the impurity, causes in follow-up baking process, and unfilled corner 118 contracts in first dielectric layer 104 forms.So, will cause the patterned conductive layer 102 of follow-up formation to produce depression breach 120, this depression breach 120 makes patterned conductive layer 102 become the not good conductor of electricity of high impedance, influences the function of semiconductor package part 100.
Summary of the invention
Manufacture method according to semiconductor package part of the present invention, before forming first dielectric layer, Surface Treatment with Plasma is carried out on surface to sealing, form coarse structure with the lip-deep impurity of removing sealing and the surface that makes sealing, increase the associativity on the surface of first dielectric layer of follow-up formation and sealing.In addition, after first dielectric layer forms, Surface Treatment with Plasma is carried out on surface to first dielectric layer, form coarse structure with the lip-deep impurity of removing first dielectric layer and the surface that makes first dielectric layer, increase the associativity on the surface of the patterned conductive layer of follow-up formation and first dielectric layer.
A kind of manufacture method of semiconductor package part is proposed according to an aspect of the present invention.Manufacture method may further comprise the steps.One support plate is provided; Several chips are set on support plate, each chip has an active surface and comprises several connection pads, and connection pad is positioned at active surface, and wherein active surface is towards support plate; With a sealing, the sidewall of coating chip makes sealing and chip form the adhesive body (Chip-redistribution Encapsulant) of a heavy cloth chip.Sealing has a first surface, and first surface flushes in fact with active surface; Remove support plate, make the adhesive body of heavy cloth chip expose connection pad; With the first surface of plasma effect, make first surface become roughened surface in connection pad and sealing; Form one first dielectric layer in connection pad and first surface, first dielectric layer has a corresponding second surface and one the 3rd surface and several first perforates, second surface is positioned at the active surface of chip and the first surface of sealing, each first perforate exposes corresponding connection pad, and wherein the sidewall of each first perforate forms a turning point with corresponding connection pad; In the 3rd surface of first dielectric layer, the sidewall of first perforate and the upper surface of connection pad, make the sidewall of the 3rd surface, first perforate and the upper surface of connection pad become roughened surface with plasma effect; Form three surface, the sidewall of first perforate and the upper surface of connection pad of a patterned conductive layer in first dielectric layer partly; Form three surface of one second dielectric layer in the patterned conductive layer and first dielectric layer; Form several soldered balls on second dielectric layer; And the adhesive body of cutting heavy cloth chip is to form several semiconductor package parts.
According to a further aspect in the invention, a kind of semiconductor package part is proposed.Semiconductor package part comprises a sealing, a chip, one first dielectric layer, a patterned conductive layer and one second dielectric layer.Chip has an active surface and comprises several connection pads.The sidewall of sealant covers chip also has a first surface, and first surface flushes in fact with active surface.First dielectric layer has a corresponding second surface and one the 3rd surface and several first perforates.Second surface is positioned on active surface and the first surface, and each first perforate exposes corresponding connection pad, and wherein the sidewall of each first perforate forms a turning point with corresponding connection pad.Patterned conductive layer is formed at the sidewall of the 3rd surface, first perforate and the upper surface of connection pad, and the patterned conductive layer that wherein is positioned at the turning point is continuously and uninterruptedly.Second dielectric layer is formed at patterned conductive layer and the 3rd surface.Wherein, the outer surface of the upper surface of the sidewall of first surface, the 3rd surface, first perforate and connection pad is a roughened surface.
For foregoing of the present invention can be become apparent, preferred embodiment cited below particularly, and conjunction with figs. are described in detail below:
The accompanying drawing simple declaration:
Fig. 1 (known skill) illustrates the partial sectional view of known semiconductor packaging part.
Fig. 2 (known skill) illustrates the enlarged diagram of local A among Fig. 1.
Fig. 3 (known skill) illustrates the enlarged diagram of local B among Fig. 1.
Fig. 4 illustrates the manufacture method flow chart according to the semiconductor package part of preferred embodiment of the present invention.
Fig. 5 A to 5L illustrates the manufacture process schematic diagram according to the semiconductor package part of first embodiment of the invention.
The primary clustering symbol description:
100,200: semiconductor package part
102,214: patterned conductive layer
104,212: the first dielectric layers
106,116,124,126,248,250: the surface
108,218: the second dielectric layers
110: conductive layer
112,204: chip
114: connection pad
118: in the unfilled corner that contracts
120: the depression breach
122,206: sealing
202: support plate
204a: active surface
208: the adhesive body of heavy cloth chip
210: chip surface
222: soldered ball
224: paste film
226: connection pad
228: protective layer
Perforate in 230: the first
232,242: partly
236: upper surface
238,272: the three surfaces
Perforate in 240: the second
244: the some of sealing
252: interface
254,274: sidewall
256: first surface
264,266,268: the lateral margin face
270: second surface
276: the turning point
280: the protective layer perforate
A, B, C, D, E, F: part
S402-S430: step
Embodiment
In semiconductor package part of the present invention and manufacture method thereof, before forming first dielectric layer, Surface Treatment with Plasma is carried out on surface to sealing, with the impurity on the surface of removing sealing and make the surface of sealing form coarse structure, with the associativity on the surface of first dielectric layer that increases follow-up formation and sealing.In addition, after first dielectric layer forms, can carry out Surface Treatment with Plasma to the surface of first dielectric layer, form coarse structure with the lip-deep impurity of removing first dielectric layer and the surface that makes first dielectric layer, increase the associativity on the surface of the patterned conductive layer of follow-up formation and first dielectric layer.
Preferred embodiment is below proposed as explanation of the present invention, however the content that embodiment proposed, usefulness only for illustrating, and the accompanying drawing of drawing illustrates for cooperating, and is not the usefulness as limit protection range of the present invention.Moreover the icon of embodiment also omits unnecessary assembly, in order to clear demonstration technical characterstic of the present invention.
Please be simultaneously with reference to Fig. 4 and Fig. 5 A to 5L, Fig. 4 illustrates the manufacture method flow chart according to the semiconductor package part of preferred embodiment of the present invention, and Fig. 5 A to 5L illustrates the manufacture process schematic diagram according to the semiconductor package part of preferred embodiment of the present invention.
At first, in step S402, please provide a support plate 202 simultaneously with reference to shown in Fig. 5 A, it comprises pastes film 224.
Then, in step S404, please be simultaneously with reference to shown in Fig. 5 B, several chips 204 are set on support plate 202, paste film 224, the active surface 204a of chip 204 is towards support plate 202.
Then, in step S406, please with a sealing 206 coating chips 204, make sealing 206 and chip 204 form the adhesive body 208 of a heavy cloth chip simultaneously with reference to shown in Fig. 5 C.
Then, in step S408, please remove support plate 202 and paste film 224, make the adhesive body 208 of heavy cloth chip expose the first surface 256 of sealing 206 simultaneously with reference to shown in Fig. 5 D.Wherein, the chip surface 210 of Fig. 5 D and first surface 256 are down.So, the action of the adhesive body 208 by being inverted (invert) heavy cloth chip can make chip surface 210 and first surface 256 up, shown in Fig. 5 E.
Fig. 5 E illustrates the enlarged diagram of Local C among Fig. 5 D.Chip 204 can comprise several connection pads 226, and the adhesive body 208 of heavy cloth chip can comprise a protective layer 228.Protective layer 228 for example is nitration case (nitride layer) or oxide layer, and it has the protective layer perforate 280 that exposes connection pad 226.In order not make icon too complicated, the connection pad of Fig. 5 E 226 is that example explains with single.
Then, in step S410, with the first surface 256 of plasma effect in connection pad 226 and sealing 206.By Surface Treatment with Plasma, can remove the impurity on the first surface 256 of sealing 206, for example be oxide.So, can promote the structure of chip surface 210, connection pad 226 and first surface 256 and follow-up formation, i.e. the associativity of first dielectric layer 212 (being illustrated in Fig. 5 F).
By Surface Treatment with Plasma, first surface 256 is hit out the pothole of many nano-grade sizes by the plasma particle.Be not subjected to the surface 124 that Surface Treatment with Plasma is crossed in Fig. 2 (known skill), the first surface 256 of present embodiment is a roughened surface, shown in the enlarged diagram of local E among Fig. 5 E.So, more can promote the structure of first surface 256 and follow-up formation, i.e. the associativity of first dielectric layer 212 (being illustrated in Fig. 5 F).
Say that further the material of sealing 206 is different with the material of first dielectric layer 212,, can promote the associativity of itself and first dielectric layer 212 by the surface roughening of sealing 206.
Then, in step S412, shown in Fig. 5 F, form one first dielectric layer 212 on chip surface 210, first surface 256 and connection pad 226.Wherein, the material of first dielectric layer 212 for example is a macromolecular material.In addition, first dielectric layer 212 has a corresponding second surface 270 and one the 3rd surface 272, and second surface 270 is positioned at chip 204 and first surface 256, that is, the some and the first surface 256 of second surface 270 protective mulches 228, connection pad 226.
In the semiconductor package part of present embodiment, first dielectric layer 212 partly is overlapping with the some 244 of sealing.Wherein, this part 244 of sealing 206 is formed at the sidewall 254 of chip 204 and the surface that first surface 256 belongs to this part 244 of sealing 206, and it flushes in fact with active surface 204a.
Then, in step S414, please form first perforate 230 in first dielectric layer 212, so that first perforate 230 exposes connection pad 226 simultaneously with reference to shown in Fig. 5 G.Wherein, the sidewall 274 of first perforate 230 forms a turning point 276 with connection pad 226.
Then, in step S416, with plasma effect in the sidewall 274 (being illustrated in Fig. 5 G) of the 3rd surface 272 of first dielectric layer 212 (being illustrated in Fig. 5 G), first perforate 230 and the upper surface 236 (being illustrated in Fig. 5 G) of connection pad 226, with the impurity on the 3rd surface 272, sidewall 274 and the upper surface 236 of removing first dielectric layer 212, for example be oxide.So, can increase the patterned conductive layer 214 (being illustrated in Fig. 5 H) of follow-up formation and the associativity of turning point 276, and the associativity of the patterned conductive layer 214 and first dielectric layer 212.
By Surface Treatment with Plasma, the 3rd surface 272 and sidewall 274 are hit out the pothole of many nano-grade sizes by the plasma particle, and become roughened surface, shown in the enlarged diagram of local F among Fig. 5 G.Be not subjected to the surface 126 that Surface Treatment with Plasma is crossed in Fig. 2 (known skill), the 3rd surface 272 and the turning point 276 of present embodiment are roughened surface.So, more can promote the structure of the 3rd surface 272 and turning point 276 and follow-up formation, i.e. the associativity of patterned conductive layer 214.Say that further the material of first dielectric layer 212 is different with the material of patterned conductive layer 214,, can promote the associativity of itself and patterned conductive layer 214 by the surface roughening of first dielectric layer 212.
Then, in step S418, please be simultaneously with reference to shown in Fig. 5 H, can adopt sputtering way, form a patterned conductive layer 214, for example be that (Redistribution layer is RDL) in the 3rd surface 272 of first dielectric layer 212, the sidewall 274 of first perforate 230 and the upper surface 236 of connection pad 226 for re-wiring layer.The part 232 that patterned conductive layer 214 connects and covering connection pad 226 exposes from first perforate 230.Wherein, Bu Fen patterned conductive layer 214 extends to this part 244 of sealing overlapping.
In addition, before forming first dielectric layer 212, the plasma process in step S410 has been removed the impurity on the connection pad 226.So, shown in the enlarged diagram of the local D of Fig. 5 H, first dielectric layer 212 can not form in the forming process shown in Fig. 3 (known skill) in the unfilled corner 118 that contracts.
Because first dielectric layer 212 can not form the unfilled corner 118 that contracts in known in forming process, so can avoid patterned conductive layer 214 generations known depression breach 120 as shown in Figure 3.Say that further the sidewall 274 that is positioned at first perforate 230 in the patterned conductive layer 214 is continuous and uninterrupted with the part of the turning point 276 of connection pad 226.So, patterned conductive layer 214 can not produce known depression breach 120 and become the not good conductor of electricity of high impedance.
Then, in step S420, with plasma effect another the 3rd surface 238 (being illustrated in Fig. 5 H) and patterned conductive layer 214 partly in first dielectric layer 212, with the impurity on the surface 248 (being illustrated in Fig. 5 H) of removing another the 3rd surperficial 238 and patterned conductive layer 214 partly in first dielectric layer 212, so can increase another the 3rd surface 238 partly and the associativity of second dielectric layer 218 (being illustrated in following Fig. 5 I) of follow-up formation, and the associativity of second dielectric layer 218 of patterned conductive layer 214 and follow-up formation.Wherein, the 3rd surface 238 is the some on the 3rd surface 272, and the 3rd surface 238 is the surface that contacts with patterned conductive layer 214 in the 3rd surface 272.
Then, in step S422, please form on the 3rd surface 238 (being illustrated in Fig. 5 H) of one second dielectric layer 218 another part in the patterned conductive layer 214 and first dielectric layer 212 simultaneously with reference to shown in Fig. 5 I.Wherein, the material of second dielectric layer 218 for example is a macromolecular material.
The metallic atom on residual the 3rd surface 238 that is not connected with patterned conductive layer 214 in the implementation of step S418 can be effectively removed in the action of plasma process among the previous step S420.So, second dielectric layer 218 can intactly be fitted on clean the 3rd surface 238 (being illustrated in Fig. 5 H), and the known conductive layer 110 that can not form as shown in Figure 2 in the interface 252 of the 3rd surface 238 and second dielectric layer 218.Therefore, the manufacture method of present embodiment can effectively avoid leakage current to take place.
Then, in step S424, please form second perforate 240 in second dielectric layer 218, so that second perforate 240 exposes the some 242 of patterned conductive layer 214 simultaneously with reference to shown in Fig. 5 J.
In addition, after this step S424, can form solder ball connecting pad (not illustrating) on the some 242 of patterned conductive layer 214, with the conductive stability and the associativity of 214 of the soldered ball 222 (being illustrated in Fig. 5 K) that promotes follow-up formation and patterned conductive layers.
Then, in step S426, with plasma effect in second dielectric layer 218, with the impurity on the some 242 (being illustrated in Fig. 5 J) of the surface 250 (being illustrated in Fig. 5 J) of removing second dielectric layer 218 and patterned conductive layer 214, to promote the associativity of patterned conductive layer 214 and the soldered ball 222 of follow-up formation.
Then, in step S428, please according to the position of second perforate 240 (being illustrated in Fig. 5 J), form soldered ball 222 on second dielectric layer 218, soldered ball 222 and patterned conductive layer 214 are electrically connected simultaneously with reference to shown in Fig. 5 K.
Then, in step S430, according to the position of chip 204, cutting is formed with the adhesive body 208 of the heavy cloth chip of above-mentioned structure, and to cut into several semiconductor package parts 200, semiconductor package part 200 is shown in Fig. 5 L.This above-mentioned structure promptly in step S412 to step S428 in formed structure.Wherein, because cutting path is through the overlapping of first dielectric layer 212, second dielectric layer 218 and sealing 206, the semiconductor package part 200 after so cutting is finished, the lateral margin face 266 of its first dielectric layer 212, the lateral margin face 264 of second dielectric layer 218 and the lateral margin face 268 of sealing 206 trim in fact.
In the semiconductor package part 200 of present embodiment, patterned conductive layer 214 partly and soldered ball 222 partly may extend to this part 244 of sealing 206 overlapping.So, can increase the output of semiconductor package part 200/go into contact number.
Disclosed semiconductor package part of the above embodiment of the present invention and manufacture method thereof have multiple advantages, and enumerating partly, advantage is described as follows:
(1). before forming first dielectric layer, reach in connection pad with plasma effect, to remove the impurity on the connection pad, make first dielectric layer in forming process, can not produce the unfilled corner 118 that contracts in known, therefore also avoided the patterned conductive layer of follow-up formation to produce known depression breach 120.So, patterned conductive layer can not become the not good conductor of electricity of high impedance because of the generation of depression breach.
(2). before forming first dielectric layer, in sealing, except can removing the impurity in the sealing, also can make sealing form roughened surface,, make acidic gas in air be difficult for invading in order to closely combining with first dielectric layer of follow-up formation with plasma effect.
(3). after forming first dielectric layer and before forming patterned conductive layer, with plasma effect in first dielectric layer, the impurity on can clearing up first dielectric layer, also can make first dielectric layer form roughened surface, in order to closely combining, make acidic gas in air be difficult for invading with the patterned conductive layer of follow-up formation.
(4). after forming first dielectric layer and patterned conductive layer,, second dielectric layer of follow-up formation can fully be conformed on first dielectric layer with plasma effect metal remained atom on first dielectric layer.Therefore, can not form known conductive layer 110 as shown in Figure 2 between first dielectric layer and second dielectric layer, therefore can avoid the generation of leakage problem.
In sum, though the present invention discloses as above with preferred embodiment, so it is not in order to limit the present invention.The persond having ordinary knowledge in the technical field of the present invention, without departing from the spirit and scope of the present invention, when being used for a variety of modifications and variations.Therefore, protection scope of the present invention is as the criterion when looking the accompanying Claim book person of defining.
Claims (16)
1. semiconductor package part comprises:
One chip has an active surface and comprises several connection pads;
One sealing coats the sidewall of this chip and has a first surface, and this first surface flushes in fact with this active surface;
One first dielectric layer, have a corresponding second surface and one the 3rd surface and several first perforates, this second surface is positioned on this first surface of this active surface of this chip and this sealing, each those first perforate exposes this corresponding connection pad, and wherein a sidewall of each those first perforate forms a turning point with corresponding this connection pad;
One patterned conductive layer is formed at the 3rd surface, this sidewall of each those first perforate and a upper surface of each those connection pad, and this patterned conductive layer that wherein is positioned at this turning point is continuously and uninterruptedly; And
One second dielectric layer is formed on this patterned conductive layer and the 3rd surface;
Wherein, this upper surface of this sidewall of this first surface, this three surface, each those first perforate and each those connection pad is a roughened surface.
2. semiconductor package part as claimed in claim 1, wherein this roughened surface is formed surface after the Surface Treatment with Plasma.
3. semiconductor package part as claimed in claim 2, wherein this roughened surface has several potholes.
4. semiconductor package part as claimed in claim 3, wherein those potholes are of a size of nano-grade size.
5. semiconductor package part as claimed in claim 1, wherein this chip more comprises:
One protective layer is formed on this active surface of this chip, has the protective layer perforate that several expose those connection pads.
6. semiconductor package part as claimed in claim 5, wherein this second surface of this first dielectric layer covers the some of this protective layer and each those connection pad.
7. semiconductor package part as claimed in claim 1, wherein this second dielectric layer more comprises:
Several second perforates, it exposes the some of this patterned conductive layer; And
Several soldered balls are formed in those second perforates, so that those soldered balls and this patterned conductive layer electrically connect.
8. semiconductor package part as claimed in claim 1, wherein the lateral margin face of the lateral margin face of the lateral margin face of this first dielectric layer, this second dielectric layer and this sealing flushes in fact.
9. semiconductor package part as claimed in claim 1, wherein this patterned conductive layer be re-wiring layer (Redistribution layer, RDL).
10. the manufacture method of a semiconductor package part comprises:
One support plate is provided;
Several chips are set on this support plate, each those chip has an active surface and comprises several connection pads, and those connection pads are positioned at this active surface, and wherein those active surfaces are towards this support plate;
With a sealing, coat the sidewall of those chips, make this sealing and those chips form the adhesive body (Chip-redistribution Encapsulant) of a heavy cloth chip, this sealing has a first surface, and this first surface flushes in fact with those active surfaces;
Remove this support plate, make the adhesive body of this heavy cloth chip expose those connection pads;
Act on this first surface of those connection pads and this sealing with plasma (plasma), make this first surface become roughened surface;
Form one first dielectric layer in those connection pads and this first surface, this first dielectric layer has a corresponding second surface and one the 3rd surface and several first perforates, this second surface is positioned at this active surface of each those chip and this first surface of this sealing, each those first perforate exposes this corresponding connection pad, and wherein a sidewall of each those first perforate forms a turning point with corresponding this connection pad;
With the upper surface of plasma effect, make this upper surface of this three surface, this sidewall and each those connection pad become roughened surface in the 3rd surface, this sidewall and each those connection pad of this first dielectric layer;
Form a patterned conductive layer in the 3rd surface, this sidewall of each those first perforate and this upper surface of each those connection pad, this patterned conductive layer that wherein is positioned at this turning point is continuously and uninterrupted;
Form three surface of one second dielectric layer in this patterned conductive layer and this first dielectric layer;
Form several soldered balls on this second dielectric layer; And
Cut the adhesive body of this heavy cloth chip, to form several semiconductor package parts.
11. manufacture method as claimed in claim 10 wherein after this step that forms this patterned conductive layer and before this step of this second dielectric layer of formation, more comprises:
With plasma effect in this first dielectric layer and this patterned conductive layer.
12. manufacture method as claimed in claim 10, wherein in this step that forms this patterned conductive layer, this patterned conductive layer connection also covers the part that those connection pads expose from those first perforates.
13. manufacture method as claimed in claim 10, wherein after forming this this step of second dielectric layer, this manufacture method more comprises:
With plasma effect in this second dielectric layer.
14. manufacture method as claimed in claim 10, wherein after this step that forms this second dielectric layer, this manufacture method more comprises:
Form several second perforates in this second dielectric layer, so that those second perforates expose the partly some of this patterned conductive layer respectively.
15. manufacture method as claimed in claim 14 wherein forms those soldered balls this step on this second dielectric layer and comprises:
According to the position of those second perforates, form those soldered balls in those second openings, so that those soldered balls and this patterned conductive layer electrically connect.
16. manufacture method as claimed in claim 10 wherein comprises in this step of the adhesive body that cuts this heavy cloth chip:
Cut the adhesive body of this heavy cloth chip along a cutting path, this cutting path is through the overlapping of this first dielectric layer, this second dielectric layer and this sealing, so that lateral margin face, the lateral margin face of this second dielectric layer and the lateral margin face of this sealing of this first dielectric layer flush in fact in this semiconductor package part after the cutting.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2009101461540A CN101924083B (en) | 2009-06-09 | 2009-06-09 | Packaged semiconductor and production method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
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