CN103811536A - Wafer thinning structure for wafer level packaging technology - Google Patents
Wafer thinning structure for wafer level packaging technology Download PDFInfo
- Publication number
- CN103811536A CN103811536A CN201410034804.3A CN201410034804A CN103811536A CN 103811536 A CN103811536 A CN 103811536A CN 201410034804 A CN201410034804 A CN 201410034804A CN 103811536 A CN103811536 A CN 103811536A
- Authority
- CN
- China
- Prior art keywords
- wafer
- level packaging
- salient point
- attenuate
- chip
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/17—Structure, shape, material or disposition of the bump connectors after the connecting process of a plurality of bump connectors
- H01L2224/171—Disposition
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Packaging Frangible Articles (AREA)
Abstract
The invention discloses a wafer thinning structure for a wafer level packaging technology. The wafer thinning structure comprises: a wafer, a plurality of chips and conductive bumps, wherein the chips are in array distribution on one surface of the wafer, the conductive bumps are formed on the surfaces of the chips far away from the wafer, and a ring structure which is thick in periphery and thin in middle part is formed on one surface of the water on which the chips are not formed. according to the wafer thinning structure for the wafer level packaging technology, the purpose that the thicknesses of single chips packaged by the wafer of a semiconductor device with same function get thinner and thinner can be achieved, and more importantly, the purpose that the back of the wafer is only slightly warped after thinning can be achieved.
Description
Technical field
The present invention relates to a kind of semiconductor package, relate in particular to a kind of wafer level packaging technique wafer attenuate structure.
Background technology
In recent years, semiconductor device is under the common promotion of the lifting of cost He Qian road wafer manufacturing process, realize the more and more less target of monomer chip size of the semiconductor device of said function, can cause like this semiconductor device heat radiation to require more and more higher, also need semiconductor device more and more thinner, wafer level packaging technique wafer reduction process originally cannot meet the requirement of thin type and high heat radiation simultaneously.
By existing wafer level packaging wafer reduction process, after wafer back part attenuate, there will be the situation of overall warpage, be illustrated in figure 1 existing wafer level packaging technique and carry out the sectional view after wafer attenuate, Fig. 2 is the sectional view of warpage after wafer back part attenuate, 301 is chip, 305 is the salient point generating on chip, and 306 is the diaphragm of coating chip and salient point, the wafer after the attenuate that 302a is semiconductor device; In existing technique, wafer carries out removing after the diaphragm 306 being coated on salient point after attenuate, and wafer there will be the situation of warpage.
Summary of the invention
Provide hereinafter about brief overview of the present invention, to the basic comprehension about some aspect of the present invention is provided.Should be appreciated that this general introduction is not about exhaustive general introduction of the present invention.It is not that intention is determined key of the present invention or pith, and nor is it intended to limit the scope of the present invention.Its object is only that the form of simplifying provides some concept, using this as the preorder in greater detail of discussing after a while.
The invention provides a kind of wafer level packaging technique wafer attenuate structure, comprising: wafer, multiple chips, conductive salient point; Each described chip is array distribution in described wafer one side; Described conductive salient point is formed at the surface of described chip away from described wafer; The one side that described wafer is not formed with described chip has the circulus structure of the thick intermediate thin of periphery.
Wafer level packaging technique wafer attenuate structure provided by the invention, has realized the more and more thinner target of monomer chip thickness of the semiconductor device disk encapsulation of said function, and the more important thing is and realized the target of only having small warpage after wafer back part attenuate.
Accompanying drawing explanation
In order to be illustrated more clearly in the embodiment of the present invention or technical scheme of the prior art, to the accompanying drawing of required use in embodiment or description of the Prior Art be briefly described below, apparently, accompanying drawing in the following describes is only some embodiments of the present invention, for those of ordinary skills, do not paying under the prerequisite of creative work, can also obtain according to these accompanying drawings other accompanying drawing.
Fig. 1 is sectional view after wafer rear entirety attenuate in existing technique;
Fig. 2 is the sectional view of warpage after wafer entirety attenuate in existing technique;
Fig. 3 to Fig. 5 is embodiment of the present invention wafer level packaging technique wafer attenuate structure preparation process structural representation;
Fig. 6 is wafer level packaging technique wafer attenuate structural representation in the embodiment of the present invention.
Embodiment
For making object, technical scheme and the advantage of the embodiment of the present invention clearer, below in conjunction with the accompanying drawing in the embodiment of the present invention, technical scheme in the embodiment of the present invention is clearly and completely described, obviously, described embodiment is the present invention's part embodiment, rather than whole embodiment.The element of describing in an accompanying drawing of the present invention or a kind of execution mode and feature can combine with element and feature shown in one or more other accompanying drawing or execution mode.It should be noted that for purposes of clarity, in accompanying drawing and explanation, omitted expression and the description of unrelated to the invention, parts known to persons of ordinary skill in the art and processing.Based on the embodiment in the present invention, the every other embodiment that those of ordinary skills obtain under the prerequisite of not paying creative work, belongs to the scope of protection of the invention.
The invention provides a kind of wafer level packaging technique wafer attenuate structure, as shown in Figure 6, comprise wafer 302b, multiple chips 201, conductive salient point 203; Each described chip 201 is array distribution in described wafer 302b one side; Described conductive salient point 203 is formed at the surface of described chip 201 away from described wafer; The one side that described wafer is not formed with described chip has the circulus of the thick intermediate thin of periphery.Described wafer attenuate structure provided by the invention forms circulus at the one side selectivity attenuate of wafer, and when having realized the more and more thinner requirement of wafer level packaging, wafer back part only has the target of small warpage.
Wafer is carried out to selectivity attenuate, and described selectivity attenuate is the one side that is not arranged with chip on wafer, wafer is formed with to one of salient point and faces down, and is placed on slide holder, and the one side that wafer is not formed to salient point is that selectivity ring-type attenuate is carried out at the back side of wafer.Described selectivity thining method is: utilize spherical gear to carry out ring-type polishing, by wafer mid portion attenuate, retain wafer surrounding part, form circulus.
Existing wafer thining method is wafer back part all to be removed until reach the thickness needing, this method is after wafer attenuate, tear off after the diaphragm on salient point, wafer there will be the situation of warpage, as depicted in figs. 1 and 2, and it is more severe that wafer more approaches edge warping degree, in order to reduce the warpage degree of the wafer after attenuate, the present invention gets off the most serious Edge preserving of warpage degree, form a circulus, it is thicker that the wafer of periphery retains, even if can there is buckling deformation, the thickness at edge is also enough to make warpage to become very little, with respect to existing technique, warpage has obtained very large improvement.
In technique scheme, optionally, be also formed with electrode and passivation layer at described chip away from the surface of described wafer, described conductive salient point is electrically connected with described electrode, described passivation layer is positioned at described electrode top, and described conductive salient point exposes described passivation layer surface at least partly.Described electrode is formed at chip surface, and described electrode can be also pad, and electrode (as pad) is the fuction output terminal of chip, and finally realizes the conduction transition of electrical functionality by the conductive salient point of follow-up formation.
Optionally, the mixture preparation of the following a kind of material of described passivation layer employing or multiple material: silica, silicon nitride, silicon oxynitride, polyimides, benzene three polybutene.The material of described passivation layer comprises dielectric material or their mixtures such as silica, silicon nitride, silicon oxynitride, polyimides, benzene three polybutene, for the protection of the circuit in chip 201.
It should be noted that, the pad of described chip and passivation layer can be initial pad and the initial passivation of chip, and can be also needs according to circuit layout-design the transition pad, the passivation layer that form; The mode that forms transition pad, passivation layer is mainly to adopt Wiring technique technology again, connect up again initial pad, passivation layer are reprinted on transition pad, passivation layer by one or more layers, form transition pad if pass through again Wiring technique, the conductive salient point being formed on chip is connected with last one deck electrode, and described conductive salient point exposes last one deck passivation layer surface at least partly.The described technology of Wiring technique is again existing maturation process, is well known to those skilled in the art, and does not repeat them here.
Described chip surface is formed with conductive salient point, and conductive salient point material is for having high conduction and dystectic metal material, as copper etc.For example, conductive salient point can be copper post, and the height of copper post determines according to the requirement of next encapsulation.Forming described conductive salient point is the transmission in order to realize electrical functionality, and described conductive salient point can be formed at above-mentioned electrode or bond pad surface, or form metal wiring layer again at electrode or bond pad surface, described conductive salient point is formed to metal again on wiring layer, act on identical with function, be all the transmission in order to realize electrical functionality, the concrete steps of these methods are known for the art personnel, do not repeat them here.
Optionally, on described wafer, be also provided with the scribe line for cutting described wafer.After the polishing attenuate of wafer is finished, overturn, be placed on slide holder, the wafer after attenuate is circulus, and just clamping is placed on slide holder.On described slide holder, have micro-groove, described micro-groove is used for corresponding one by one with the groove on wafer, and in the step of ensuing scribing for standard is done in its scribing.Optionally, be provided with described scribe line on the crystal column surface between different chips, described scribe line is for cutting described wafer, the chip on wafer to be cut and come respectively, forms monomer chip, so described scribe line is arranged between chip.
The manufacture method of wafer level packaging technique wafer attenuate structure provided by the invention comprises step:
S201: as shown in Figure 3, provide a wafer 202, have multiple chips 201 in the one side array distribution of wafer.
S202: as shown in Figure 4, form conductive salient point 203 at described chip 201 away from the surface of described wafer 202.
S203: as shown in Figure 5; after having formed conductive salient point 203; the one side that is formed with conductive salient point 203 at wafer 202 is pasted layer protecting film 204; described diaphragm 204 coated with conductive salient points 203; conductive salient point 203 is covered completely; in order in following step, conductive salient point 203 to be protected, be not worn.
Optionally, the material of described diaphragm 204 is epoxy resin, or is PI glue; above-mentioned material is coated salient point, plays the effect of protection, and forms described diaphragm by modes such as printing, spin coatings; these have been well-known to those skilled in the art, do not repeat them here.
S204: as shown in Figure 6; then wafer 202 being formed with to one of salient point 203 and coated with protective film 203 faces down; be placed on slide holder, do not form the one side selectivity ring-type attenuate of described conductive salient point at wafer, form the circulus 302b of the thick intermediate thin of periphery.
For the wafer in Fig. 3 to Fig. 5 202 being become to the circulus 302b of the thick intermediate thin of periphery as shown in Figure 6, need to be by using spherical gear mesh wafer 202 to polish, spherical gear also advances in rotary-grinding, until the thickness of wafer mid portion reaches the requirement of attenuate, now, original wafer 202 becomes the circulus 302b of the thick intermediate thin of periphery of circulus.
S205: by the wafer upset after ring-type attenuate, be placed on slide holder;
S206: tear the diaphragm being formed on wafer off;
S207: the wafer of removing diaphragm is tested, cut after test.
In described slide holder, also have vacuum adapter and vacuum passage, extract the air in described vacuum passage, can will be placed on wafer on slide holder and be firmly adsorbed on the surface of described slide holder, so in implementing wafer attenuate, wafer is attracted on slide holder, do not have any movement or crooked etc., after wafer attenuate, its upset is adsorbed on slide holder, has also beaten basis for following step, the situation that there will not be wafer to touch.Diaphragm 204 is the salient point on chip and chip to be protected when polishing attenuate at wafer rear, also needs to be torn off after finishing, and proceeds following step.
The wafer of removing diaphragm is tested to the electrical property of the each salient point on test chip; After test, cut apart, described in cut apart along scribe line and carry out, the chip on wafer is separated, form monomer bump chip.
The wafer level packaging technique wafer attenuate structure that the present invention proposes, by wafer back part is carried out to selectivity attenuate, after attenuate, form circulus, the more and more thinner target of monomer chip thickness in the semiconductor device wafer level packaging that has realized said function is simultaneously, adopt selectivity ring-type attenuate, realize the target of only having small warpage after wafer back part attenuate, had very large improvement with respect to existing wafer back part thinning technique.
In the embodiment such as apparatus and method of the present invention, obviously, each parts or each step reconfigure after can decomposing, combine and/or decomposing.These decomposition and/or reconfigure and should be considered as equivalents of the present invention.Simultaneously, in the above in the description of the specific embodiment of the invention, describe and/or the feature that illustrates can be used in same or similar mode in one or more other execution mode for a kind of execution mode, combined with the feature in other execution mode, or substitute the feature in other execution mode.
Should emphasize, term " comprises/comprises " existence that refers to feature, key element, step or assembly while use herein, but does not get rid of the existence of one or more further feature, key element, step or assembly or add.
Finally it should be noted that: although described above the present invention and advantage thereof in detail, be to be understood that in the case of not exceeding the spirit and scope of the present invention that limited by appended claim and can carry out various changes, alternative and conversion.And scope of the present invention is not limited only to the specific embodiment of the described process of specification, equipment, means, method and step.One of ordinary skilled in the art will readily appreciate that from disclosure of the present invention, can use carry out with the essentially identical function of corresponding embodiment described herein or obtain process, equipment, means, method or step result essentially identical with it, that existing and will be developed future according to the present invention.Therefore, appended claim is intended to comprise such process, equipment, means, method or step in their scope.
Claims (6)
1. a wafer level packaging technique wafer attenuate structure, is characterized in that, comprising: wafer, multiple chips, conductive salient point; Each described chip is array distribution in described wafer one side; Described conductive salient point is formed at the surface of described chip away from described wafer; The one side that described wafer is not formed with described chip has the circulus of the thick intermediate thin of periphery.
2. wafer level packaging technique wafer attenuate structure according to claim 1, it is characterized in that, described chip also forms electrode and passivation layer away from the surface of described wafer, described conductive salient point is electrically connected with described electrode, described passivation layer is positioned at described electrode top, and described conductive salient point exposes described passivation layer surface at least partly.
3. wafer level packaging technique wafer attenuate structure according to claim 2, is characterized in that, described electrode is pad.
4. wafer level packaging technique wafer attenuate structure according to claim 2, is characterized in that, described passivation layer adopts the mixture preparation of following a kind of material or multiple material: silica, silicon nitride, silicon oxynitride, polyimides, benzene three polybutene.
5. wafer level packaging technique wafer attenuate structure according to claim 1, is characterized in that, is also provided with the scribe line for cutting described wafer on described wafer.
6. wafer level packaging technique wafer attenuate structure according to claim 5, is characterized in that, is provided with described scribe line on the crystal column surface between different chips.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410034804.3A CN103811536A (en) | 2014-01-24 | 2014-01-24 | Wafer thinning structure for wafer level packaging technology |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410034804.3A CN103811536A (en) | 2014-01-24 | 2014-01-24 | Wafer thinning structure for wafer level packaging technology |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN103811536A true CN103811536A (en) | 2014-05-21 |
Family
ID=50708044
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201410034804.3A Pending CN103811536A (en) | 2014-01-24 | 2014-01-24 | Wafer thinning structure for wafer level packaging technology |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN103811536A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108109901A (en) * | 2016-11-25 | 2018-06-01 | 中芯国际集成电路制造(上海)有限公司 | A kind of production method of semiconductor devices |
| CN111816602A (en) * | 2020-07-21 | 2020-10-23 | 上海韦尔半导体股份有限公司 | Chip preparation method and chip |
Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20070077731A1 (en) * | 2005-09-30 | 2007-04-05 | Disco Corporation | Processing method of wafer |
| CN101345201A (en) * | 2007-07-13 | 2009-01-14 | 株式会社迪思科 | Wafer processing method |
| CN101483142A (en) * | 2008-01-11 | 2009-07-15 | 株式会社迪思科 | Lamination device manufacturing method |
| JP2009212439A (en) * | 2008-03-06 | 2009-09-17 | Fuji Electric Device Technology Co Ltd | Method of manufacturing semiconductor device and semiconductor manufacturing apparatus |
| JP2009283636A (en) * | 2008-05-21 | 2009-12-03 | Fuji Electric Device Technology Co Ltd | Production process of semiconductor device |
| CN101807542A (en) * | 2009-02-13 | 2010-08-18 | 株式会社迪思科 | The processing method of wafer |
-
2014
- 2014-01-24 CN CN201410034804.3A patent/CN103811536A/en active Pending
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20070077731A1 (en) * | 2005-09-30 | 2007-04-05 | Disco Corporation | Processing method of wafer |
| CN101345201A (en) * | 2007-07-13 | 2009-01-14 | 株式会社迪思科 | Wafer processing method |
| CN101483142A (en) * | 2008-01-11 | 2009-07-15 | 株式会社迪思科 | Lamination device manufacturing method |
| JP2009212439A (en) * | 2008-03-06 | 2009-09-17 | Fuji Electric Device Technology Co Ltd | Method of manufacturing semiconductor device and semiconductor manufacturing apparatus |
| JP2009283636A (en) * | 2008-05-21 | 2009-12-03 | Fuji Electric Device Technology Co Ltd | Production process of semiconductor device |
| CN101807542A (en) * | 2009-02-13 | 2010-08-18 | 株式会社迪思科 | The processing method of wafer |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108109901A (en) * | 2016-11-25 | 2018-06-01 | 中芯国际集成电路制造(上海)有限公司 | A kind of production method of semiconductor devices |
| CN111816602A (en) * | 2020-07-21 | 2020-10-23 | 上海韦尔半导体股份有限公司 | Chip preparation method and chip |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US9601531B2 (en) | Wafer-level packaging structure for image sensors with packaging cover dike structures corresponding to scribe line regions | |
| TW201113992A (en) | Chip package and fabrication method thereof | |
| CN104037133B (en) | Fan-out packaging method and packaging structure of wafer-level chip | |
| CN102163559A (en) | Temporary carrier bonding and detaching processes | |
| CN103400808A (en) | Wafer-level packaging structure and packaging method of image sensor | |
| CN105632911A (en) | Wafer level package method for reducing edge stress | |
| JP6393036B2 (en) | Semiconductor device and manufacturing method thereof | |
| US20130256842A1 (en) | Semiconductor device packaging structure and packaging method | |
| US8652939B2 (en) | Method and apparatus for die assembly | |
| CN103021888A (en) | Methods for fabricating integrated circuit systems including high reliability die under-fill | |
| CN103811396A (en) | Jig for wafer packaging technology | |
| CN103811357A (en) | Ultra-thin wafer level package manufacturing method | |
| CN103811536A (en) | Wafer thinning structure for wafer level packaging technology | |
| CN111710646B (en) | Polycrystalline circle scribing method and semiconductor structure | |
| CN103325692A (en) | Manufacturing method of semiconductor device fan-out flip chip packaging structure | |
| TW201643989A (en) | Semiconductor structure and manufacturing method thereof | |
| CN103247639A (en) | Wafer level packaging method and structure of image sensor | |
| JP4528758B2 (en) | Transfer tape and semiconductor device manufacturing method using the transfer tape | |
| CN102122624B (en) | Wafer packaging method | |
| US9324686B2 (en) | Semiconductor chips having improved solidity, semiconductor packages including the same and methods of fabricating the same | |
| CN203733801U (en) | Wafer thinning structure | |
| CN105655311A (en) | Wafer-level chip package backside interconnection structure and manufacturing method thereof | |
| US20070290377A1 (en) | Three Dimensional Six Surface Conformal Die Coating | |
| JP2005191485A (en) | Semiconductor device | |
| CN111627857A (en) | Packaging method and packaging structure |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| RJ01 | Rejection of invention patent application after publication |
Application publication date: 20140521 |
|
| RJ01 | Rejection of invention patent application after publication |