CN106098625A - The chip package structure of plasma scribing and manufacture method - Google Patents
The chip package structure of plasma scribing and manufacture method Download PDFInfo
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- CN106098625A CN106098625A CN201610638956.3A CN201610638956A CN106098625A CN 106098625 A CN106098625 A CN 106098625A CN 201610638956 A CN201610638956 A CN 201610638956A CN 106098625 A CN106098625 A CN 106098625A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
- H01L21/3065—Plasma etching; Reactive-ion etching
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/561—Batch processing
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/7806—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices involving the separation of the active layers from a substrate
Abstract
The invention discloses chip package structure and the manufacture method of a kind of plasma scribing, this structure includes a chip, this chip front side covers one dielectric layer, dielectric layer is contained within least one conductive pad, chip at least sidewall presents the spline-simulating of lower extension, and each teeth groove of tooth bar is curved, sidewall and the back of chip are coated with completely by one layer of passivation layer.In this structure, the back of passivation layer coating chip and sidewall, it is to avoid chip basal body exposes and causes the chip to leak electricity；The sidewall of chip rack shape, it is simple to kiss-coating, increases the adhesion of passivation layer and sidewall.The method uses plasma dry etch scribing segmentation wafer, it is to avoid blade machinery diced chip collapses the problem on limit, and avoids the problem that the chip sidewall that plasma separation method formed exposes, and improves the feasibility of technique.
Description
Technical field
The present invention relates to technical field of semiconductor encapsulation, be specifically related to chip package structure and the system of a plasma scribing
Make method.
Background technology
During the wafer-level packaging of semiconductor chip, after encapsulation, then cutting is separated into single chips, packaging efficiency
Height, low cost.And cut and generally use blade machine cuts, easily produce and collapse limit, and cutting is the longest, affect production capacity.
Plasma removes the barrier material of wafer Cutting Road position, predominantly silicon, separates the method forming single chips,
No matter from the point of view of collapsing limit or production capacity, it it is all a kind of highly desirable separation method.But, the core after plasma separation
Sheet, can expose by sidewall silicon, is easily caused electric leakage, causes chip failure.Therefore, how encapsulation chip is carried out guarantor in all directions
Protect, be a bigger challenge.
At present, in field, personnel use the technique of PECVD (physical vapour deposition (PVD)), can be preferably at Cutting Road sidewall and core
Sheet back forms a dielectric layer, but pecvd process using plasma and the hot conditions more than 200 DEG C, it is not suitable for interim
The encapsulation scheme of bonding, reason is plasma or hot conditions, acts on ephemeral key rubber alloy, makes ephemeral key rubber alloy degeneration, from
And cause other processing procedure chips to drop, and affect and follow-up tear bonding technology open.
Summary of the invention
In order to solve above-mentioned technical problem, the present invention proposes chip package structure and the making side of a kind of plasma scribing
Method, by back and the sidewall of passivation layer coating chip, it is to avoid chip silicon substrate exposes and causes chip to leak electricity；Use plasma
The chip rack shape sloped sidewall that body is formed, beneficially passivation layer preferably covers the sidewall of chip, it is ensured that passivation layer and core
The strong adhesion of sheet sidewall.
The technical scheme is that and be achieved in that:
The chip package structure of a kind of plasma scribing, including a chip, this chip front side covers one dielectric layer, described
Dielectric layer is contained within least one conductive pad, and described chip at least sidewall presents the spline-simulating of lower extension, and tooth bar is every
Individual teeth groove is curved, and sidewall and the back of described chip are coated with completely by one layer of passivation layer.
Further, the sidewall of described chip is the vertical vertical with surface, or be from chip front side to back by
Inclined plane A that gradually inside contracts or for inclined plane B gradually inside contracted to front from chip back.
Further, the tilt angle theta of described inclined plane A is in the range of 45 °≤θ 90 °, or the inclining of described inclined plane B
Rake angle θ is in the range of 90 ° of θ≤135 °.
Further, described passivation layer is photoresist or dry film.
Further, when described passivation layer is photoresist, this photoresist is positivity.
Further, when the sidewall of described chip is inclined plane, sidewall is formed with at least one step.
The manufacture method of the chip package structure of a kind of plasma scribing, comprises the steps:
A, providing a wafer comprising some chips, have Cutting Road between adjacent chips, the front of wafer is chip
Functional surfaces；
B, unify a support component at wafer frontside or back ephemeral key；
C, in wafer back part or Cutting Road position, front, using plasma dry method performs etching, formed bottom-exposed prop up
The fluting of support component, the sidewall of this fluting presents the spline-simulating of lower extension, and each teeth groove of tooth bar is curved；
D, on wafer back part or front and fluting inwall formed one layer of passivation layer, this each chip of passivation layer coated silicon wafer
Back or front and the inwall of fluting；
Passivation layer bottom E, removal wafer Cutting Road position fluting；
F, tear bonding open, form the single chips encapsulating structure separated, if be bonded support assembly at wafer back part temporarily, tear key open
After conjunction, form one layer of passivation layer at single chips back.
Further, described chip front side covers one dielectric layer, and described dielectric layer is contained within least one conductive pad, at crystalline substance
When circle is faced with during bonding support component, in step C, first make mask layer at wafer back part, and in wafer back part Cutting Road position
Put and do opening, expose the chip substrates of Cutting Road position, then, the chip base that using plasma dry etching opening exposes
Material, forms the straight trough of exposed chip front dielectric layer；Finally, utilize whole surface plasma to etch, straight trough opening be enlarged,
And etch away the dielectric layer bottom straight trough, form the skewed slot gradually inside contracted from opening to bottom.
Further, before step B, also include the step that wafer back part is thinning.
Further, described support component is a support plate or carrier film；Wafer frontside is sticked by ephemeral key rubber alloy with support plate
Together, or the cohesive force by carrier film one side, wafer frontside is sticked together with carrier film temporarily.
The invention has the beneficial effects as follows: the present invention provides chip package structure and the manufacture method of a kind of plasma scribing,
First the method forms the skewed slot (skewed slot inside contracted from opening) of through wafer to bottom in wafer Cutting Road position, and makes skewed slot
Sidewall present the spline-simulating of lower extension, and each teeth groove of tooth bar is curved, isolates chip, then uses passivation layer cladding
The back of chip and sidewall, finally tear bonding open and form the single chips separated.The method uses plasma dry etch scribing
Segmentation wafer, it is to avoid blade machinery diced chip collapses the problem on limit, and avoids the chip that plasma separation method is formed
The problem that sidewall exposes, improves the feasibility of technique.In this encapsulating structure, the back of passivation layer coating chip and sidewall, keep away
Exempt from chip silicon substrate to expose and cause chip to leak electricity；The chip rack shape sloped sidewall that plasma etching is formed, the most blunt
Change layer and preferably cover the sidewall of chip, it is to avoid the problem being difficult to remove passivation layer at the bottom land of high-aspect-ratio straight trough；And be easy to
Kiss-coating, increases the adhesion of passivation layer and sidewall.
Accompanying drawing explanation
Fig. 1 is wafer top view in the present invention；
Fig. 2 is location A section enlarged diagram in Fig. 1；
Fig. 3 is that wafer of the present invention is bonded schematic diagram with support plate；
Fig. 4 is to wafer back part schematic diagram after thinning after the present invention is bonded；
Fig. 5 is the thinning rear wafer back part resist coating of the present invention the schematic diagram of opening；
Fig. 6 is the schematic diagram that photoresist opening part plasma of the present invention removes silicon substrate；
Fig. 7 is the schematic diagram that plasma of the present invention makes sloped sidewall；
Fig. 8 is that the present invention is coated with the schematic diagram of passivation layer at chip back and sidewall；
Fig. 9 is the schematic diagram that the present invention removes the passivation layer of Cutting Road position；
Figure 10 is that wafer of the present invention tears the schematic diagram being bonded open with support plate；
Figure 11 is chips encapsulating structure schematic diagram of the present invention.
Figure 12 is the schematic diagram that chips encapsulating structure sidewall of the present invention has step.
In conjunction with accompanying drawing, make the following instructions:
1-chip 2-salient point
3-conductive pad 4-dielectric layer
5-ephemeral key rubber alloy 6-support plate
7-straight trough 8-passivation layer
9-skewed slot 10-boss
11-step A1-the first side wall
A2-the second sidewall
Detailed description of the invention
More understandable for enabling the invention to, below in conjunction with the accompanying drawings the detailed description of the invention of the present invention is done specifically
Bright.For convenience of description, in the structure of embodiment accompanying drawing, each ingredient does not presses normal rates scaling, therefore does not represent in embodiment each
The actual relative size of structure.
As shown in figure 11, the invention provides the chip package structure of a kind of plasma scribing, this structure includes a chip
1, this chip front side covers one dielectric layer 4, and dielectric layer is contained within least one conductive pad 3, a described chip at least sidewall
Presenting the spline-simulating of lower extension, and each teeth groove of tooth bar is curved, sidewall and the back of described chip are complete by one layer of passivation layer
Full cladding.In this structure, the back of passivation layer coating chip and sidewall, it is to avoid chip basal body exposes and causes the chip to leak electricity；Core
The sidewall of sheet spline-simulating, it is simple to kiss-coating, increases the adhesion of passivation layer and sidewall.
Chip can be active component (active element) or passive element (passive elements), numeral electricity
The electronic component (electronic components) of the integrated circuit such as road or analog circuit, MEMS (Micro
ElectroMechanical Systems, MEMS), microfluid system (micro fluidic systems) or utilize heat, light
Physics sensor (physical sensor) that the physical quantity variation such as line and pressure is measured, surface acoustic wave element, pressure-sensing
Device (pressure sensors), but be not limited.
It is silicon oxide, nitrogen that dielectric layer is used for protecting function element and/or the conductive pad of chip front side (functional surfaces), its material
SiClx, aluminium nitride etc..
The sidewall of chip can be the vertical vertical with surface, it is preferred that the sidewall of chip is to back from chip front side
Inclined plane A gradually inside contracted, i.e. chip sidewall are tilted to chip near the one end at back；Or, chip sidewall is carried on the back from chip
Inclined plane B that portion gradually inside contracts to front.I.e. chip sidewall is tilted to chip near the one end in front, this from opening the end of to
The sloped sidewall that portion inside contracts is conducive to passivation layer preferably to cover the sidewall of chip, and avoids the bottom land at high-aspect-ratio straight trough
Remove passivation layer.It is also preferred that the left the tilt angle theta of described inclined plane A sees Figure 11 in the range of: 45 °≤θ 90 °, or described in incline
The tilt angle theta of inclined-plane B in the range of 90 ° of θ≤135 °, the situation of inclined plane B for illustrating, θ be chip sidewall with chip just
The angle in face.Optionally, when the sidewall of chip is inclined plane A or inclined plane B, sidewall is formed with at least one step, it is simple to deep
The making of opening and the coating of passivation layer.See Figure 12, form a step 11 at inclined plane A sidewall, sidewall is considered as first
Sidewall A1 and the second sidewall A2, the first side wall and the second sidewall at least first are formed by plasma etching, have upper downward
The spline-simulating stretched.It is also preferred that the left chip sloped sidewall is formed with boss 10 away from the one end inside contracted, it is ensured that passivation layer envelopes this position
The chip sidewall put.
Preferably, passivation layer is photoresist, it is simple to exposure imaging removes the passivation layer of bottom land.It is furthermore preferred that photoresist in
Positivity, light position is removed.Compare negative photoresist, light position retains, it is to avoid it is reflective that illumination sloped sidewall causes, and leads
Remove after causing the sidewall passivation layer development needing to retain.In other embodiments, passivation layer can also is that dry film.
As shown in Figures 1 to 10, the manufacture method of the chip package structure of a kind of plasma scribing, interim in wafer frontside
Being bonded a support plate, using plasma carries out scribing from wafer back part, and forms the scribing sidewall of inclination, uses passivation layer cladding
The back of chip and sidewall, and remove the passivation layer between adjacent chips with exposure imaging mode or laser ablation, finally tear open
Bonding, i.e. isolates single encapsulation chip.
Here, chip can be active component (active element) or passive element (passive elements),
The electronic component (electronic components) of the integrated circuit such as digital circuit or analog circuit, MEMS
(Micro ElectroMechanical Systems, MEMS), microfluid system (micro fluidic systems) or profit
The physics sensor (physical sensor) measured with the physical quantity variation such as heat, light and pressure, surface acoustic wave element,
Pressure sensor (pressure sensors), but be not limited.
See Fig. 1, for comprising the wafer of some chips.Chip front side has some salient points 2, and salient point can be soldered ball, gold
Belong to post or other protrusion metal structure.Preferably, described salient point includes metal salient point and ubm layer, and described metal is convex
Point is or/and described ubm layer is made up of one or more layers metal.More excellent, every layer of metal of ubm layer is permissible
For the one in titanium, chromium, tungsten, copper, nickel, gold, silver, stannum；Every layer of metal of metal salient point is the one in copper, stannum, silver, gold.Often
The metal salient point seen has copper post, principal column, stannum salient point, au bump and hybrid metal salient point etc..
Seeing Fig. 2, metal salient point is copper post and the combination of top stannum salient point thereof.For convenience of diagram, Fig. 2 gives on wafer
Two chip unit structures at A in the structure of two adjacent cells, i.e. Fig. 1, other chip units are same, as one
Citing, the structure of each chip is: chip is silicon substrate, and chip front side covers one dielectric layer 4, and dielectric layer is contained within least one
Conductive pad 3, conductive pad is drawn electrically by salient point 2.
See Fig. 3, by wafer frontside and a support plate 6 by ephemeral key rubber alloy 5 glutinous together with.Support plate can be Silicon Wafer,
The panel (Panel) of glass, the wafer of other semiconductor bases or other suitable materials.Ephemeral key rubber alloy can be by wafer and support plate
It is bonded to together, and the character of ephemeral key rubber alloy is can be dropped by modes such as the chemical solution dissolving of corresponding types, pyrolysis, photodissociation
The viscosity of low glue, to realize tearing open the purpose of bonding.
Preferably, the thickness of described slide glass is more than 300 microns, to reach enough supporting role.
In other embodiments, wafer frontside pastes a carrier film temporarily, substitutes the support plate of interim bonding.Carrier film has one
Fixed mechanical strength, and carrier film one side there is certain cohesive force.Carrier film such as grinding wafer film.
See Fig. 4, under the supporting role of support plate, thinned wafer back, it is thinned near target silicon thickness.Preferably, greatly
In thick 20 microns to 40 microns of target silicon.Thinning mode includes grinding, etching, one or more of polishing etc..
Seeing Fig. 5, the wafer back part after thinning makes mask layer, and does opening, cruelly in wafer Cutting Road position (SL)
Expose the silicon substrate of Cutting Road position.This mask layer can be photoresist, and corresponding opening manufacture method is exposure imaging.
See Fig. 6, the silicon substrate that the above-mentioned opening of plasma dry etch exposes, etch straight trough 7.Etching removes cutting
The silicon of position, road, exposes the dielectric layer bottom silicon material, such as silicon oxide, silicon nitride etc..After etched, remove mask layer.
See Fig. 7, utilize whole surface plasma to etch, straight trough upper shed is enlarged, and etch away the dielectric of bottom land
Layer, forms the skewed slot 9 gradually inside contracted from opening to bottom.Owing to being whole etching, wafer thickness now can reduce further,
Regulation etching parameters, completes openings of sizes, dielectric layer etching degree is mated with chip target thickness, makes the dielectric bottom skewed slot
Layer is removed completely.
See Fig. 8, wafer back part is coated passivation layer 8.Preferably cover owing to straight trough becomes skewed slot 9, beneficially passivation layer
The sidewall of cover core sheet, it is preferred that the coating method of passivation layer is spraying (spray), it is simple to control the uniformity and the groove of passivation layer
The thickness of end passivation layer.
See Fig. 9, remove the passivation layer of Cutting Road position, make the passivation layer between adjacent chips be separated from each other.Preferably,
This passivation layer is positive photoresist, and by being exposed the photoresist bottom Cutting Road, then development is removed by illumination position
Photoresist.Comparing negative photoresist, light position retains, it is to avoid it is reflective that illumination sloped sidewall causes, and causes needing to protect
Remove after the sidewall passivation layer development stayed.In other embodiments, remove the passivation bottom Cutting Road also by laser ablation etc.
Layer, makes adjacent chips separate.
Seeing Figure 10, tear bonding open, separate wafer and slide glass, now chip has been single.Tear the mode of bonding open, corresponding interim
The character of bonding glue, as with chemical solution dissolving, pyrolysis, photodissociation etc..Preferably, complete passivation layer bottom wafer Cutting Road to remove
After technique, wafer back part and a protection adhesive tape are adhered to, then carries out solving bonding.After being easy to tear bonding open, wafer holds.This guarantor
Retaining tape can have photodissociation or pyrolysis characteristics, can easily isolate wafer after making processing procedure complete.Protect adhesive tape such as UV film, cut
Cut film.
In other embodiments, at one support component of wafer back part temporary adhesion, wafer frontside Cutting Road position can be adopted
Perform etching by plasma dry, form sloped sidewall；With front and the sidewall of passivation layer coating chip, remove wafer cutting
The passivation layer of position, road, removes a support component at back, is coated with a passivation layer at its back.
Above example is referring to the drawings, to a preferred embodiment of the present invention will be described in detail.Those skilled in the art
Member by above-described embodiment being carried out the amendment on various forms or change, but without departing substantially from the essence of the present invention in the case of, all
Fall within the scope and spirit of the invention.
Claims (10)
1. the chip package structure of a plasma scribing, it is characterised in that: including a chip, this chip front side covers one layer of Jie
Electric layer, described dielectric layer is contained within least one conductive pad, and described chip at least sidewall presents the spline-simulating of lower extension, and
Each teeth groove of tooth bar is curved, and sidewall and the back of described chip are coated with completely by one layer of passivation layer.
The chip package structure of plasma scribing the most according to claim 1, it is characterised in that the sidewall of described chip be with
The vertical that surface is vertical, or for inclined plane A that gradually inside contracts to back from chip front side or for from chip back to front
Inclined plane B gradually inside contracted.
The chip package structure of plasma scribing the most according to claim 2, it is characterised in that the inclination of described inclined plane A
Angle, θ is in the range of 45 °≤θ 90 °, or the tilt angle theta of described inclined plane B is in the range of 90 ° of θ≤135 °.
The chip package structure of plasma scribing the most according to claim 1, it is characterised in that described passivation layer is photoresist
Or dry film.
The chip package structure of plasma scribing the most according to claim 4, it is characterised in that described passivation layer is photoresist
Time, this photoresist is positivity.
The chip package structure of plasma scribing the most according to claim 2, it is characterised in that the sidewall of described chip is for inclining
During inclined-plane, sidewall is formed with at least one step.
7. the manufacture method of the chip package structure of a plasma scribing, it is characterised in that: comprise the steps:
A, providing a wafer comprising some chips, have Cutting Road between adjacent chips, the front of wafer is the function of chip
Face；
B, unify a support component at wafer frontside or back ephemeral key；
C, in wafer back part or Cutting Road position, front, using plasma dry method performs etching, formed bottom-exposed support group
The fluting of part, the sidewall of this fluting presents the spline-simulating of lower extension, and each teeth groove of tooth bar is curved；
D, on wafer back part or front and fluting inwall formed one layer of passivation layer, the back of the body of this each chip of passivation layer coated silicon wafer
Portion or front and the inwall of fluting；
Passivation layer bottom E, removal wafer Cutting Road position fluting；
F, tear bonding open, form the single chips encapsulating structure separated, if be bonded support assembly at wafer back part temporarily, tear bonding open
After, form one layer of passivation layer at single chips back.
The manufacture method of the chip package structure of plasma scribing the most according to claim 7, it is characterised in that described chip
Front covers one dielectric layer, and described dielectric layer is contained within least one conductive pad, when wafer frontside is bonded support assembly temporarily,
In step C, first make mask layer at wafer back part, and do opening in wafer back part Cutting Road position, expose Cutting Road position
Chip substrates, then, the chip substrates that using plasma dry etching opening exposes, form exposed chip front dielectric layer
Straight trough；Finally, utilize whole surface plasma to etch, straight trough opening be enlarged, and etch away the dielectric layer bottom straight trough,
Form the skewed slot gradually inside contracted from opening to bottom.
The manufacture method of the chip package structure of plasma scribing the most according to claim 7, it is characterised in that in step B
Before, the step that wafer back part is thinning is also included.
The manufacture method of the chip package structure of plasma scribing the most according to claim 7, it is characterised in that described
Support component is a support plate or carrier film；Wafer frontside and support plate by ephemeral key rubber alloy glutinous together with, or by carrier film one side
Cohesive force, wafer frontside is sticked together with carrier film temporarily.
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| CN106960829A (en) * | 2017-05-11 | 2017-07-18 | 北京工业大学 | A kind of structure for alleviating chip package stress and preparation method thereof |
| CN109461701A (en) * | 2018-09-27 | 2019-03-12 | 全球能源互联网研究院有限公司 | A kind of compound dicing method and semiconductor devices of power chip |
| CN110970362A (en) * | 2018-09-28 | 2020-04-07 | 典琦科技股份有限公司 | Method for manufacturing chip package |
| CN110970361A (en) * | 2018-09-28 | 2020-04-07 | 典琦科技股份有限公司 | Method for manufacturing chip package |
| CN111298854A (en) * | 2020-02-27 | 2020-06-19 | 西人马联合测控（泉州）科技有限公司 | Chip forming method and wafer |
| CN111446158A (en) * | 2020-03-05 | 2020-07-24 | 绍兴同芯成集成电路有限公司 | Metal deposition process after wafer back cutting |
| CN111463134A (en) * | 2019-01-18 | 2020-07-28 | 典琦科技股份有限公司 | Method for manufacturing chip package |
| CN112018027A (en) * | 2019-05-31 | 2020-12-01 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor structure, forming method thereof and wafer cutting method |
| CN112992780A (en) * | 2019-12-16 | 2021-06-18 | 美光科技公司 | Process for sizing dielectric bond wire material and related films, articles, and assemblies |
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