CN204558453U - Improve wafer packaging structure and the chip-packaging structure of solder mask stripping - Google Patents
Improve wafer packaging structure and the chip-packaging structure of solder mask stripping Download PDFInfo
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- CN204558453U CN204558453U CN201520190729.XU CN201520190729U CN204558453U CN 204558453 U CN204558453 U CN 204558453U CN 201520190729 U CN201520190729 U CN 201520190729U CN 204558453 U CN204558453 U CN 204558453U
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Abstract
The utility model discloses a kind of wafer packaging structure and the chip-packaging structure that improve solder mask stripping, wafer packaging structure comprise there is some chip units wafer, be laid on insulating barrier, metal pattern and solder mask on wafer substrate surface successively, metal pattern comprise metal wiring layer or/and according to wiring needs design metal auxiliary patterns, have a width metal lines road easily causing solder mask to peel off in each metallic circuit of metal wiring layer at least, width metal lines road is formed with one or more metal breach; Metal auxiliary patterns comprises at least one large stretch of metal derby easily causing solder mask to peel off, and large stretch of metal derby is formed with one or more metal breach.This metal breach effectively can reduce the contact area between solder mask and metal wiring layer, increases the bonded area between insulating barrier and solder mask, thus avoids solder mask to peel off from metal wiring layer, for the reliability of chip provides safeguard.
Description
Technical field
The utility model relates to wafer stage chip encapsulation technology field, specifically relates to a kind of wafer packaging structure and the chip-packaging structure that improve solder mask stripping.
Background technology
The general packaged type of wafer stage chip is: first, and form groove on wafer one surface containing some chip units, this groove can be used for reducing packaging height, also can be used for the conductive welding pad exposing wafer; Then, in groove and wafer substrate surface lay a layer insulating; Again then, lay the metal wiring layer of one deck electrical connection conductive welding pad on the insulating layer, gone by the electrical extraction of metal wiring layer by the conductive welding pad of wafer, then, metal wiring layer is formed one deck solder mask, be corroded for preventing metal wiring layer or be oxidized, finally, packaged wafer packaging structure being cut into single wafer stage chip encapsulating structure; In above-mentioned wafer-grade chip packaging process, because the wires design of metal wiring layer needs, the width of each metallic circuit in metal wiring layer may be inconsistent, namely many metallic traces that width is different may be there are, and the wider metallic circuit of some of them can make the contact area of solder mask and metal wiring layer increase, and adhesion between solder mask and metal is weak relative to the adhesion between itself and insulating barrier, easily cause solder mask to peel off from metal wiring layer, the reliability of chip is caused a hidden trouble.
In above-mentioned wafer-grade chip packaging process, the groove formed normally has the groove structure of ramped shaped sidewall, wires design for metal wiring layer needs, the slope that may there is groove the first side wall is equipped with metallic circuit, and relative the second sidewall of groove is not laid the situation of metallic circuit, owing to usually using the photoresist patterned Seed Layer metal seeing light reaction easily removed in the photoetching process of formation metal wiring layer, therefore, in exposure manufacture process, light beam can reflect on the second sidewall, cause the photoresist on the first side wall on opposite photosensitive, thus the metallic circuit that destruction the first side wall designs, cause metallic circuit open circuit.In order to avoid above-mentioned situation occurs, need to lay corresponding photoresist at the second sidewall, form assistant metal pattern through successive process.And some wider large stretch of metal derbies in assistant metal pattern, may be there are, also the contact area of solder mask and metal wiring layer is made to increase, and then cause the adhesion of solder mask to die down, easily cause solder mask to peel off from metal wiring layer, the reliability of chip is caused a hidden trouble.
In addition, when wafer substrate surface forms metal wiring layer, because wires design needs, there is the situation needing to establish on wafer substrate surface large stretch of metal derby according to wires design, therefore, also easily cause solder mask to peel off from metal wiring layer, the reliability of chip is caused a hidden trouble.
Summary of the invention
In order to solve the problems of the technologies described above, the utility model proposes a kind of wafer packaging structure and the chip-packaging structure that improve solder mask stripping, effectively can reduce the contact area between solder mask and metal wiring layer, increase the bonded area between insulating barrier and solder mask, thus avoid solder mask to peel off from metal wiring layer, for the reliability of chip provides safeguard.
The technical solution of the utility model is achieved in that
A kind of wafer packaging structure improving solder mask and peel off, comprise the wafer with some chip units, the insulating barrier be laid on described wafer substrate surface, the solder mask that is laid on the metal pattern on described insulating barrier and is laid on described metal pattern, described metal pattern comprises the metal wiring layer of the electrical derivation of wafer conductive welding pad, have a width metal lines road easily causing described solder mask to peel off in each metallic circuit of described metal wiring layer at least, described width metal lines road is formed with the metal breach that at least one does not block this width metal lines road; Or described metal pattern also comprises the metal auxiliary patterns according to the design of wiring needs, described metal auxiliary patterns comprises at least one large stretch of metal derby easily causing described solder mask to peel off, and described large stretch of metal derby is formed with the metal breach that at least one does not block this large stretch of metal derby.
As further improvement of the utility model, when being provided with described width metal lines road, described metal breach is positioned at the edge on described width metal lines road or/and inside; When being provided with described large stretch of metal derby, described metal breach is positioned at the edge of described large stretch of metal derby or/and inside.
As further improvement of the utility model, when being provided with described width metal lines road, described wafer substrate surface is formed with the groove exposing wafer conductive welding pad, described groove comprises the relative the first side wall of ramped shaped and the second sidewall, described the first side wall is equipped with successively described insulating barrier, described metal wiring layer and described solder mask, have in described metal wiring layer and extend to this groove bottom land plane, and connect the described width metal lines road of at least one weld pad, described width metal lines road is formed with described metal breach.
As further improvement of the utility model, described second sidewall is equipped with successively described insulating barrier, described metal auxiliary patterns and described solder mask, there is in described metal auxiliary patterns the described large stretch of metal derby extending to this groove bottom land plane, described large stretch of metal derby is formed with described metal breach.
As further improvement of the utility model, when being provided with described large stretch of metal derby, described wafer substrate surface is formed for reducing packaging height or the groove exposing wafer conductive welding pad, described groove comprises the relative the first side wall of ramped shaped and the second sidewall, described the first side wall is equipped with described insulating barrier successively, described metal wiring layer and described solder mask, described second sidewall is equipped with described insulating barrier successively, described metal auxiliary patterns and described solder mask, not there is in described metal wiring layer described width metal lines road, there is in described metal auxiliary patterns the described large stretch of metal derby extending to this groove bottom land plane, described large stretch of metal derby is formed with described metal breach.
As further improvement of the utility model, described groove is between adjacent two chip units of described wafer, the first side wall of described groove has the metallic circuit of two vicinities in metal wiring layer at least, second sidewall of described groove is to the position of metallic circuit forming described large stretch of metal derby, and described large stretch of metal derby extends to the bottom land of described groove by wafer substrate surface.
As further improvement of the utility model, when being provided with described large stretch of metal derby, described large stretch of metal derby is positioned on the plan position approach on described wafer substrate surface, and described large stretch of metal derby is formed with described metal breach.
As further improvement of the utility model, the shape of described metal breach is for closing or semi-enclosed arc, polygon or irregular figure.
Improve the chip-packaging structure that solder mask is peeled off, the encapsulating structure of arbitrary single chips that the wafer packaging structure for the stripping of described improvement solder mask is formed after the cutting of predetermined cuts road.
The beneficial effects of the utility model are: the utility model provides a kind of wafer packaging structure and the chip-packaging structure that improve solder mask stripping, one or several metal breach is carved by the edge on metal derby large stretch of in the metal pattern of wafer or width metal lines road and/or centre, the contact area of solder mask and metal pattern can be effectively reduced, increase the bonded area of solder mask and insulating barrier simultaneously, have larger improvement to the stripping of solder mask.Meanwhile, the cumulative stress also caused the existence of metal derby large stretch of on insulating barrier has alleviation to a certain degree.
Accompanying drawing explanation
Fig. 1 is metal notch geometry schematic diagram in the utility model embodiment;
Fig. 2 is width metal lines road schematic diagram in the utility model embodiment 1;
Fig. 3 is large stretch of metal derby schematic diagram in the utility model embodiment 2;
Fig. 4 is for A-A in Fig. 3 after coating solder mask is to generalized section.
By reference to the accompanying drawings, make the following instructions:
1---substrate 2---insulating barrier
3---solder mask 4---metal pattern
41---width metal lines road 42---large stretch of metal derby
411,421---metal breach 43---metallic circuit
6---groove 601---the first side wall
602---second sidewall 7---conductive welding pad
8---predetermined cuts road 9---cutting groove
10---operator guards
Embodiment
For enabling the utility model more become apparent, below in conjunction with accompanying drawing, the specific embodiment of the present invention is described in detail.For convenience of description, in the structure of embodiment accompanying drawing, each part does not press normal rates convergent-divergent, therefore does not represent the actual relative size of each structure in embodiment.
Embodiment 1
As shown in Figure 2, a kind of wafer packaging structure improving solder mask 3 and peel off, comprise the wafer with some chip units, be laid on the insulating barrier 2 on described wafer substrate 1 surface, the solder mask 3 being laid on the metal pattern on described insulating barrier 2 and being laid on described metal pattern, described metal pattern comprises the metal wiring layer of the electrical derivation of wafer conductive welding pad 7, a width metal lines road 41 easily causing described solder mask 3 to peel off is had at least in each metallic circuit of described metal wiring layer, described width metal lines road 41 is formed with the metal breach 411 that at least one does not block this width metal lines road 41,
Preferably, the width on width metal lines road 41 is greater than 300 microns, and described metal breach is positioned at the edge on described width metal lines road 41 or/and inside, and the shape of metal breach is closed or semi-enclosed arc, polygon or irregular figure, see Fig. 1.
Preferably, see Fig. 2, described wafer substrate 1 surface is formed with the groove 6 for exposing wafer conductive welding pad 7, described groove 6 is between adjacent two chip units of described wafer, described groove 6 comprises the relative the first side wall of ramped shaped 601 and the second sidewall 602, described the first side wall 601 is equipped with described insulating barrier 2 successively, described metal wiring layer and described solder mask, there is in described metal wiring layer the described width metal lines road 41 extending to this groove bottom land, position near line of cut on described width metal lines road 41 is formed with described metal breach 411, to make the more effective insulating barrier 2 caught under metal wiring layer of the solder mask 3 on metal wiring layer, improve the stripping of solder mask 3.
One or several metal breach 411 is carved by (edge and/or centre) on the width metal lines road 41 that exists in the metal pattern of wafer (comprising on groove 6 the first side wall 601 and groove bottom land) in the present embodiment 1, the contact area of solder mask 3 and metal pattern 4 can be effectively reduced, increase solder mask 3 and the bonded area of insulating barrier 2 simultaneously, have larger improvement to the stripping of solder mask 3.
Embodiment 2
As shown in 3 and Fig. 4, a kind of wafer packaging structure improving solder mask 3 and peel off, comprise the wafer with some chip units, be laid on the insulating barrier 2 on described wafer substrate 1 surface, the solder mask 3 being laid on the metal pattern on described insulating barrier 2 and being laid on described metal pattern, described metal pattern comprises the metal wiring layer of the electrical derivation of wafer conductive welding pad 7, described metal pattern also comprises the metal auxiliary patterns according to the design of wiring needs, described metal auxiliary patterns comprises at least one large stretch of metal derby 42 easily causing described solder mask 3 to peel off, described large stretch of metal derby 42 is formed with the metal breach 421 that at least one does not block this large stretch of metal derby 42.
Preferably, large stretch of metal derby 42 is covering 300 micron of * 100 ym square block, and described metal breach is positioned at the edge of described large stretch of metal derby 42 or/and inside.The shape of metal breach is closed or semi-enclosed arc, polygon or irregular figure, see Fig. 1.
Preferably, described wafer substrate 1 surface is formed for reducing packaging height or the groove 6 exposing wafer conductive welding pad 7, described groove 6 comprises the relative the first side wall of ramped shaped 601 and the second sidewall 602, described the first side wall 601 is equipped with described insulating barrier 2 successively, described metal wiring layer and described solder mask, described second sidewall 602 is equipped with described insulating barrier 2 successively, described metal auxiliary patterns and described solder mask, not there is in described metal wiring layer described width metal lines road, there is in described metal auxiliary patterns the described large stretch of metal derby 42 extending to this groove bottom land plane, described large stretch of metal derby 42 is formed with described metal breach 421.
Preferably, see Fig. 3 and Fig. 4, described groove 6 is between adjacent two chip units of described wafer, bottom groove 6 between adjacent two chip units, cutting groove 9 is carved with in the position in corresponding wafer predetermined cuts road 8, the first side wall 601 of described groove 6 has the metallic circuit of two vicinities in metal wiring layer at least, metallic circuit connects conductive welding pad 7, is electrically drawn out on non-functional of wafer by corresponding chip unit; Second sidewall 602 of described groove 6 is to the position of metallic circuit forming described large stretch of metal derby 42, and described large stretch of metal derby 42 is extended to the bottom land of described groove 6 by wafer substrate 1 surface.In Fig. 4, operator guards 10 has the effect such as functional section or supporting wafer, and concrete structure requires design according to chip, has omission in the diagram.
One or several metal breach 421 is carved by (edge and/or centre) on large stretch of metal derby 42 of existing in the metal pattern of wafer (non-functional extends to groove bottom land plane through groove 6 second sidewall 602 by wafer) in the present embodiment 2, the contact area of solder mask 3 and metal pattern can be effectively reduced, increase solder mask 3 and the bonded area of insulating barrier 2 simultaneously, have larger improvement to the stripping of solder mask 3.Meanwhile, the cumulative stress also caused the existence of metal derby 42 large stretch of on insulating barrier 2 has alleviation to a certain degree.
Embodiment 3
A kind of wafer packaging structure improving solder mask and peel off, comprise the wafer with some chip units, the insulating barrier 2 be laid on described wafer substrate surface, the solder mask that is laid on the metal pattern on described insulating barrier and is laid on described metal pattern, described metal pattern comprises the metal wiring layer of the electrical derivation of wafer conductive welding pad, have a width metal lines road easily causing described solder mask to peel off in each metallic circuit of described metal wiring layer at least, described width metal lines road is formed with the metal breach that at least one does not block this width metal lines road; And described metal pattern also comprises the metal auxiliary patterns according to the design of wiring needs, described metal auxiliary patterns comprises at least one large stretch of metal derby easily causing described solder mask to peel off, and described large stretch of metal derby is formed with the metal breach that at least one does not block this large stretch of metal derby.And described wafer substrate surface is formed for reducing packaging height or the groove exposing wafer conductive welding pad, described groove is between adjacent two chip units of described wafer, described groove comprises the relative the first side wall of ramped shaped and the second sidewall, described the first side wall is equipped with successively described insulating barrier, described metal wiring layer and described solder mask, have in described metal wiring layer and extend to this groove bottom land plane, and connect the width metal lines road of at least one weld pad, described width metal lines road is formed with described metal breach; Described second sidewall is equipped with successively described insulating barrier 2, described metal auxiliary patterns and described solder mask, there is in described metal auxiliary patterns the described large stretch of metal derby extending to this groove bottom land plane, described large stretch of metal derby is formed with described metal breach.
One or several metal breach is all carved by (edge and/or centre) on the width metal lines road that exists in the metal pattern of wafer (non-functional extends to groove bottom land plane through groove the first side wall and the second sidewall by wafer) and large stretch of metal derby in the present embodiment 3, the contact area of solder mask and metal pattern can be effectively reduced, increase the bonded area of solder mask and insulating barrier simultaneously, have larger improvement to the stripping of solder mask.Meanwhile, the cumulative stress also caused the existence of metal derby large stretch of on insulating barrier has alleviation to a certain degree.
Embodiment 4
A kind of wafer packaging structure improving solder mask and peel off, comprise the wafer with some chip units, be laid on the insulating barrier on described wafer substrate surface, the solder mask being laid on the metal pattern on described insulating barrier and being laid on described metal pattern, described metal pattern comprises the metal wiring layer of the electrical derivation of wafer conductive welding pad, described metal pattern also comprises the metal auxiliary patterns according to the design of wiring needs, described metal auxiliary patterns comprises at least one large stretch of metal derby easily causing described solder mask to peel off, described large stretch of metal derby is formed with the metal breach that at least one does not block this large stretch of metal derby.And described large stretch of metal derby is positioned on the plan position approach on described wafer substrate surface, and described large stretch of metal derby is formed with described metal breach.
One or several metal breach is all carved by (edge and/or centre) on large stretch of metal derby of existing in the metal pattern of wafer (on the plan position approach of substrate surface) in the present embodiment 4, the contact area of solder mask and metal pattern can be effectively reduced, increase the bonded area of solder mask and insulating barrier simultaneously, have larger improvement to the stripping of solder mask.Meanwhile, the cumulative stress also caused the existence of metal derby large stretch of on insulating barrier has alleviation to a certain degree.
In above-described embodiment 1-4, width metal lines road and large stretch of metal derby are relative concepts, and the area of the width of different chip metal circuits and large stretch of metal derby of design is all not quite similar, and peel off be limited can cause solder mask; Concrete width metal lines road can be that the metallic circuit connecting single conductive welding pad extends to both sides as required and formed, and also can be to connect adjacent two or more conductive welding pad metallic circuits to connect formation.The size of metal breach is determined according to actual needs, as long as this metal breach does not block metallic circuit, can guarantee that metallic circuit electrically conducts well.Wherein the type of chip unit can for having the functional chip of more conductive welding pad, as image sensor chip, and chip of micro-electro-mechanical system, fingerprint recognition chip etc., but be not limited thereto.
Improve the chip-packaging structure that solder mask is peeled off, it is the encapsulating structure of arbitrary single chips that the wafer packaging structure improving solder mask stripping in above-described embodiment 1-4 is formed after the cutting of predetermined cuts road.The chip-packaging structure peeled off owing to improving solder mask is formed by the wafer packaging structure cutting of improving solder mask stripping, therefore, this chip-packaging structure also effectively can reduce the contact area between solder mask and metal wiring layer, increase the bonded area between insulating barrier 2 and solder mask, thus avoid solder mask to peel off from metal wiring layer, for the reliability of chip provides safeguard, meanwhile, the cumulative stress also caused the existence of metal derby large stretch of on insulating barrier 2 has alleviation to a certain degree.
Above embodiment is with reference to accompanying drawing, is described in detail to preferred embodiment of the present utility model.Those skilled in the art by carrying out amendment on various forms or change to above-described embodiment, but when not deviating from essence of the present utility model, drops within protection range of the present utility model.
Claims (9)
1. the wafer packaging structure improving solder mask and peel off, comprise the wafer with some chip units, be laid on the insulating barrier (2) on described wafer substrate (1) surface, the solder mask (3) being laid on the metal pattern (4) on described insulating barrier and being laid on described metal pattern, described metal pattern comprises the metal wiring layer of the electrical derivation of wafer conductive welding pad (7), it is characterized in that: the width metal lines road (41) having at least easily to cause described solder mask to peel off in each metallic circuit (43) of described metal wiring layer, described width metal lines road is formed with the metal breach (411) that at least one does not block this width metal lines road, or described metal pattern also comprises the metal auxiliary patterns according to the design of wiring needs, described metal auxiliary patterns comprises at least one large stretch of metal derby (42) easily causing described solder mask to peel off, and described large stretch of metal derby is formed with the metal breach (421) that at least one does not block this large stretch of metal derby.
2. the wafer packaging structure improving solder mask and peel off according to claim 1, it is characterized in that: when being provided with described width metal lines road, described metal breach is positioned at the edge on described width metal lines road or/and inside; When being provided with described large stretch of metal derby, described metal breach is positioned at the edge of described large stretch of metal derby or/and inside.
3. the wafer packaging structure improving solder mask and peel off according to claim 1, it is characterized in that: when being provided with described width metal lines road, described wafer substrate surface is formed with the groove (8) exposing wafer conductive welding pad, described groove comprises the relative the first side wall of ramped shaped (601) and the second sidewall (602), described the first side wall is equipped with described insulating barrier successively, described metal wiring layer and described solder mask, have in described metal wiring layer and extend to this groove bottom land plane, and connect the described width metal lines road of at least one weld pad, described width metal lines road is formed with described metal breach.
4. the wafer packaging structure improving solder mask and peel off according to claim 3, it is characterized in that: described second sidewall is equipped with successively described insulating barrier, described metal auxiliary patterns and described solder mask, there is in described metal auxiliary patterns the described large stretch of metal derby extending to this groove bottom land plane, described large stretch of metal derby is formed with described metal breach.
5. the wafer packaging structure improving solder mask and peel off according to claim 1, it is characterized in that: when being provided with described large stretch of metal derby, described wafer substrate surface is formed for reducing packaging height or the groove (6) exposing wafer conductive welding pad, described groove comprises the relative the first side wall of ramped shaped (601) and the second sidewall (602), described the first side wall is equipped with described insulating barrier successively, described metal wiring layer and described solder mask, described second sidewall is equipped with described insulating barrier successively, described metal auxiliary patterns and described solder mask, not there is in described metal wiring layer described width metal lines road, there is in described metal auxiliary patterns the described large stretch of metal derby extending to this groove bottom land plane, described large stretch of metal derby is formed with described metal breach.
6. the wafer packaging structure that the improvement solder mask according to claim 4 or 5 is peeled off, it is characterized in that: described groove is between adjacent two chip units of described wafer, the first side wall of described groove has the metallic circuit of two vicinities in metal wiring layer at least, second sidewall of described groove is to the position of metallic circuit forming described large stretch of metal derby, and described large stretch of metal derby extends to the bottom land of described groove by wafer substrate surface.
7. the wafer packaging structure improving solder mask and peel off according to claim 1, it is characterized in that: when being provided with described large stretch of metal derby, described large stretch of metal derby is positioned on the plan position approach on described wafer substrate surface, and described large stretch of metal derby is formed with described metal breach.
8. the wafer packaging structure improving solder mask and peel off according to claim 1, is characterized in that: the shape of described metal breach is for closing or semi-enclosed arc, polygon or irregular figure.
9. improve the chip-packaging structure that solder mask is peeled off, it is characterized in that: the encapsulating structure of arbitrary single chips that the wafer packaging structure that described chip-packaging structure is peeled off for the improvement solder mask described in any one of claim 1 to 8 is formed after the cutting of predetermined cuts road.
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| CN201520190729.XU CN204558453U (en) | 2015-04-01 | 2015-04-01 | Improve wafer packaging structure and the chip-packaging structure of solder mask stripping |
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| CN201520190729.XU CN204558453U (en) | 2015-04-01 | 2015-04-01 | Improve wafer packaging structure and the chip-packaging structure of solder mask stripping |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106098625A (en) * | 2016-08-08 | 2016-11-09 | 华天科技（昆山）电子有限公司 | The chip package structure of plasma scribing and manufacture method |
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2015
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106098625A (en) * | 2016-08-08 | 2016-11-09 | 华天科技（昆山）电子有限公司 | The chip package structure of plasma scribing and manufacture method |
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