CN111769098B - Packaging structure and packaging method for realizing integration of multiple chips - Google Patents
Packaging structure and packaging method for realizing integration of multiple chips Download PDFInfo
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- CN111769098B CN111769098B CN202010657091.1A CN202010657091A CN111769098B CN 111769098 B CN111769098 B CN 111769098B CN 202010657091 A CN202010657091 A CN 202010657091A CN 111769098 B CN111769098 B CN 111769098B
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- 230000010354 integration Effects 0.000 title claims abstract description 21
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- 239000004065 semiconductor Substances 0.000 abstract description 2
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- 229910052751 metal Inorganic materials 0.000 description 15
- 238000004519 manufacturing process Methods 0.000 description 8
- 239000000463 material Substances 0.000 description 7
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 238000000465 moulding Methods 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
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- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- 206010063385 Intellectualisation Diseases 0.000 description 1
- 238000004458 analytical method Methods 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 239000010949 copper Substances 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 230000017525 heat dissipation Effects 0.000 description 1
- 239000012778 molding material Substances 0.000 description 1
- 239000005022 packaging material Substances 0.000 description 1
- 238000012858 packaging process Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/535—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including internal interconnections, e.g. cross-under constructions
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
- H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
- H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L25/0655—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00 the devices being arranged next to each other
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/50—Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00
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Abstract
The invention relates to a packaging structure and a packaging method for realizing integration of a plurality of chips, belongs to the technical field of semiconductor packaging, and solves the problem that the number of integrated chips of the packaging structure in the prior art is limited. The package structure includes a package body, the package body includes: the chip integration device comprises a substrate, a plurality of first grooves and a plurality of second grooves, wherein the surface of the substrate is provided with the first grooves, and the first grooves are used for arranging a plurality of chips to be integrated; the integrated special-shaped adapter plate is positioned on the upper part of the substrate and used for realizing interconnection among the plurality of chips; and the projection of each chip on the substrate is at least partially not coincident with the projection of the adapter plate on the substrate; and the projection of each chip and the projection of the adapter plate on the substrate are not overlapped, so that the chip and an external signal are interconnected. The interconnection among a plurality of chips is realized, and a complete system with high integration among a plurality of chips is formed.
Description
Technical Field
The invention relates to the technical field of semiconductor packaging, in particular to a packaging structure and a packaging method for realizing integration of a plurality of chips.
Background
Along with the development of miniaturization, integration and intellectualization of electronic products, the complexity of a chip is greatly increased, the number of corresponding I/Os pins is also greatly increased, and the complexity of packaging is improved.
In the existing heterogeneous integration technology, a 2.5D interposer with Through Silicon Vias (TSVs) is usually used to realize interconnection between chips and substrates, thereby realizing high-density integration.
However, the TSV manufacturing process is complex, the manufacturing cost is high, the yield is low, and great challenges are brought to the realization of large-scale and multi-type integration among chips. In order to solve the problem that the conventional interposer technology can only integrate a limited number of chips, a new package structure is urgently needed.
Disclosure of Invention
In view of the foregoing analysis, embodiments of the present invention are directed to a package structure and a packaging method for implementing integration of multiple chips, so as to solve the problem of limited number of integrated chips in the existing package structure.
In one aspect, an embodiment of the present invention provides a package structure for implementing integration of multiple chips, where the package structure includes a package body; the package body includes: the chip integration device comprises a substrate, a plurality of first grooves and a plurality of second grooves, wherein the surface of the substrate is provided with the first grooves, and the first grooves are used for arranging a plurality of chips to be integrated;
the integrated special-shaped adapter plate is positioned on the upper part of the substrate and used for realizing interconnection among the plurality of chips; and the number of the first and second groups,
the projection of each chip on the substrate is at least partially not coincident with the projection of the adapter plate on the substrate; and the projection of each chip and the projection of the adapter plate on the substrate are not overlapped, so that the chip and an external signal are interconnected.
Further, the package structure further comprises a substrate; the substrate comprises a base, a first dielectric layer and a second dielectric layer which are stacked from bottom to top; a second groove is formed in the first medium layer, and the packaging body is arranged in the second groove after being subjected to plastic packaging.
Furthermore, the adapter plate comprises a plurality of wires and salient points led out from two ends of the wires; wherein, the salient points led out from the two ends of the wiring respectively correspond to the two adjacent chips.
Each chip comprises a first bonding pad and a second bonding pad on the surface of the chip; the first bonding pad is positioned at a part where the chip and the projection of the adapter plate on the substrate are superposed and is used for being correspondingly connected with the salient point on the adapter plate; the second bonding pad is positioned at the part where the chip and the adapter plate project on the substrate and are not overlapped, so that the chip and an external signal are interconnected.
Furthermore, the upper surface of the second dielectric layer comprises a third bonding pad which is arranged corresponding to the second bonding pad, and the second bonding pad and the third bonding pad are connected through a metalized through hole; the substrate comprises a metalized through hole penetrating through the substrate, the first dielectric layer and the second dielectric layer, and the metalized through hole is used for connecting the third bonding pad and an external signal.
Further, the first pad and the second pad are located on the same plane.
Furthermore, the part of the chip, which is overlapped with the projection of the adapter plate on the substrate, is located at the edge position of the chip, and the interconnection between the chips is realized through the edge position.
On the other hand, the embodiment of the invention provides a packaging method for realizing integration of a plurality of chips, which comprises the steps of forming a packaging body; the forming of the package body includes:
forming a plurality of first grooves on the surface of the substrate;
placing the plurality of chips to be integrated in the first grooves respectively;
placing an integrated special-shaped adapter plate on the upper part of the substrate in a flip-chip mode, so that the projection of each chip on the substrate is at least partially not coincident with the projection of the adapter plate on the substrate;
interconnecting the plurality of chips through the interposer; and
and interconnecting the chips and external signals through the parts of the chips and the adapter plate, which are not overlapped in projection on the substrate.
Further, forming a first dielectric layer on the substrate;
forming a second groove on the surface of the first dielectric layer;
placing the encapsulated package body in the second groove;
and forming a second dielectric layer on the first dielectric layer and the packaging body.
Furthermore, the adapter plate comprises a plurality of wires and salient points led out from two ends of the wires; the salient points led out from the two ends of the wiring respectively correspond to the two adjacent chips; each chip comprises a first bonding pad and a second bonding pad which are positioned on the surface of the chip, the first bonding pad is positioned on the part of the chip, which is coincided with the projection of the adapter plate on the substrate, and the second bonding pad is positioned on the part of the chip, which is not coincided with the projection of the adapter plate on the substrate;
said interconnecting said plurality of chips comprises:
and correspondingly arranging the first bonding pad and the salient point, and interconnecting the chips through the first bonding pad, the salient point and the wiring.
Further, the interconnecting the chips and external signals through the parts of the chips and the interposer projected on the substrate without overlapping includes:
forming a metalized through hole which is arranged corresponding to the second bonding pad;
forming a third bonding pad corresponding to the second bonding pad on the upper surface of the second dielectric layer, and connecting the third bonding pad with the second bonding pad through a metalized through hole;
forming a metalized via hole penetrating through the substrate, the first dielectric layer and the second dielectric layer in the substrate, and connecting the metalized via hole with the third pad;
the chip is interconnected with an external signal through the second bonding pad, the metalized through hole, the third bonding pad and the metalized through hole.
Compared with the prior art, the invention can realize at least one of the following beneficial effects:
1. the adapter plate has an integrated special-shaped structure, the types, sizes and number of chips to be integrated are not limited, and a complete system with high integration among a plurality of chips can be formed; and the adapter plate is not provided with TSV, the manufacturing process is simple, and the cost is low.
2. The chips are respectively arranged in the first grooves on the surface of the substrate, so that on one hand, the first bonding pads and the second bonding pads of the chips can be accurately controlled to be positioned on the same horizontal plane, the difficulty of the process of the subsequent flip-chip of the adapter plate is reduced, and the reliability of the connection between the bumps and the first bonding pads or between the bumps and the second bonding pads is improved; on the other hand, the reliability of the package can be improved due to the fact that the Coefficient of Thermal Expansion (CTE) matching degree of the chip and the substrate is high.
3. The types of the convex points of the integrated special-shaped adapter plate are consistent, and the reliability problem caused by inconsistent stress deformation of the convex points can be solved in the process of inversely installing the adapter plate with the convex points of one type and the chip.
In the invention, the technical schemes can be combined with each other to realize more preferable combination schemes. Additional features and advantages of the invention will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. The objectives and other advantages of the invention will be realized and attained by the structure particularly pointed out in the written description and drawings.
Drawings
The drawings are only for purposes of illustrating particular embodiments and are not to be construed as limiting the invention, wherein like reference numerals are used to designate like parts throughout.
Fig. 1 is a top view of a package body;
FIG. 2 is a schematic structural diagram of an integrated special-shaped adapter plate;
FIG. 3 is a cross-sectional view of the package body of FIG. 1 taken along line B-B;
FIG. 4 is a cross-sectional view of a package structure;
FIGS. 5(a) -5(e) are schematic views illustrating the fabrication of the package structure
Reference numerals:
11. 12, 13, 14, 15-chips; 111. 121, 122, 131-first pad; 112. 132-a second pad; 2-a substrate; 21. 22, 23-first grooves; 3-an integrated special-shaped adapter plate; 31. 32, 33, 34, 35, 36-wiring; 311. 312, 321, 322, 331, 332, 341, 342, 351, 352, 361, 362-bumps; 41-a substrate; 42-a first dielectric layer; 43-a second dielectric layer; 421-a second groove; 51. 52-metallized vias; 61. 62-a third pad; 71. 72-a metallized via; 8-metal layer
Detailed Description
Hereinafter, embodiments of the present disclosure will be described with reference to the accompanying drawings. It should be understood that the description is illustrative only and is not intended to limit the scope of the present disclosure. Moreover, in the following description, descriptions of well-known structures and techniques are omitted so as to not unnecessarily obscure the concepts of the present disclosure.
Various structural schematics according to embodiments of the present disclosure are shown in the figures. The figures are not drawn to scale, wherein certain details are exaggerated and possibly omitted for clarity of presentation. The shapes of various regions, layers, and relative sizes and positional relationships therebetween shown in the drawings are merely exemplary, and deviations may occur in practice due to manufacturing tolerances or technical limitations, and a person skilled in the art may additionally design regions/layers having different shapes, sizes, relative positions, as actually required.
In the context of the present disclosure, when a layer/element is referred to as being "on" another layer/element, it can be directly on the other layer/element or intervening layers/elements may be present. In addition, if a layer/element is "on" another layer/element in one orientation, then that layer/element may be "under" the other layer/element when the orientation is reversed.
In one aspect of the invention, a package structure for realizing integration of a plurality of chips is disclosed, which comprises a package body; the packaging body comprises a substrate, wherein a plurality of first grooves are formed in the surface of the substrate and used for arranging a plurality of chips to be integrated; the integrated special-shaped adapter plate is positioned on the upper part of the substrate and used for realizing interconnection among a plurality of chips; and the projection of each chip on the substrate is at least partially not coincident with the projection of the adapter plate on the substrate; and the projection of each chip and the adapter plate on the substrate are not overlapped, so that the chip and an external signal are interconnected.
Compared with the prior art, the embodiment has the advantages that through the use of the integrated special-shaped adapter plate, the types, sizes and numbers of chips to be integrated are not limited, and a complete system with high integration among a plurality of chips can be formed; and the adapter plate is not provided with TSV, the manufacturing process is simple, and the cost is low.
Referring to fig. 1, fig. 1 is a top view of a package body. The integrated special-shaped interposer 3 is used to interconnect the chip 11, the chip 12, the chip 13, the chip 14, and the chip 15. The package body comprises a substrate 2, a surface of the substrate 2 is provided with 5 first grooves (3 of which are shown in fig. 5a, 3 first grooves 21, 22, 23), the 5 first grooves are used for arranging a chip 11, a chip 12, a chip 13, a chip 14 and a chip 15 to be integrated, wherein the chip 11 is arranged in the first groove 21, the chip 12 is arranged in the first groove 22, the chip 13 is arranged in the first groove 23, and the chip 14 and the chip 15 are also respectively arranged in the first grooves corresponding thereto. An integrated, profiled interposer 3 is placed on top of the substrate 2, the interposer 3 being used to interconnect the chip 11, the chip 12, the chip 13, the chip 14 and the chip 15. The projections of the chip 11, the chip 12, the chip 13, the chip 14 and the chip 15 on the substrate 2 are at least partially misaligned with the projections of the interposer 3 on the substrate, and the parts of the chip 11, the chip 12, the chip 13, the chip 14 and the chip 15 that are misaligned with the projections of the interposer 3 on the substrate 2 are used for realizing the interconnection of the respective chips and external signals, that is, the parts of the chip 11 that are misaligned with the projections of the interposer 3 on the substrate 2 are used for realizing the interconnection of the chip 11 and external signals; the chip 12 and the projection of the adapter plate 3 on the substrate 2 are not overlapped, so that the chip 12 and an external signal are interconnected; the chip 13 and the projection of the adapter plate 3 on the substrate 2 are not overlapped, so that the chip 13 and an external signal are interconnected; the chip 14 and the projection of the adapter plate 3 on the substrate 2 are not overlapped, so that the chip 14 and an external signal are interconnected; the portion of the chip 15 that does not coincide with the projection of the interposer 3 on the substrate 2 is used to interconnect the chip 15 with external signals.
In one embodiment, referring to fig. 2, fig. 2 is a schematic structural diagram of an integrated profiled adapter plate. The interposer 3 includes the wiring 31 and bumps 311 and 312 led out from both ends thereof, the wiring 32 and bumps 321 and 322 led out from both ends thereof, the wiring 33 and bumps 331 and 332 led out from both ends thereof, the wiring 34 and bumps 341 and 342 led out from both ends thereof, the wiring 35 and bumps 351 and 352 led out from both ends thereof, and the wiring 36 and bumps 361 and 362 led out from both ends thereof. Bumps 311 and 312 correspond to chips 11 and 12, bumps 321 and 322 correspond to chips 12 and 15, bumps 331 and 332 correspond to chips 12 and 13, bumps 341 and 342 correspond to chips 13 and 15, bumps 351 and 352 correspond to chips 14 and 15, and bumps 361 and 362 correspond to chips 14 and 11.
Fig. 3 is a cross-sectional view of the package body of fig. 1 along line B-B. Chip 11 includes first pads 111 and second pads 112 on its surface, chip 12 includes first pads 121, 122 and second pads (not shown) on its surface, chip 13 includes first pads 131 and second pads 132 on its surface, chip 14 includes first pads (not shown) and second pads (not shown) on its surface and chip 15 includes first pads (not shown) and second pads (not shown) on its surface. The first bonding pad 111 is located at a part where the chip 11 and the projection of the adapter plate 3 on the substrate 2 coincide, and is used for being connected with the bump 311; the second bonding pads 112 are located at the portion where the chip 11 and the interposer 3 are projectively misaligned on the substrate 2, so as to interconnect the chip 11 and an external signal. The first bonding pads 121, 122 are located at the part where the chip 12 and the projection of the interposer 3 on the substrate 2 coincide, the first bonding pad 121 is used for connecting with the bump 331, and the first bonding pad 122 is used for connecting with the bump 312; a second pad (not shown) of the chip 12 interconnects the chip 12 with an external signal. The first bonding pad 131 is located at a part where the chip 13 and the projection of the adapter plate 3 on the substrate 2 coincide, and is used for being connected with the bump 332; the second bonding pads 132 are located at the portion where the chip 13 and the interposer 3 are not overlapped in projection on the substrate 2, so as to interconnect the chip 13 and an external signal. That is, the chip 11 and the chip 12 are interconnected through the first pad 111, the bump 311, the wiring 31, the bump 312 and the first pad 122; the chip 12 and the chip 13 are interconnected through the first pad 121, the bump 331, the wiring 33, the bump 332, and the first pad 131. For the interconnection between the chips 13 and 15, the chips 15 and 14, the chips 15 and 12, the chips 14 and 11, and the interconnection between the chips 14 and 15 and the external signals, please refer to the above-mentioned manner of the chips 11, 12, and 13, which is not described herein again.
Referring to fig. 4, fig. 4 is a cross-sectional view of a package structure. The package structure further includes a substrate, and the substrate includes a substrate 41, a first dielectric layer 42, and a second dielectric layer 43 stacked from bottom to top. A second groove 421 (shown in fig. 5 (d)) is opened in the first dielectric layer 42, and the molded package body is disposed in the second groove 421. The upper surface of the second dielectric layer includes third pads 61, 62 disposed corresponding to the second pads 112, 132. The second pad 112 is connected to the third pad 61 through a metallized via 51, and the second pad 132 is connected to the third pad 62 through a metallized via 52. The substrate includes a metalized via that penetrates through the substrate 41, the first dielectric layer 42, and the second dielectric layer 43 and corresponds to each chip, the metalized via being disposed at a position offset from the second recess. Fig. 4 exemplarily shows the metalized vias 71 and 72 corresponding to the chip 11 and the chip 13, the third pad 61 is interconnected with the external signal through the metalized via 71, the third pad 62 is interconnected with the external signal through the metalized via 72, that is, the chip 11 is interconnected with the external signal through the second pad 112, the metalized via 51, the third pad 61 and the metalized via 71, and the chip 13 is interconnected with the external signal through the third pad 132, the metalized via 52, the third pad 62 and the metalized via 72. For the interconnection of the chips 12, 14, and 15 and the external signal, please refer to the interconnection manner of the chips 11 and 13 and the external signal, which is not described herein again.
In one embodiment, a good conductor material, such as copper, is disposed in each of the metalized vias or metalized vias to provide an electrical connection. This is not described in detail in the following.
In an embodiment, the depth of the second groove is determined according to the thickness of the package body after molding. Optionally, the depth of the second groove is greater than or equal to the thickness of the package body.
In one embodiment, the types of the bumps on the adapter plate 3 are consistent, so that the problems of uneven bump deformation and other reliability caused by inconsistent types of the bumps on the adapter plate during the flip-chip process are solved, and the process difficulty in manufacturing the adapter plate is reduced. Optionally, the bump is of a CuPillar + Solderball structure.
In one embodiment, with continued reference to fig. 4, a plurality of chips are disposed in a plurality of first grooves of the substrate 2, the size and depth of the first grooves are determined according to the actual size and thickness of the chips, and the second pads 112, the first pads 111, the first pads 122, the first pads 121, the first pads 131, and the second pads 132 are precisely controlled to be located on the same plane, so that the first pads and the second pads located on the surfaces of the chips 11, 12, 13, 14, and 15 are all located on the same plane. By the design, on one hand, the difficulty of the process of the adapter plate during the flip-chip process is reduced, and the reliability of the connection between the salient point and the first bonding pad or between the salient point and the second bonding pad is improved; on the other hand, the reliability of the packaging structure can be improved due to the fact that the Coefficient of Thermal Expansion (CTE) of the chip is matched with that of the substrate. Optionally, the depth of the first groove is greater than or equal to the thickness of the chip placed correspondingly.
Alternatively, the substrate may be a silicon substrate.
In an embodiment, with continued reference to fig. 4, the package structure includes a metal layer 8, and the metal layer 8 is located between the substrate 41 and the first dielectric layer 42 and is disposed corresponding to the second recess 421. Due to the existence of the metal layer 8, on one hand, when the second groove 421 is manufactured, the flatness of the bottom of the second groove is kept, and a relatively flat setting environment is provided for embedding the encapsulated package body; on the other hand, when the chip is in work, the metal layer has a better heat dissipation function, and heat generated by the chip can be better dissipated through the packaging body and the metal layer. Optionally, a projected area of the metal layer 8 on the substrate 41 is larger than a projected area of the package body after the plastic package on the substrate 41.
In one embodiment, the size and spacing of the second pads is greater than the size and spacing of the first pads. Further, the line width and the line pitch (L/S) of the wiring on the interposer are in the micron level or the submicron level.
In one embodiment, the part of the chip coinciding with the projection of the interposer onto the substrate is located at an edge position of the chip, and the chip-to-chip interconnection is realized through the edge position.
In one embodiment, the line width and line spacing (L/S) of the wiring on the adapter board is less than or equal to 2 microns, the diameter of the salient points on the adapter board is less than or equal to 40 microns, and the center distance of the salient points is less than or equal to 60 microns, so that high-density interconnection between chips is realized.
In one embodiment, the external signal is a power signal.
In one embodiment, the shape of the integrated shaped interposer is related to the layout pattern and location of the plurality of chips to be integrated. The shape of the integrated special-shaped adapter plate can be specifically designed according to actual requirements.
Optionally, the plurality of chips are a Central Processing Unit (CPU) chip, a north bridge chip, a south bridge chip, a memory chip, a radio frequency chip, and the like in the system with the inherent mode, and the interposer may be designed and manufactured accordingly according to the corresponding position relationship between the chips. Further, in practical application, in order to meet the interconnection among a plurality of chips in the fixed mode, the corresponding integrated special-shaped adapter plate can be produced in batch, and the requirement of chip interconnection in the fixed mode is met.
In another aspect of the invention, a packaging method for realizing integration of a plurality of chips is disclosed, which comprises forming a packaging body; the forming of the packaging body comprises the steps of forming a plurality of first grooves on the surface of the substrate; placing a plurality of chips to be integrated in the first grooves respectively; placing an integrated special-shaped adapter plate on the upper part of a substrate in a flip-chip mode, so that the projection of each chip on the substrate is at least partially not coincident with the projection of the adapter plate on the substrate; interconnecting a plurality of chips through a patch panel; and interconnecting the chips with external signals through the parts of the chips and the adapter plate, which are not overlapped in projection on the substrate.
In a specific embodiment, specific steps in the packaging process are described with reference to fig. 3, fig. 4, and fig. 5(a) to 5 (e).
Referring to fig. 5(a), a substrate 2 is provided, and 5 first grooves (only 3 first grooves 21, 22, 23 are shown in fig. 5 a) are opened on the surface of the substrate 2. The size and the depth of each first groove are set according to the size and the thickness of the corresponding chip, and the depth of each first groove is larger than or equal to the thickness of the corresponding chip. The process of forming the first recess may depend on the specific material of the substrate 2.
Referring to fig. 5(b), a plurality of chips to be integrated are respectively placed in the first grooves, the chip 11 is placed in the first groove 21, the chip 12 is placed in the first groove 22, the chip 13 is placed in the first groove 23, and the chip 14 and the chip 15 are also placed in the corresponding first grooves (not shown). Optionally, the first bonding pad and the second bonding pad of each chip are controlled to be located on the same plane. Optionally, the first pads are small-sized narrow-pitch pads and the second pads are large-sized wide-pitch pads.
Referring to fig. 3 and 5(c), the integrated shaped interposer 3 is flip-chip mounted on the substrate 2. The first pad 111 is disposed corresponding to the bump 311, the first pad 122 is disposed corresponding to the bump 312, the first pad 121 is disposed corresponding to the bump 331, and the first pad 131 is disposed corresponding to the bump 332. That is, the chip 11 and the chip 12 are interconnected through the first pad 111, the bump 311, the wiring 31, the bump 312 and the first pad 122, and the chip 11 is interconnected with an external signal through the second pad 112; the chip 13 and the chip 12 are interconnected through the first pad 131, the bump 332, the wiring 33, the bump 331 and the first pad 121, and the chip 13 is interconnected with an external signal through the second pad 132. The interconnection mode between other chips and the interconnection mode with external signals refer to the interconnection mode of the chip 11 and the chip 13, which is not described in detail herein.
Referring to fig. 5(c), the package body is subjected to plastic packaging, a molding process is adopted, the package body is subjected to plastic packaging through a molding material, and metallized first sub-through holes are formed in positions, corresponding to the second pads 112 and 132, in the plastic packaging material.
Referring to fig. 5(d), providing a substrate 41, and fabricating a first metallized sub-via and a patterned metal layer 8, where the patterned metal layer 8 may be formed by sputtering, photolithography, etching, and the like; forming a first dielectric layer 42 on the substrate 41 and the patterned metal layer 8, forming a second metallized sub-via hole and a second groove 421 in the second dielectric layer 42, wherein the second groove 421 corresponds to the metal layer 8; optionally, a projected area of the metal layer 8 on the substrate 41 is larger than a projected area of the second groove 421 on the substrate 41. The material of the first dielectric layer 42 may be selected from abf (ajinomoto buildupp layer), Core (Core) material, pp (prepreg) material, and photosensitive material, and the specific grooving process is determined according to the selected material. This step may be performed at the same time as or after the manufacture of the package body.
Referring to fig. 5(e), the molded package body is placed in the second groove 421. Preferably, the molded package body is located on the metal layer 8, and a projection of the molded package body on the substrate 41 coincides with a projection of the metal layer 8 on the substrate 41, that is, the projection of the molded package body on the substrate 41 is located in the projection of the metal layer 8 on the substrate 41.
Referring to fig. 4, on the basis of the structure in fig. 5(e), a second dielectric layer 43 is formed on the first dielectric layer 42 and the encapsulated package body.
A metallized third sub-via hole corresponding to the metallized first sub-via hole and the metallized second sub-via hole is formed in the second dielectric layer 43, wherein the metallized first sub-via hole, the metallized second sub-via hole and the metallized third sub-via hole form metallized via holes 71 and 72 penetrating through the substrate 41, the first dielectric layer 42 and the second dielectric layer 43, and the substrate further includes metallized via holes corresponding to other chips to be integrated, which is not described in detail herein.
A metallized second sub-via corresponding to the metallized first sub-via is formed in the second dielectric layer 43, wherein the metallized first sub-via and the metallized second sub-via form metallized vias 51 and 52, and the substrate further includes metallized vias corresponding to other chips to be integrated, which is not described in detail herein.
Forming third bonding pads on the upper surface of the second dielectric layer 43, and forming third bonding pads 61 and 62 on the upper surface of the second dielectric layer 43 by taking the chips 11 and 13 as an example; the second pad 112 is connected to the third pad 61 by a metallized via 51; the second pad 132 is connected to the third pad 62 by the metalized via 52. The surface of the second medium layer is also provided with third bonding pads corresponding to other chips to be integrated, and the third bonding pads are connected with the second bonding pads of the respective chips through the metalized through holes corresponding to the respective chips, so that the connection between the respective corresponding chips and external signals is realized, and the description is omitted.
With continued reference to fig. 4, the chip 11 and the chip 12 are interconnected through the first pad 111, the bump 311, the wiring 31, the bump 312 and the first pad 122, and the chip 11 is interconnected with an external signal through the second pad 112, the metalized via 51, the third pad 61 and the metalized via 71. The chip 13 and the chip 12 are interconnected through the first pad 131, the bump 332, the wiring 33, the bump 331 and the first pad 121, and the chip 13 is interconnected with an external signal through the second pad 132, the metalized through hole 52, the third pad 62 and the metalized through hole 72. For the interconnection manner between other chips to be integrated and the interconnection manner with external signals, please refer to the interconnection manner between the chips 11 and 13 and the chip 12 and the interconnection manner between the chips 11 and 13 and external signals, which will not be described herein.
The above description is only for the preferred embodiment of the present invention, but the scope of the present invention is not limited thereto, and any changes or substitutions that can be easily conceived by those skilled in the art within the technical scope of the present invention are included in the scope of the present invention.
Claims (8)
1. A packaging structure for realizing integration of a plurality of chips is characterized by comprising a packaging body; the package body includes:
the chip integration device comprises a substrate, a plurality of first grooves and a plurality of second grooves, wherein the surface of the substrate is provided with the first grooves, and the first grooves are used for arranging a plurality of chips to be integrated;
the integrated special-shaped adapter plate is positioned on the upper part of the substrate and used for realizing interconnection among the plurality of chips; and the number of the first and second groups,
the projection of each chip on the substrate is at least partially not coincident with the projection of the adapter plate on the substrate; the projection of each chip and the projection of the adapter plate on the substrate are not overlapped, so that the chip and an external signal are interconnected;
the packaging structure further comprises a substrate; the substrate comprises a base, a first dielectric layer and a second dielectric layer which are stacked from bottom to top; the upper surface of the second dielectric layer comprises a third bonding pad which is arranged corresponding to the second bonding pad, and the second bonding pad and the third bonding pad are connected through a metalized through hole; the substrate comprises a metalized through hole penetrating through the substrate, the first dielectric layer and the second dielectric layer, and the metalized through hole is used for connecting the third bonding pad and an external signal.
2. The package structure of claim 1, wherein a second groove is formed in the first dielectric layer, and the package body is disposed in the second groove after being molded.
3. The package structure according to claim 2, wherein the interposer includes a plurality of wires and bumps led out from both ends of the wires; wherein, the salient points led out from the two ends of the wiring respectively correspond to the two adjacent chips;
each chip comprises a first bonding pad and a second bonding pad on the surface of the chip; the first bonding pad is positioned at a part where the chip and the projection of the adapter plate on the substrate are superposed and is used for being correspondingly connected with the salient point on the adapter plate; the second bonding pad is positioned at the part where the chip and the adapter plate project on the substrate and are not overlapped, so that the chip and an external signal are interconnected.
4. The package structure of claim 3, wherein the first pad and the second pad are located on a same plane.
5. The package structure according to claim 3, wherein a portion of the chip coinciding with a projection of the interposer onto the substrate is located at an edge position of the chip, through which the interconnection between the chips is achieved.
6. A packaging method for realizing integration of a plurality of chips is characterized by comprising the steps of forming a packaging body; the forming of the package body includes:
forming a plurality of first grooves on the surface of the substrate;
placing the plurality of chips to be integrated in the first grooves respectively;
placing an integrated special-shaped adapter plate on the upper part of the substrate in a flip-chip mode, so that the projection of each chip on the substrate is at least partially not coincident with the projection of the adapter plate on the substrate;
interconnecting the plurality of chips through the interposer; and
interconnecting the chips with external signals through the parts of the chips and the adapter plate which are not overlapped in projection on the substrate, comprising:
forming a metalized through hole which is arranged corresponding to the second bonding pad;
forming a third bonding pad corresponding to the second bonding pad on the upper surface of the second dielectric layer, and connecting the third bonding pad with the second bonding pad through a metalized through hole;
forming a metalized via hole penetrating through a substrate, the first dielectric layer and the second dielectric layer in the substrate, and connecting the metalized via hole with the third bonding pad;
the chip is interconnected with an external signal through the second bonding pad, the metalized through hole, the third bonding pad and the metalized through hole.
7. The method of packaging of claim 6, further comprising:
forming a first dielectric layer on a substrate;
forming a second groove on the surface of the first dielectric layer;
placing the encapsulated package body in the second groove;
and forming a second dielectric layer on the first dielectric layer and the packaging body.
8. The method of claim 7, wherein the interposer includes a plurality of wires and bumps extending from opposite ends of the wires; the salient points led out from the two ends of the wiring respectively correspond to the two adjacent chips; each chip comprises a first bonding pad and a second bonding pad which are positioned on the surface of the chip, the first bonding pad is positioned on the part of the chip, which is coincided with the projection of the adapter plate on the substrate, and the second bonding pad is positioned on the part of the chip, which is not coincided with the projection of the adapter plate on the substrate;
said interconnecting said plurality of chips comprises:
and correspondingly arranging the first bonding pad and the salient point, and interconnecting the chips through the first bonding pad, the salient point and the wiring.
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| US9385110B2 (en) * | 2014-06-18 | 2016-07-05 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor device and method |
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| CN107393900B (en) * | 2017-08-08 | 2019-07-26 | 中国电子科技集团公司第五十八研究所 | The embedded type TSV adapter plate structure of pole multilayer wiring |
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