CN107393900B - The embedded type TSV adapter plate structure of pole multilayer wiring - Google Patents

The embedded type TSV adapter plate structure of pole multilayer wiring Download PDF

Info

Publication number
CN107393900B
CN107393900B CN201710668543.4A CN201710668543A CN107393900B CN 107393900 B CN107393900 B CN 107393900B CN 201710668543 A CN201710668543 A CN 201710668543A CN 107393900 B CN107393900 B CN 107393900B
Authority
CN
China
Prior art keywords
wiring
pinboard
plate body
switching
switching plate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
CN201710668543.4A
Other languages
Chinese (zh)
Other versions
CN107393900A (en
Inventor
明雪飞
朱家昌
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
CETC 58 Research Institute
Original Assignee
CETC 58 Research Institute
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by CETC 58 Research Institute filed Critical CETC 58 Research Institute
Priority to CN201710668543.4A priority Critical patent/CN107393900B/en
Publication of CN107393900A publication Critical patent/CN107393900A/en
Application granted granted Critical
Publication of CN107393900B publication Critical patent/CN107393900B/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49861Lead-frames fixed on or encapsulated in insulating substrates
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814Conductive parts
    • H01L21/4821Flat leads, e.g. lead frames with or without insulating supports
    • H01L21/4839Assembly of a flat lead with an insulating support, e.g. for TAB
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814Conductive parts
    • H01L21/4846Leads on or in insulating or insulated substrates, e.g. metallisation
    • H01L21/486Via connections through the substrate with or without pins
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49827Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04105Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/19Manufacturing methods of high density interconnect preforms
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32151Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73251Location after the connecting process on different surfaces
    • H01L2224/73267Layer and HDI connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92Specific sequence of method steps
    • H01L2224/922Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
    • H01L2224/9222Sequential connecting processes
    • H01L2224/92242Sequential connecting processes the first connecting process involving a layer connector
    • H01L2224/92244Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a build-up interconnect
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/1515Shape
    • H01L2924/15153Shape the die mounting substrate comprising a recess for hosting the device
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/156Material
    • H01L2924/157Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/156Material
    • H01L2924/15786Material with a principal constituent of the material being a non metallic, non metalloid inorganic material
    • H01L2924/15788Glasses, e.g. amorphous oxides, nitrides or fluorides

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)

Abstract

The present invention relates to a kind of adapter plate structure, the embedded type TSV adapter plate structure of especially a kind of pole multilayer wiring belongs to the technical field of integrated antenna package.According to technical solution provided by the invention, the embedded type TSV adapter plate structure of the pole multilayer wiring, including switching plate body;Wiring switching board slot is recessed in the pinboard body, the setting wiring pinboard in wiring switching board slot, pole multilayer wiring is provided on the wiring pinboard, wiring pinboard by pole multilayer wiring with switching plate body upper surface pinboard on again wiring layer be electrically connected, on the pinboard again wiring layer by be filled in the filling connector of through-hole in pinboard body with wiring layer is electrically connected again under the pinboard of switching plate body lower surface, under the pinboard again wiring layer be equipped with several soldered balls, the soldered ball with wiring layer is electrically connected again under pinboard.The present invention can effectively increase the wiring number of plies, realize highdensity wafer-level package and system encapsulation, securely and reliably.

Description

The embedded type TSV adapter plate structure of pole multilayer wiring
Technical field
The present invention relates to a kind of adapter plate structure, the embedded type TSV adapter plate structure of especially a kind of pole multilayer wiring belongs to In the technical field of integrated antenna package.
Background technique
As electronic product develops to the directions such as miniaturization, high-performance, highly reliable, level of integrated system is also increasingly improved.? In this case, the characteristic size and the line width of interconnection line by further reducing integrated circuit propose high performance mode by material Expect the limitation of physical characteristic and apparatus and process, traditional Moore's Law has been difficult to continue to develop.
TSV (ThroughSiliconVia, through silicon via) technology can carry out chip and chip, chip and substrate perpendicular interconnection, Information transmission path is effectively shortened, and can realize more multi-functional, higher power, more exits with package area.TSV skill Art is to break through the effective way of Moore's Law, it is considered to be the dominant technology of Future high-density encapsulation field.Currently, TSV technology Mainly apply it first is that preparation TSV interposer substrate, encapsulates for chip-scale encapsulation and system.
TSV pinboard is the essential elements for realizing high-density packages, and multiple chips can be made to be directly realized by interconnection.With partly leading The promotion of body chip performance, the interconnection density between chip also constantly increase, force and be routed (RDL) layer again on TSV pinboard Number is continuously increased.But conventional RD L technology of preparing is limited by technological level, prepares multilayer (4 layers or more) wiring layer again It is difficult, it has been unable to satisfy the growth requirement of the high interconnection density of TSV pinboard.So high in order to meet current microelectronics system The growth requirement of performance, high interconnection density needs the novel TSV adapter plate structure for developing a kind of pole multilayer wiring.
Summary of the invention
The purpose of the present invention is overcoming the deficiencies in the prior art, a kind of embedded type TSV of pole multilayer wiring is provided Adapter plate structure, it is compact-sized, the wiring number of plies can be effectively increased, realizes highdensity wafer-level package and system encapsulation, Securely and reliably.
According to technical solution provided by the invention, a kind of preparation method of the embedded type TSV pinboard of pole multilayer wiring, packet Include switching plate body;Wiring switching board slot is recessed in the pinboard body, setting wiring turns in wiring switching board slot Fishplate bar, is provided with pole multilayer wiring on the wiring pinboard, and wiring pinboard passes through on pole multilayer wiring and switching plate body Wiring layer is electrically connected again on the pinboard on surface, on the pinboard again wiring layer by being filled in filling out for through-hole in pinboard body Fill connector with transfer plate body lower surface pinboard under again wiring layer be electrically connected, if under the pinboard again wiring layer equipped with Dry soldered ball, the soldered ball with wiring layer is electrically connected again under pinboard;
The wiring pinboard is adhesively fixed by pinboard cohesive body in wiring switching board slot;
The material of the switching plate body includes silicon or glass.
Advantages of the present invention: the wiring pinboard 3 with pole multilayer wiring 4 is embedded in switching plate body 1, to can increase The wiring number of plies of switching plate body makes up the deficiency that TSV switching plate body is limited by the RDL wiring number of plies, can meet high-performance, Gao Ji The application demand encapsulated at the micro-system of density;By in the prefabricated TSV interposer substrate with through-hole and wiring switching board slot The TSV switching plate body for meeting performance requirement of upper interception certain size, can be improved encapsulation yield, compact-sized, securely and reliably.
Detailed description of the invention
Fig. 1 is the schematic diagram that switching plate body is prepared using interposer substrate by the present invention.
Fig. 2 is that present invention wiring interposer substrate obtains the schematic diagram of wiring pinboard.
Fig. 3 is that the pinboard of the invention that will be routed is placed in the intracorporal schematic diagram of pinboard.
Fig. 4 is that the present invention prepares on pinboard under wiring layer, pinboard again the signal after wiring layer again on switching plate body Figure.
Fig. 5 is that the schematic diagram after soldered ball is prepared in the present invention.
Description of symbols: 1- switching plate body, 2- through-hole, 3- wiring pinboard, the pole 4- multilayer wiring, 5- pinboard bonding Wiring layer, 7- soldered ball, 8- filling connector, wiring layer, 10- interposer substrate, 11- again under 9- pinboard again on body, 6- pinboard Wiring switching board slot and 12- are routed interposer substrate.
Specific embodiment
Below with reference to specific drawings and examples, the invention will be further described.
It is as shown in Figure 5: in order to effectively increase the wiring number of plies, realize highdensity wafer-level package and system encapsulation, The present invention includes switching plate body 1;Wiring switching board slot 11 is recessed in the switching plate body 1, in wiring switching board slot Setting wiring pinboard 3 in 11, is provided with pole multilayer wiring 4 on the wiring pinboard 3, and wiring pinboard 3 passes through extremely more Layer wiring 4 with switching 1 upper surface of plate body pinboard on again wiring layer 6 be electrically connected, on the pinboard again wiring layer 6 pass through fill out Fill switching 1 inner via hole 2 of plate body filling connector 8 with transfer 1 lower surface of plate body pinboard under again wiring layer 9 be electrically connected, Under the pinboard again wiring layer 9 be equipped with several soldered balls 7, the soldered ball 7 with wiring layer 9 is electrically connected again under pinboard.
Specifically, the depth of wiring switching board slot 11 is less than the thickness of switching plate body 1, and through-hole 2 penetrates through specially switching plate body 1, Through-hole 2 is located at the outer ring of wiring switching board slot 11, and wiring pinboard 3 is embedded in switching plate body 1 by wiring switching board slot 11, The thickness for being routed pinboard 3 is less than the depth of wiring switching board slot 11, when pole multilayer wiring 4 is set on wiring pinboard 3, It is consistent with the wiring switching depth of board slot 11 to be routed the sum of pinboard 3 and the thickness of pole multilayer wiring 4, thus in switching plate body After preparing on pinboard wiring layer 6 again on 1, wiring pinboard 3 can be with 6 electricity of wiring layer again on pinboard by pole multilayer wiring 4 Connection.
The wiring pinboard 3 is adhesively fixed by pinboard cohesive body 5 in wiring switching board slot 11, and pinboard bonds Body 5 can use existing common binding material, and wiring pinboard 3 is fixed in wiring switching board slot 11 as long as being able to achieve, Reach and is fixedly connected with switching plate body 1.After connector 8 is filled in through-hole 2, turned by filling connector 8 and being able to achieve Under fishplate bar again wiring layer 9 with wiring layer 6 is electrically connected again on pinboard, pass through soldered ball 7 and realize drawing plate body 1 signal of transferring Out.
As shown in fig. 1~fig. 5, the TSV adapter plate structure of above structure can be prepared by following concrete technologies, tool Body step are as follows:
Step 1 provides interposer substrate 10, and the material of the interposer substrate 10 includes but is not limited to the materials such as silicon, glass, The switching plate body 1 of pitch needed for being made in interposer substrate 10 of routine TSV technique, depth-to-width ratio;The through-hole of the switching plate body 1 2 perforation interposer substrates 10.
After obtaining required switching plate body 1 in interposer substrate 10, using conventional etching technics in each switching plate body 1 The switching board slot 11 of wiring needed for upper preparation, as shown in Figure 1;In figure, obtain several being in array distribution in interposer substrate 10 Transfer plate body 1, the size of wiring switching board slot 11 according to specific it needs to be determined that, the depth of wiring switching board slot 11 is no more than turn The thickness of fishplate bar body 1.After obtaining wiring switching board slot 11 in each switching plate body 1, intercepted by conventional scribing process To independent switching plate body 1.
Step 2 is provided wiring interposer substrate 12, and is made in wiring interposer substrate 12 using conventional wafer grade CMOS technology Make pole multilayer wiring 4, the wiring number of plies and wiring rule of pole multilayer wiring 4 can be determined according to signal interconnection design requirement, The wiring pinboard 3 with pole multilayer wiring 4 is obtained by conventional scribing process;Wiring pinboard 3 is shown in Fig. 2 to be routed It is in the schematic diagram of array distribution in interposer substrate 12.
Step 3 transfers the embedment of the wiring pinboard 3 with pole multilayer wiring 4 in plate body 1, and wiring pinboard 3 is by turning Fishplate bar cohesive body 5 is adhesively fixed with switching plate body 1, and the material of pinboard cohesive body 5 includes but is not limited to adhesive glue, alloy sheet etc. Common binding material, as shown in Figure 3.In Fig. 3, filling connection can be obtained in the through-hole 2 for plate body 1 of transferring by fill process Body 8, filling connector 8 fill up through-hole 2, and filling connector 8, tool can be specifically obtained using the common technique of the art Details are not described herein again for body technology process.
Step 4 passes through photoetching but is not desired to be satisfied with the technique of photoetching, manufactures in upper surface, the lower surface of above-mentioned switching plate body 1 Wiring layer (RDL) is again to get to wiring layer 9 again under wiring layer 6 and pinboard again on pinboard, wiring layer 6 again on pinboard By filling connector 8 with wiring layer 9 is electrically connected again under pinboard, wiring layer 6 is covered on pole multilayer wiring 4 again on pinboard On, and be electrically connected with pole multilayer wiring 4, as shown in Figure 4.
Step 5 plants the array soldered ball 7 that switching partitioned signal extraction is realized in the production of ball technique using standard.The big rootlet of soldered ball 7 Depending on the diameter and pitch of TSV pinboard surface pads.The material of soldered ball 7 includes but is not limited to tin-lead, Xi Yin and tin silver The materials such as copper, as shown in Figure 5.It is embedded in switching plate body 1 by the wiring pinboard 3 with pole multilayer wiring 4, increases and turn The wiring number of plies of fishplate bar body 1, to realize that the encapsulation of the higher microelectronics system of routing complexity is integrated.

Claims (1)

1. a kind of preparation method of the embedded type TSV pinboard of pole multilayer wiring, including switching plate body (1);It is characterized in that: institute It states and is recessed with wiring switching board slot (11) in switching plate body (1), the setting wiring pinboard in wiring switching board slot (11) (3), be provided with pole multilayer wiring (4) on the wiring pinboard (3), wiring pinboard (3) by pole multilayer wiring (4) with Wiring layer (6) is electrically connected again on the pinboard of switching plate body (1) upper surface, and wiring layer (6) passes through filling again on the pinboard Wiring layer (9) again under the filling connector (8) of switching plate body (1) inner via hole (2) and the pinboard of switching plate body (1) lower surface Electrical connection, wiring layer (9) is equipped with several soldered balls (7) again under the pinboard, wiring layer again under the soldered ball (7) and pinboard (9) it is electrically connected;
The wiring pinboard (3) is adhesively fixed by pinboard cohesive body (5) in wiring switching board slot (11);
The material of switching plate body (1) includes silicon or glass;
The TSV adapter plate structure is prepared by following concrete technologies, specific steps are as follows:
Step 1 provides interposer substrate (10), pitch, depth-to-width ratio needed for being made on interposer substrate (10) of routine TSV technique Switching plate body (1);The through-hole (2) of switching plate body (1) penetrates through interposer substrate (10);
After obtaining required switching plate body (1) on interposer substrate (10), using conventional etching technics in each switching plate body (1) required wiring switching board slot (11) is prepared on, and several switching plate bodys in array distribution are obtained on interposer substrate (10) (1), the size of wiring switching board slot (11) according to specific it needs to be determined that, the depth of wiring switching board slot (11), which is no more than, transfers The thickness of plate body (1);After obtaining wiring switching board slot (11) in each switching plate body (1), cut by conventional scribing process Obtain independent switching plate body (1);
Step 2 is provided wiring interposer substrate (12), and is made in wiring interposer substrate (12) using conventional wafer grade CMOS technology To make pole multilayer wiring (4), the wiring number of plies and wiring rule of pole multilayer wiring (4) are determined according to signal interconnection design requirement, The wiring pinboard (3) with pole multilayer wiring (4) is obtained by conventional scribing process;
Step 3 will have in wiring pinboard (3) embedment switching plate body (1) of pole multilayer wiring (4), and wiring pinboard (3) is logical It crosses pinboard cohesive body (5) to be adhesively fixed with switching plate body (1), be obtained in the through-hole (2) of switching plate body (1) by fill process It fills connector (8), through-hole (2) is filled up in filling connector (8);
Step 4, the upper surface of above-mentioned switching plate body (1), lower surface manufacture again wiring layer (RDL) to get on pinboard again Wiring layer (9) again under wiring layer (6) and pinboard, wiring layer (6) passes through filling connector (8) and pinboard again on pinboard Under again wiring layer (9) be electrically connected, wiring layer (6) is covered on pole multilayer wiring (4) again on pinboard, and with pole multilayer wiring (4) it is electrically connected;
Step 5 plants the array soldered ball (7) that switching partitioned signal extraction is realized in the production of ball technique, the big rootlet of soldered ball (7) using standard Depending on the diameter and pitch of TSV pinboard surface pads.
CN201710668543.4A 2017-08-08 2017-08-08 The embedded type TSV adapter plate structure of pole multilayer wiring Active CN107393900B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN201710668543.4A CN107393900B (en) 2017-08-08 2017-08-08 The embedded type TSV adapter plate structure of pole multilayer wiring

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN201710668543.4A CN107393900B (en) 2017-08-08 2017-08-08 The embedded type TSV adapter plate structure of pole multilayer wiring

Publications (2)

Publication Number Publication Date
CN107393900A CN107393900A (en) 2017-11-24
CN107393900B true CN107393900B (en) 2019-07-26

Family

ID=60354434

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201710668543.4A Active CN107393900B (en) 2017-08-08 2017-08-08 The embedded type TSV adapter plate structure of pole multilayer wiring

Country Status (1)

Country Link
CN (1) CN107393900B (en)

Families Citing this family (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN108598062A (en) * 2018-05-10 2018-09-28 中国电子科技集团公司第五十八研究所 A kind of novel three-dimensional integrated encapsulation structure
US11264332B2 (en) 2018-11-28 2022-03-01 Micron Technology, Inc. Interposers for microelectronic devices
CN109686722A (en) * 2018-11-30 2019-04-26 中国电子科技集团公司第五十八研究所 A kind of high density interconnection package structure based on bridging chip
US11069622B2 (en) * 2019-03-22 2021-07-20 At&S Austria Technologie & Systemtechnik Aktiengesellschaft Interposer-type component carrier and method of manufacturing the same
CN110634848A (en) * 2019-08-29 2019-12-31 上海先方半导体有限公司 Multi-chip stacking packaging structure and manufacturing method thereof
CN111128948B (en) * 2019-12-30 2022-05-17 上海先方半导体有限公司 Structure for realizing coplanarity of embedded adapter plate and substrate and manufacturing method thereof
CN111128949B (en) * 2019-12-30 2021-08-24 上海先方半导体有限公司 Embedded adapter plate and manufacturing method of packaging structure thereof
CN111312697B (en) * 2020-02-28 2022-02-22 西安微电子技术研究所 Three-dimensional stacking integrated structure, multi-chip integrated structure and preparation method thereof
CN111785646B (en) * 2020-02-28 2022-11-11 浙江集迈科微电子有限公司 Ultra-thin welding stack packaging mode
CN111769098B (en) * 2020-07-09 2022-04-08 中国科学院微电子研究所 Packaging structure and packaging method for realizing integration of multiple chips
CN112992851B (en) * 2021-04-20 2021-11-23 浙江集迈科微电子有限公司 Adapter plate and preparation method thereof
CN113257786B (en) * 2021-06-17 2021-11-02 浙江集迈科微电子有限公司 Multilayer wiring adapter plate for radio frequency transmission and preparation method thereof
CN113471161A (en) * 2021-06-28 2021-10-01 浙江集迈科微电子有限公司 Multilayer wiring adapter plate for radio frequency transmission and preparation method thereof
CN113567838A (en) * 2021-07-27 2021-10-29 中国电子科技集团公司第五十八研究所 Circuit test structure based on adapter plate and preparation method thereof

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI492680B (en) * 2011-08-05 2015-07-11 Unimicron Technology Corp Package substrate having embedded interposer and fabrication method thereof
US9852998B2 (en) * 2014-05-30 2017-12-26 Taiwan Semiconductor Manufacturing Company, Ltd. Ring structures in device die
US10074630B2 (en) * 2015-04-14 2018-09-11 Amkor Technology, Inc. Semiconductor package with high routing density patch

Also Published As

Publication number Publication date
CN107393900A (en) 2017-11-24

Similar Documents

Publication Publication Date Title
CN107393900B (en) The embedded type TSV adapter plate structure of pole multilayer wiring
TWI734455B (en) Multi-chip package and manufacture method thereof
KR101692120B1 (en) Semiconductor package including an embedded surface mount device and method of forming the same
CN105374693B (en) Semiconductor package part and forming method thereof
CN103208482B (en) Through-hole component module and forming method thereof
CN103579022B (en) Structure and manufacturing method of semiconductor package
US7446424B2 (en) Interconnect structure for semiconductor package
CN113257778B (en) 3D stacked fan-out type packaging structure with back lead-out function and manufacturing method thereof
CN101252121A (en) Stack package and method of manufacturing the same
CN108389823A (en) For multi-chip wafer scale fan-out-type 3 D stereo encapsulating structure and its packaging technology
CN102420180A (en) Semiconductor device and manufacturing method thereof
CN102543927A (en) Packaging substrate with embedded through-hole interposer and manufacturing method thereof
CN104505382A (en) Wafer-level fan-out PoP encapsulation structure and making method thereof
CN107424938A (en) Encapsulating structure and its manufacture method
WO2021018014A1 (en) Tsv-based multi-chip package structure and method for manufacturing same
CN105655320B (en) Low-cost chip back silicon through hole interconnection structure and preparation method thereof
CN106206476A (en) Electronic package and manufacturing method thereof
CN106206509A (en) Electronic package, manufacturing method thereof and substrate structure
CN110400780A (en) A kind of fan-out-type stack package structure and preparation method thereof using metallic conduction post
CN107706520A (en) Fan-out-type antenna packages structure and preparation method thereof
CN112736031A (en) Interposer and method of manufacturing the same, semiconductor device and method of manufacturing the same
CN107507816A (en) Fan-out-type wafer scale multilayer wiring encapsulating structure
CN102544040B (en) Method utilizing TSV (Through-Silicon-Via) to realize wafer level package of GaAs (gallium arsenide) image sensor
CN102800633A (en) Semiconductor assembly structure and manufacturing method thereof
CN102646658A (en) Semiconductor package and method for manufacturing the same

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant